[AMDGPU] Disassembler: support for DPP

[SamWot]

Summary

Support for DPP instructions in disassembler.

[vpykhtin]

LGTM and one nit.

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

135

tryDecodeInst restores Bytes on failed attempt.

[SamWot]

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

135

It is still needed here because eatBytes<uint64_t>() eats 8 bytes and tryDecodeInst would not restore them. We need to restore Bytes from original Bytes_ stream.

[SamWot]

Submitted r265015

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

 #undef GET_SUBTARGETINFO_ENUM
 
 #include "AMDGPUGenDisassemblerTables.inc"
 
 //===----------------------------------------------------------------------===//
 //
 //===----------------------------------------------------------------------===//
 
-static inline uint32_t eatB32(ArrayRef<uint8_t>& Bytes) {
-  assert(Bytes.size() >= sizeof eatB32(Bytes));
-  const auto Res = support::endian::read32le(Bytes.data());
-  Bytes = Bytes.slice(sizeof Res);
+template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
+  assert(Bytes.size() >= sizeof T);
+  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
+  Bytes = Bytes.slice(sizeof T);
   return Res;
 }
 
 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
                                                MCInst &MI,
                                                uint64_t Inst,
                                                uint64_t Address) const {
   assert(MI.getOpcode() == 0);
DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 
   const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
   Bytes = Bytes_.slice(0, MaxInstBytesNum);
 
   DecodeStatus Res = MCDisassembler::Fail;
   do {
     // ToDo: better to switch encoding length using some bit predicate
     // but it is unknown yet, so try all we can
+    
+    // Try to decode DPP first to solve conflict with VOP1 and VOP2 encodings
+    if (Bytes.size() >= 8) {
+      const uint64_t QW = eatBytes<uint64_t>(Bytes);
+      Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
+      if (Res) break;
+    }
+
+    // Reinitialize Bytes as DPP64 could have eaten too much
+    Bytes = Bytes_.slice(0, MaxInstBytesNum);
+
+    // Try decode 32-bit instruction
     if (Bytes.size() < 4) break;
-    const uint32_t DW = eatB32(Bytes);
+    const uint32_t DW = eatBytes<uint32_t>(Bytes);
     Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
     if (Res) break;
 
     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
     if (Res) break;
 
     if (Bytes.size() < 4) break;
-    const uint64_t QW = ((uint64_t)eatB32(Bytes) << 32) | DW;
+    const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
     Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
     if (Res) break;
 
     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
   } while (false);
 
   Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
   return Res;

 
 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
   // For now all literal constants are supposed to be unsigned integer
   // ToDo: deal with signed/unsigned 64-bit integer constants
   // ToDo: deal with float/double constants
   if (Bytes.size() < 4)
     return errOperand(0, "cannot read literal, inst bytes left " +
                          Twine(Bytes.size()));
-  return MCOperand::createImm(eatB32(Bytes));
+  return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
 }
 
 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
   assert(Imm >= 128 && Imm <= 208);
   return MCOperand::createImm((Imm <= 192) ? (Imm - 128) : (192 - Imm));
 }
 
 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) {

lib/Target/AMDGPU/SIInstrInfo.td

multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
   def _vi : VOP1_Real_vi <opName, op, p.Outs, p.Ins32, asm>;
 
 }
 
 class VOP1_DPP <vop1 op, string opName, VOPProfile p> :
   VOP1_DPPe <op.VI>,
   VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "DPP";
+  let DisableDecoder = DisableVIDecoder;
   let src0_modifiers = !if(p.HasModifiers, ?, 0);
   let src1_modifiers = 0;
 }
 
 multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
                      string asm = opName#p.Asm32> {
 
   def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
multiclass VOP2_m <vop2 op, string opName, VOPProfile p, list <dag> pattern,
   def _vi : VOP2_Real_vi <opName, op, p.Outs32, p.Ins32, p.Asm32>;
 
 }
 
 class VOP2_DPP <vop2 op, string opName, VOPProfile p> :
   VOP2_DPPe <op.VI>,
   VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "DPP";
+  let DisableDecoder = DisableVIDecoder;
   let src0_modifiers = !if(p.HasModifiers, ?, 0);
   let src1_modifiers = !if(p.HasModifiers, ?, 0);
 }
 
 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
 
   bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
   bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);

test/MC/Disassembler/AMDGPU/dpp_vi.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x58,0x00,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x58 0x00 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x01 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x1f 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x2c,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x2c 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x30,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x30 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x34,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x34 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x38,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x38 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x3c 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x40,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x40 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x41,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x41 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x42 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x43 0x01 0xff
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xa1
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xaf
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xf1
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xff
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xa1
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xaf
+
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
+0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xf1
+
+# VI: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
+0xfa 0x0e 0x00 0x7e 0x00 0x01 0x09 0xa1
+
+# VI: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
+0xfa 0x36 0x00 0x7e 0x00 0x01 0x09 0xa1
+
+# VI: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
+0xfa 0x52 0x00 0x7e 0x00 0x01 0x09 0xa1
+
+# VI: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
+0xfa 0x00 0x00 0x02 0x00 0x01 0x09 0xa1
+
+# VI: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
+0xfa 0x00 0x00 0x14 0x00 0x01 0x09 0xa1
+
+# VI: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
+0xfa 0x00 0x00 0x26 0x00 0x01 0x09 0xa1
+
+# VI: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
+0xfa 0x00 0x00 0x02 0x00 0x01 0x19 0xa1
+
+# VI: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
+0xfa 0x00 0x00 0x02 0x00 0x01 0x89 0xa1
+
+# VI: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
+0xfa 0x00 0x00 0x02 0x00 0x01 0x99 0xa1
+
+# VI: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
+
+0xfa 0x00 0x00 0x02 0x00 0x01 0x69 0xa1
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