AMDGPU/SI: Optimize adjacent s_nop instructions

[• tstellarAMD]

Summary

Use the operand for how long to wait. This is somewhat
distasteful, since it would be better to just emit s_nop
with the right argument in the first place. This would require
changing TII::insertNoop to emit N operands, which would be easy.
Slightly more problematic is the post-RA scheduler and hazard recognizer
represent nops as a single null node, and would require inventing
another way of representing N nops.

Patch by: Matt Arsenault

[• tstellarAMD]

Ping.

[nhaehnle]

Looks mostly good, just one comment.

lib/Target/AMDGPU/SIShrinkInstructions.cpp

260–261

I think you need to guard against the case where Next == MBB.end() - in that case, NextMI.getOpcode() (or I guess technically already the assignment to NextMI) seems to invoke undefined behavior.

[• tstellarAMD]

Fix possible undefined behavior.

[nhaehnle]

LGTM

[arsenm]

r267456

lib/Target/AMDGPU/SIShrinkInstructions.cpp

bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
                                                   BI != BE; ++BI) {
 
     MachineBasicBlock &MBB = *BI;
     MachineBasicBlock::iterator I, Next;
     for (I = MBB.begin(); I != MBB.end(); I = Next) {
       Next = std::next(I);
       MachineInstr &MI = *I;
+      MachineInstr &NextMI = *Next;
 
       // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
       if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
         const MachineOperand &Src = MI.getOperand(1);
 
         if (Src.isImm()) {
           if (isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src, 4))
             MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
for (I = MBB.begin(); I != MBB.end(); I = Next) {
             if (ReverseImm >= -16 && ReverseImm <= 64) {
               MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
               Src.setImm(ReverseImm);
               continue;
             }
           }
         }
       }
+      // Combine adjacent s_nops to use the immediate operand encoding how long
+      // to wait.
+      //
+      // s_nop N
+      // s_nop M
+      //  =>
+      // s_nop (N + M)
+      if (MI.getOpcode() == AMDGPU::S_NOP &&
+          NextMI.getOpcode() == AMDGPU::S_NOP) {
+        // The instruction encodes the amount to wait with an offset of 1,
+        // i.e. 0 is wait 1 cycle. Convert both to cycles and then convert back
+        // after adding.
+        uint8_t Nop0 = MI.getOperand(0).getImm() + 1;
+        uint8_t Nop1 = NextMI.getOperand(0).getImm() + 1;
+
+        // Make sure we don't overflow the bounds.
+        if (Nop0 + Nop1 <= 8) {
+          NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1);
+          MI.eraseFromParent();
+        }
+
+        continue;
+      }
 
       if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
         continue;
 
       if (!canShrink(MI, TII, TRI, MRI)) {
         // Try commuting the instruction and see if that enables us to shrink
         // it.
         if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||