SelectionDAG: Fix a crash on inline asm when output register supports multiple types

[• tstellarAMD]

Summary

The code in SelectionDAG did not handle the case where the
register type and output types were different, but had the same size.

[arsenm]

test/CodeGen/AMDGPU/inline-asm.ll

50

Shouldn't this have an i1 return type?

[• tstellarAMD]

test/CodeGen/AMDGPU/inline-asm.ll

50

No, this test case comes from an inline asm implementation of hsail's activelanemask. I need to return a mask containing the true/false values for each thread. If I use i1, I will need to sign extend the value in order to store it, and I will get either 0 or -1 instead of the lane mask.

[arsenm]

test/CodeGen/AMDGPU/inline-asm.ll

50

Should probably add another testcase where it does use i1 then

[• tstellarAMD]

test/CodeGen/AMDGPU/inline-asm.ll

50

There is a different bug that prevents the i1 test from working, so I'll attach the test case to the fix for that bug.

[echristo]

Looks reasonable. Can you comment the function a bit as well so that the logic is more clear? (And commit when you've done so)

Thanks!

-eric

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
   if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
       ValueVT.bitsLT(PartEVT)) {
     // For an FP value in an integer part, we need to truncate to the right
     // width first.
     PartEVT = EVT::getIntegerVT(*DAG.getContext(),  ValueVT.getSizeInBits());
     Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
   }
 
+  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
+    return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
+
   if (PartEVT.isInteger() && ValueVT.isInteger()) {
     if (ValueVT.bitsLT(PartEVT)) {
       // For a truncate, see if we have any information to
       // indicate whether the truncated bits will always be
       // zero or sign-extension.
       if (AssertOp != ISD::DELETED_NODE)
         Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
                           DAG.getValueType(ValueVT));
       return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
     }
     return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
   }
 
   if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
     // FP_ROUND's are always exact here.
     if (ValueVT.bitsLT(Val.getValueType()))
       return DAG.getNode(
           ISD::FP_ROUND, DL, ValueVT, Val,
           DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
 
     return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
   }
 
-  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
-    return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
-
   llvm_unreachable("Unknown mismatch!");
 }
 
 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
                                               const Twine &ErrMsg) {
   const Instruction *I = dyn_cast_or_null<Instruction>(V);
   if (!V)
     return Ctx.emitError(ErrMsg);

test/CodeGen/AMDGPU/inline-asm.ll

 
 if:
   store i32 0, i32 addrspace(1)* %out
   br label %endif
 
 endif:
   ret void
 }
+
+; CHECK: {{^}}v_cmp_asm:
+; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
+; CHECK: v_cmp_ne_i32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]]
+; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
+; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]]
+; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
+define void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) {
+  %sgpr = tail call i64 asm "v_cmp_ne_i32_e64 $0, 0, $1", "=s,v"(i32 %in)
+  store i64 %sgpr, i64 addrspace(1)* %out
+  ret void
+}