AMDGPU/SI: Implement S_GETREG Intrinsic

[cfang]

Summary

S_GETREG is to read hardware registers.

[arsenm]

SC has some prettier syntax for the values being read, but that can be a separate patch

include/llvm/IR/IntrinsicsAMDGPU.td

221

This needs to be read only. In special cases the call site can be marked readnone

lib/Target/AMDGPU/SIInstructions.td

2076

You should be able to put this in the instruction definition

[cfang]

Update based on Matt's Comments:

1. Use "read only" attribute for s_getreg intrinsic;
2. Decided to use separate Pattern for the intrinsic temporarily.

[cfang]

update based on Matt's Comments

1. Create a new SOPK_32 multicalss, and rename the original one as SOPK_16 (so both are based on operand size);
2. Move the intrinsic s_getreg_b32 pattern inside the instruction definition;
3. Add checks for SI and CI devices in the test.

[arsenm]

LGTM

include/llvm/IR/IntrinsicsAMDGPU.td

   Intrinsic<[], [llvm_i32_ty], []> {
 }
 
+def int_amdgcn_s_getreg :
+  GCCBuiltin<"__builtin_amdgcn_s_getreg">,
+  Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem]>;
+
 def int_amdgcn_dispatch_ptr :
   GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">,
   Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], [IntrNoMem]>;

lib/Target/AMDGPU/SIInstructions.td

   sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs),
   (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
 >;
+
+let mayLoad = 1 in {
 defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>;
+}
+
 defm S_SETREG_B32 : SOPK_m <
   sopk<0x13, 0x12>, "s_setreg_b32", (outs),
   (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16"

 >;
 
 //===----------------------------------------------------------------------===//
+// S_GETREG_B32 Intrinsic Pattern.
+//===----------------------------------------------------------------------===//
+def : Pat <
+  (int_amdgcn_s_getreg imm:$simm16),
+  (S_GETREG_B32 (as_i16imm $simm16))
+>;
+
+//===----------------------------------------------------------------------===//
 // SMRD Patterns
 //===----------------------------------------------------------------------===//
 

test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll

+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
+
+; FUNC-LABEL: {{^}}s_getreg_test:
+; CHECK: s_getreg_b32 s{{[0-9]+}}, 0xb206
+define void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
+  %lds_size_64dwords = call i32 @llvm.amdgcn.s.getreg(i32 45574) #0
+  %lds_size_bytes = shl i32 %lds_size_64dwords, 8
+  store i32 %lds_size_bytes, i32 addrspace(1)* %out
+  ret void
+}
+
+declare i32 @llvm.amdgcn.s.getreg(i32) #0
+
+attributes #0 = { nounwind readonly}