[PPC64] Use mfocrf in prologue when we only need to save 1 nonvolatile CR field

[cycheng]

Summary

In the ELFv2 ABI, we are not required to save all CR fields. If only one nonvolatile CR field is clobbered, use mfocrf instead of mfcr to selectively save the field, because mfocrf has short latency compares to mfcr.

[nemanjai]

lib/Target/PowerPC/PPCFrameLowering.cpp

849

Do we not want to do this if we're serializing the CR/LR save sequences (i.e. when the prologue has a single scratch register available)? Perhaps define MfcrOpcode above and use it here as well.

test/CodeGen/PowerPC/crsave.ll

25

Do we not know which CR field we need to save here?

[cycheng]

• Also use MfcrOpcode checking in the CR/LR serializing case
• Only do this for ELFv2ABI
• Fix test case

lib/Target/PowerPC/PPCFrameLowering.cpp

849

Thanks : ) I fixed it.

By the way, I am curious about in which circumstance TempReg == ScratchReg? Because of shrink-wrapping?

test/CodeGen/PowerPC/crsave.ll

25

Yes we know it.

[nemanjai]

lib/Target/PowerPC/PPCFrameLowering.cpp

849

Yes. When we sink the prologue into the function for shrink wrapping and the BB has only one available register we use that register to save both the CR and the LR.

[kbarton]

LGTM

[cycheng]

Committed r266038.

lib/Target/PowerPC/PPCFrameLowering.cpp

void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   bool isLargeFrame = !isInt<16>(NegFrameSize);
 
   assert((isPPC64 || !MustSaveCR) &&
          "Prologue CR saving supported only in 64-bit mode");
 
   // If we need to spill the CR and the LR but we don't have two separate
   // registers available, we must spill them one at a time
   if (MustSaveCR && SingleScratchReg && MustSaveLR) {
-    // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
-    // If only one or two CR fields are clobbered, it could be more
-    // efficient to use mfocrf to selectively save just those fields.
+    // In the ELFv2 ABI, we are not required to save all CR fields.
+    // If only one or two CR fields are clobbered, it is more efficient to use
+    // mfocrf to selectively save just those fields, because mfocrf has short
+    // latency compares to mfcr.
+    unsigned MfcrOpcode = PPC::MFCR8;
+    if (isELFv2ABI && MustSaveCRs.size() == 1)
+      MfcrOpcode = PPC::MFOCRF8;
     MachineInstrBuilder MIB =
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
+      BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
       MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
     BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
       .addReg(TempReg, getKillRegState(true))
       .addImm(8)
       .addReg(SPReg);
   }
 
   if (MustSaveLR)
     BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
 
   if (MustSaveCR &&
       !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
-    // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
-    // If only one or two CR fields are clobbered, it could be more
-    // efficient to use mfocrf to selectively save just those fields.
+    // In the ELFv2 ABI, we are not required to save all CR fields.
+    // If only one or two CR fields are clobbered, it is more efficient to use
+    // mfocrf to selectively save just those fields, because mfocrf has short
+    // latency compares to mfcr.
+    unsigned MfcrOpcode = PPC::MFCR8;
+    if (isELFv2ABI && MustSaveCRs.size() == 1)
+      MfcrOpcode = PPC::MFOCRF8;
     MachineInstrBuilder MIB =
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
+      BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
       MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
   }
 
   if (HasFP)
     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
     BuildMI(MBB, MBBI, dl, StoreInst)
       .addReg(FPReg)

test/CodeGen/PowerPC/crsave.ll

 ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
+; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64-ELFv2
 
 declare void @foo()
 
 define i32 @test_cr2() nounwind uwtable {
 entry:
   %ret = alloca i32, align 4
   %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
   store i32 %0, i32* %ret, align 4
   call void @foo()
   %1 = load i32, i32* %ret, align 4
   ret i32 %1
 }
 
 ; PPC32: stw 31, -4(1)
 ; PPC32: stwu 1, -32(1)
 ; PPC32: mfcr 12
 ; PPC32-NEXT: stw 12, 24(31)
 ; PPC32: lwz 12, 24(31)
 ; PPC32-NEXT: mtocrf 32, 12
 
 ; PPC64: .cfi_startproc
 ; PPC64: mfcr 12
 ; PPC64: stw 12, 8(1)
 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
 ; PPC64: .cfi_def_cfa_offset 128
 ; PPC64: .cfi_offset lr, 16
 ; PPC64: .cfi_offset cr2, 8
 ; PPC64: addi 1, 1, [[AMT]]
 ; PPC64: lwz 12, 8(1)
 ; PPC64: mtocrf 32, 12

 ; PPC64: stw 12, 8(1)
 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
 ; PPC64: addi 1, 1, [[AMT]]
 ; PPC64: lwz 12, 8(1)
 ; PPC64: mtocrf 32, 12
 ; PPC64: mtocrf 16, 12
 ; PPC64: mtocrf 8, 12
 
+; Generate mfocrf in prologue when we need to save 1 nonvolatile CR field
+define void @cloberOneNvCrField() {
+entry:
+  tail call void asm sideeffect "# clobbers", "~{cr2}"()
+  ret void
+
+; PPC64-ELFv2-LABEL: @cloberOneNvCrField
+; PPC64-ELFv2: mfocrf [[REG1:[0-9]+]], 32
+}
+
+; Generate mfcr in prologue when we need to save all nonvolatile CR field
+define void @cloberAllNvCrField() {
+entry:
+  tail call void asm sideeffect "# clobbers", "~{cr2},~{cr3},~{cr4}"()
+  ret void
+
+; PPC64-ELFv2-LABEL: @cloberAllNvCrField
+; PPC64-ELFv2: mfcr [[REG1:[0-9]+]]
+}

test/CodeGen/PowerPC/pr26690.ll

 if.then15:                                        ; preds = %if.end13
   store i32 %p2, i32* %p1, align 4, !tbaa !1
   br label %if.end16
 
 if.end16:                                         ; preds = %entry, %if.end13, %if.then15
   ret i32 2
 }
 
-; CHECK: mfcr {{[0-9]+}}
+; CHECK: mfocrf {{[0-9]+}}
 
 !llvm.ident = !{!0}
 
 !0 = !{!"clang version 3.9.0 (trunk 261520)"}
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}
 !5 = !{!6, !6, i64 0}
 !6 = !{!"any pointer", !3, i64 0}
 !7 = !{!8, !2, i64 0}
 !8 = !{!"", !9, i64 0, !9, i64 4}
 !9 = !{!"", !2, i64 0}
 !10 = !{!8, !2, i64 4}