[WebAssembly] Insert COPY_LOCAL between CopyToReg and FrameIndex DAG nodes

[dschuff]

Summary

CopyToReg nodes don't support FrameIndex operands. Other targets select
the FI to some LEA-like instruction, but since we don't have that, we
need to insert some kind of instruction that can take an FI operand and
produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
copy_local between Op and its FI operand. This results in a redundant
copy which we should optimize away later (maybe in the post-FI-lowering
peephole pass).

[sunfish]

As you say, we may need to revisit this when we're ready to start optimizing this, but this looks good for now.

lib/Target/WebAssembly/WebAssemblyISelLowering.h

private:
   // Custom lowering hooks.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
 };
 
 namespace WebAssembly {
 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                          const TargetLibraryInfo *libInfo);
 }  // end namespace WebAssembly
 
 }  // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

for (auto T : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
 
   // Dynamic stack allocation: use the default expansion.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
 
   setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
+  setOperationAction(ISD::CopyToReg, MVT::Other, Custom);
 
   // Expand these forms; we pattern-match the forms that we can handle in isel.
   for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
     for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
       setOperationAction(Op, T, Expand);
 
   // We have custom switch handling.
   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
switch (Op.getOpcode()) {
     case ISD::ExternalSymbol:
       return LowerExternalSymbol(Op, DAG);
     case ISD::JumpTable:
       return LowerJumpTable(Op, DAG);
     case ISD::BR_JT:
       return LowerBR_JT(Op, DAG);
     case ISD::VASTART:
       return LowerVASTART(Op, DAG);
+    case ISD::CopyToReg:
+      return LowerCopyToReg(Op, DAG);
   }
 }
 
+SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SDValue Src = Op.getOperand(2);
+  if (isa<FrameIndexSDNode>(Src.getNode())) {
+    // CopyToReg nodes don't support FrameIndex operands. Other targets select
+    // the FI to some LEA-like instruction, but since we don't have that, we
+    // need to insert some kind of instruction that can take an FI operand and
+    // produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
+    // copy_local between Op and its FI operand.
+    SDLoc DL(Op);
+    EVT VT = Src.getValueType();
+    SDValue Copy(
+        DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_LOCAL_I32
+                                          : WebAssembly::COPY_LOCAL_I64,
+                           DL, VT, Src),
+        0);
+    return DAG.getCopyToReg(Op.getOperand(0), DL,
+                            cast<RegisterSDNode>(Op.getOperand(1))->getReg(),
+                            Copy);
+  }
+  return SDValue();
+}
+
 SDValue WebAssemblyTargetLowering::LowerFrameIndex(SDValue Op,
                                                    SelectionDAG &DAG) const {
   int FI = cast<FrameIndexSDNode>(Op)->getIndex();
   return DAG.getTargetFrameIndex(FI, Op.getValueType());
 }
 
 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
                                                       SelectionDAG &DAG) const {

lib/Target/WebAssembly/known_gcc_test_failures.txt

 # Tests which are known to fail from the GCC torture test suite.
 
-# InstrEmitter.cpp:302: unsigned int llvm::InstrEmitter::getVR(llvm::SDValue, DenseMap<llvm::SDValue, unsigned int> &): Assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' failed.
-20000801-2.c
-20000815-1.c
-20011126-2.c
-20030916-1.c
-20050826-2.c
-20090113-1.c
-920501-6.c
-930518-1.c
-980707-1.c
-990127-1.c
-loop-15.c
-loop-ivopts-2.c
-pr20466-1.c
-pr28778.c
-pr33870-1.c
-pr33870.c
-pr38051.c
-pr39100.c
-pr49390.c
-pr53645-2.c
-pr53645.c
-pr59643.c
-
-
-
 # WebAssemblyCFGStackify.cpp:438: void PlaceMarkers(llvm::MachineFunction&, const llvm::MachineLoopInfo&, const llvm::WebAssemblyInstrInfo&, llvm::MachineDominatorTree&): Assertion `ScopeTops[Stack.back()->getNumber()] == &MBB && "Block should be balanced"' failed.
 20090113-2.c
 20090113-3.c
 ashldi-1.c
 ashrdi-1.c
 builtin-bitops-1.c
 loop-11.c
+loop-15.c
 lshrdi-1.c
 mode-dependent-address.c
 va-arg-10.c
 
 
 # WebAssemblyCFGStackify.cpp:458: void PlaceMarkers(llvm::MachineFunction &, const llvm::MachineLoopInfo &, const llvm::WebAssemblyInstrInfo &, llvm::MachineDominatorTree &, llvm::WebAssemblyFunctionInfo &): Assertion `Stack.back() == &MBB && "Loop top should be balanced"' failed.
 930628-1.c
 

 va-arg-pack-1.c
 va-arg-22.c
 920908-1.c
 pr38151.c
 
 # include/llvm/CodeGen/SelectionDAGNodes.h:800: llvm::SDNode::SDNode(unsigned int, unsigned int, llvm::DebugLoc, llvm::SDVTList, ArrayRef<llvm::SDValue>): Assertion `NumOperands == Ops.size() && "NumOperands wasn't wide enough for its operands!"' failed.
 pr28982b.c
 
+# SelectionDAGNodes.h:943: llvm::SDValue::SDValue(llvm::SDNode *, unsigned int): Assertion `(!Node || ResNo < Node->getNumValues()) && "Invalid result number for the given node!"' failed.
+pr53645.c
+pr53645-2.c
+
+# multiple-entry loops are not supported yet.
+pr38051.c
 
 # Cannot select brind.
 20040302-1.c
 20071210-1.c
 920501-4.c
 920501-5.c
 
 # Cannot select BlockAddress.

test/CodeGen/WebAssembly/userstack.ll

  store i32 0, i32* %r
  ; CHECK: i32.const [[L3:.+]]=, 16
  ; CHECK: i32.add [[SP]]=, [[FP]], [[L3]]
  ; CHECK: i32.const [[L4:.+]]=, __stack_pointer
  ; CHECK-NEXT: i32.store [[SP]]=, 0([[L4]]), [[SP]]
  ret void
 }
 
+; The use of the alloca in a phi causes a CopyToReg DAG node to be generated,
+; which has to have special handling because CopyToReg can't have a FI operand
+; CHECK-LABEL: copytoreg_fi:
+define void @copytoreg_fi(i1 %cond, i32* %b) {
+entry:
+ ; CHECK: i32.const [[L2:.+]]=, 16
+ ; CHECK-NEXT: i32.sub [[SP:.+]]=, {{.+}}, [[L2]]
+ %addr = alloca i32
+ ; CHECK: i32.const [[OFF:.+]]=, 12
+ ; CHECK-NEXT: i32.add [[ADDR:.+]]=, [[SP]], [[OFF]]
+ ; CHECK-NEXT: copy_local [[COPY:.+]]=, [[ADDR]]
+ br label %body
+body:
+ %a = phi i32* [%addr, %entry], [%b, %body]
+ store i32 1, i32* %a
+ ; CHECK: i32.store {{.*}}, 0([[COPY]]),
+ br i1 %cond, label %body, label %exit
+exit:
+ ret void
+}
+
 ; TODO: test over-aligned alloca