AMDGPU/SI: Add llvm.amdgcn.mov.dpp intrinsic

[• tstellarAMD]

Summary

This intrinsic will be used to expose dpp functionality to higher-level
languages. It will map to the dpp version of v_mov_b32.

[arsenm]

include/llvm/IR/IntrinsicsAMDGPU.td

198–200

I was keeping VI only intrinsics somewhere near the bottom of the file. There should already be a VI only comment.

I've been meaning to clean this up to make it more obvious

201

Is this for i16/i32? I don't think there are any VOP2 i64 instructions

203

I think this needs to be convergent

[• tstellarAMD]

Add convergent attribute.

[• tstellarAMD]

include/llvm/IR/IntrinsicsAMDGPU.td

201

It's for i16/i32/i64, because it can be used for VOPC instructions as well as f64 instructions.

[arsenm]

LGTM with the test fixed

lib/Target/AMDGPU/VIInstructions.td

115–121

Is there a reason this needs to be a standalone pattern?

test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

12–14

Attributes in test are wrong

[• tstellarAMD]

lib/Target/AMDGPU/VIInstructions.td

115–121

This is likely the only dpp pattern, so I didn't think it was worth it to modify the existing VOP1Inst class and related classes so they would be able to accept dpp patterns.

include/llvm/IR/IntrinsicsAMDGPU.td

 
 def int_amdgcn_mbcnt_lo :
   GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">,
   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 
 def int_amdgcn_mbcnt_hi :
   GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">,
   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+
+// VI Only
+// llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <bound_ctrl> <bank_mask> <row_mask>
+def int_amdgcn_mov_dpp :
+  Intrinsic<[llvm_anyint_ty],
+            [LLVMMatchType<0>, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty,
+             llvm_i32_ty], [IntrNoMem]>;
+
 }

lib/Target/AMDGPU/VIInstructions.td

 let Predicates = [isVI] in {
 
 // 1. Offset as 20bit DWORD immediate
 def : Pat <
   (SIload_constant v4i32:$sbase, IMM20bit:$offset),
   (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
 >;
 
+//===----------------------------------------------------------------------===//
+// DPP Paterns
+//===----------------------------------------------------------------------===//
+
+def : Pat <
+  (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$bound_ctrl,
+                      imm:$bank_mask, imm:$row_mask),
+  (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i1imm $bound_ctrl),
+                       (as_i32imm $bank_mask), (as_i32imm $row_mask))
+>;
+
 } // End Predicates = [isVI]

test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
+
+; VI-LABEL: {{^}}dpp_test:
+; VI: v_mov_b32 v0, v0, 1, -1, 1, 1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
+define void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
+  %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i1 1, i32 1, i32 1) #0
+  store i32 %tmp0, i32 addrspace(1)* %out
+  ret void
+}
+
+declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i1, i32, i32) #0
+
+attributes #0 = { nounwind readnone }