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Differential D17018

AMDGPU: Match more med3 integer patterns
ClosedPublic

Authored by arsenm on Feb 8 2016, 7:58 PM.

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Reviewers
• tstellarAMD
nhaehnle

Diff Detail

Event Timeline

arsenm updated this revision to Diff 47292.Feb 8 2016, 7:58 PM
arsenm retitled this revision from to AMDGPU: Match more med3 integer patterns.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptFeb 8 2016, 7:58 PM
arsenm added parent revisions: D17016: SelectionDAG: Make min/max commutative and associative, D17017: SelectionDAG: Make Properties a field of SDPatternOperator.Feb 8 2016, 7:58 PM
arsenm updated this revision to Diff 47293.Feb 8 2016, 8:09 PM

Add a few tests for if exactly 1 operand is an immediate

nhaehnle accepted this revision.Feb 10 2016, 12:29 PM
nhaehnle added a reviewer: nhaehnle.
nhaehnle added a subscriber: nhaehnle.

LGTM

This revision is now accepted and ready to land.Feb 10 2016, 12:29 PM
arsenm closed this revision.Mar 7 2016, 1:59 PM

r262864

Revision Contents

PathSize
lib/
Target/
AMDGPU/
30 lines
3 lines
test/
CodeGen/
AMDGPU/
329 lines
329 lines

Diff 47292

lib/Target/AMDGPU/AMDGPUInstructions.td

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Linesdef COND_NE : PatLeaf <
[{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}] [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
>; >;
def COND_NULL : PatLeaf < def COND_NULL : PatLeaf <
(cond), (cond),
[{(void)N; return false;}] [{(void)N; return false;}]
>; >;
//===----------------------------------------------------------------------===//
// Misc. PatFrags
//===----------------------------------------------------------------------===//
class HasOneUseBinOp<SDPatternOperator op> : PatFrag<
(ops node:$src0, node:$src1),
(op $src0, $src1),
[{ return N->hasOneUse(); }]
>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Load/Store Pattern Fragments // Load/Store Pattern Fragments
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{ class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS; return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
}]>; }]>;
▲ Show 20 Lines • Show All 408 Lines • ▼ Show 20 Lines
>; >;
// rotr pattern // rotr pattern
class ROTRPattern <Instruction BIT_ALIGN> : Pat < class ROTRPattern <Instruction BIT_ALIGN> : Pat <
(rotr i32:$src0, i32:$src1), (rotr i32:$src0, i32:$src1),
(BIT_ALIGN $src0, $src0, $src1) (BIT_ALIGN $src0, $src0, $src1)
>; >;
// This matches 16 permutations of
// max(min(x, y), min(max(x, y), z))
class IntMed3Pat<Instruction med3Inst,
SDPatternOperator max,
SDPatternOperator max_oneuse,
SDPatternOperator min_oneuse> : Pat<
(max (min_oneuse i32:$src0, i32:$src1),
(min_oneuse (max_oneuse i32:$src0, i32:$src1), i32:$src2)),
(med3Inst $src0, $src1, $src2)
>;
let Properties = [SDNPCommutative, SDNPAssociative] in {
def smax_oneuse : HasOneUseBinOp<smax>;
def smin_oneuse : HasOneUseBinOp<smin>;
def umax_oneuse : HasOneUseBinOp<umax>;
def umin_oneuse : HasOneUseBinOp<umin>;
} // Properties = [SDNPCommutative, SDNPAssociative]
// 24-bit arithmetic patterns // 24-bit arithmetic patterns
def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>; def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
// Special conversion patterns // Special conversion patterns
def cvt_rpi_i32_f32 : PatFrag < def cvt_rpi_i32_f32 : PatFrag <
(ops node:$src), (ops node:$src),
(fp_to_sint (ffloor (fadd $src, FP_HALF))), (fp_to_sint (ffloor (fadd $src, FP_HALF))),
Show All 36 Lines

lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 3,181 Lines • ▼ Show 20 Lines
} // End Predicates = [isSI] } // End Predicates = [isSI]
//============================================================================// //============================================================================//
// Miscellaneous Optimization Patterns // Miscellaneous Optimization Patterns
//============================================================================// //============================================================================//
def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>; def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>;
//============================================================================// //============================================================================//
// Assembler aliases // Assembler aliases
//============================================================================// //============================================================================//
def : MnemonicAlias<"v_add_u32", "v_add_i32">; def : MnemonicAlias<"v_add_u32", "v_add_i32">;
def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
} // End isGCN predicate } // End isGCN predicate

test/CodeGen/AMDGPU/smed3.ll

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesdefine void @v_test_smed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
%icmp1 = icmp slt i16 %i0, 17 %icmp1 = icmp slt i16 %i0, 17
%i1 = select i1 %icmp1, i16 %i0, i16 17 %i1 = select i1 %icmp1, i16 %i0, i16 17
store i16 %i1, i16 addrspace(1)* %outgep store i16 %i1, i16 addrspace(1)* %outgep
ret void ret void
} }
define internal i32 @smin(i32 %x, i32 %y) #2 {
%cmp = icmp slt i32 %x, %y
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define internal i32 @smax(i32 %x, i32 %y) #2 {
%cmp = icmp sgt i32 %x, %y
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define internal i16 @smin16(i16 %x, i16 %y) #2 {
%cmp = icmp slt i16 %x, %y
%sel = select i1 %cmp, i16 %x, i16 %y
ret i16 %sel
}
define internal i16 @smax16(i16 %x, i16 %y) #2 {
%cmp = icmp sgt i16 %x, %y
%sel = select i1 %cmp, i16 %x, i16 %y
ret i16 %sel
}
define internal i8 @smin8(i8 %x, i8 %y) #2 {
%cmp = icmp slt i8 %x, %y
%sel = select i1 %cmp, i8 %x, i8 %y
ret i8 %sel
}
define internal i8 @smax8(i8 %x, i8 %y) #2 {
%cmp = icmp sgt i8 %x, %y
%sel = select i1 %cmp, i8 %x, i8 %y
ret i8 %sel
}
; 16 combinations
; 0: max(min(x, y), min(max(x, y), z))
; 1: max(min(x, y), min(max(y, x), z))
; 2: max(min(x, y), min(z, max(x, y)))
; 3: max(min(x, y), min(z, max(y, x)))
; 4: max(min(y, x), min(max(x, y), z))
; 5: max(min(y, x), min(max(y, x), z))
; 6: max(min(y, x), min(z, max(x, y)))
; 7: max(min(y, x), min(z, max(y, x)))
;
; + commute outermost max
; FIXME: In these cases we probably should have used scalar operations
; instead.
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_1:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_2:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_3:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_3(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_4:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_4(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_5:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_5(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_6:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_6(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_7:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_7(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_8:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_8(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_9:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_9(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_10:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_10(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_11:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_11(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_12:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_12(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_13:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_13(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_14:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_14(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_15:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_15(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i16_pat_0:
; GCN: s_sext_i32_i16
; GCN: s_sext_i32_i16
; GCN: s_sext_i32_i16
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i16_pat_0(i16 addrspace(1)* %arg, i16 %x, i16 %y, i16 %z) #1 {
bb:
%tmp0 = call i16 @smin16(i16 %x, i16 %y)
%tmp1 = call i16 @smax16(i16 %x, i16 %y)
%tmp2 = call i16 @smin16(i16 %tmp1, i16 %z)
%tmp3 = call i16 @smax16(i16 %tmp0, i16 %tmp2)
store i16 %tmp3, i16 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i8_pat_0:
; GCN: s_sext_i32_i8
; GCN: s_sext_i32_i8
; GCN: s_sext_i32_i8
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i8_pat_0(i8 addrspace(1)* %arg, i8 %x, i8 %y, i8 %z) #1 {
bb:
%tmp0 = call i8 @smin8(i8 %x, i8 %y)
%tmp1 = call i8 @smax8(i8 %x, i8 %y)
%tmp2 = call i8 @smin8(i8 %tmp1, i8 %z)
%tmp3 = call i8 @smax8(i8 %tmp0, i8 %tmp2)
store i8 %tmp3, i8 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_0:
; GCN-NOT: v_med3_i32
define void @s_test_smed3_i32_pat_0_multi_use_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp0, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_1:
; GCN-NOT: v_med3_i32
define void @s_test_smed3_i32_pat_0_multi_use_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp1, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_2:
; GCN-NOT: v_med3_i32
define void @s_test_smed3_i32_pat_0_multi_use_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp2, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_result:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_smed3_i32_pat_0_multi_use_result(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp3, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }
attributes #2 = { nounwind readnone alwaysinline }

test/CodeGen/AMDGPU/umed3.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesdefine void @v_test_umed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
%i0 = select i1 %icmp0, i16 %a, i16 12 %i0 = select i1 %icmp0, i16 %a, i16 12
%icmp1 = icmp ult i16 %i0, 17 %icmp1 = icmp ult i16 %i0, 17
%i1 = select i1 %icmp1, i16 %i0, i16 17 %i1 = select i1 %icmp1, i16 %i0, i16 17
store i16 %i1, i16 addrspace(1)* %outgep store i16 %i1, i16 addrspace(1)* %outgep
ret void ret void
} }
define internal i32 @umin(i32 %x, i32 %y) #2 {
%cmp = icmp ult i32 %x, %y
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define internal i32 @umax(i32 %x, i32 %y) #2 {
%cmp = icmp ugt i32 %x, %y
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define internal i16 @umin16(i16 %x, i16 %y) #2 {
%cmp = icmp ult i16 %x, %y
%sel = select i1 %cmp, i16 %x, i16 %y
ret i16 %sel
}
define internal i16 @umax16(i16 %x, i16 %y) #2 {
%cmp = icmp ugt i16 %x, %y
%sel = select i1 %cmp, i16 %x, i16 %y
ret i16 %sel
}
define internal i8 @umin8(i8 %x, i8 %y) #2 {
%cmp = icmp ult i8 %x, %y
%sel = select i1 %cmp, i8 %x, i8 %y
ret i8 %sel
}
define internal i8 @umax8(i8 %x, i8 %y) #2 {
%cmp = icmp ugt i8 %x, %y
%sel = select i1 %cmp, i8 %x, i8 %y
ret i8 %sel
}
; 16 combinations
; 0: max(min(x, y), min(max(x, y), z))
; 1: max(min(x, y), min(max(y, x), z))
; 2: max(min(x, y), min(z, max(x, y)))
; 3: max(min(x, y), min(z, max(y, x)))
; 4: max(min(y, x), min(max(x, y), z))
; 5: max(min(y, x), min(max(y, x), z))
; 6: max(min(y, x), min(z, max(x, y)))
; 7: max(min(y, x), min(z, max(y, x)))
;
; + commute outermost max
; FIXME: In these cases we probably should have used scalar operations
; instead.
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_1:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_2:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_3:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_3(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_4:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_4(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_5:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_5(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_6:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_6(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_7:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_7(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_8:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_8(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_9:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_9(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_10:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_10(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_11:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_11(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_12:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_12(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_13:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_13(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_14:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_14(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_15:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_15(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i16_pat_0:
; GCN: s_and_b32
; GCN: s_and_b32
; GCN: s_and_b32
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i16_pat_0(i16 addrspace(1)* %arg, i16 %x, i16 %y, i16 %z) #1 {
bb:
%tmp0 = call i16 @umin16(i16 %x, i16 %y)
%tmp1 = call i16 @umax16(i16 %x, i16 %y)
%tmp2 = call i16 @umin16(i16 %tmp1, i16 %z)
%tmp3 = call i16 @umax16(i16 %tmp0, i16 %tmp2)
store i16 %tmp3, i16 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i8_pat_0:
; GCN: s_and_b32
; GCN: s_and_b32
; GCN: s_and_b32
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i8_pat_0(i8 addrspace(1)* %arg, i8 %x, i8 %y, i8 %z) #1 {
bb:
%tmp0 = call i8 @umin8(i8 %x, i8 %y)
%tmp1 = call i8 @umax8(i8 %x, i8 %y)
%tmp2 = call i8 @umin8(i8 %tmp1, i8 %z)
%tmp3 = call i8 @umax8(i8 %tmp0, i8 %tmp2)
store i8 %tmp3, i8 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_0:
; GCN-NOT: v_med3_u32
define void @s_test_umed3_i32_pat_0_multi_use_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp0, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_1:
; GCN-NOT: v_med3_u32
define void @s_test_umed3_i32_pat_0_multi_use_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp1, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_2:
; GCN-NOT: v_med3_u32
define void @s_test_umed3_i32_pat_0_multi_use_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp2, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_result:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @s_test_umed3_i32_pat_0_multi_use_result(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
%tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2)
store volatile i32 %tmp3, i32 addrspace(1)* %arg
store volatile i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }
attributes #2 = { nounwind readnone alwaysinline }