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Differential D15951

AMDGPU: Emit functions sizes
ClosedPublic

Authored by • tstellarAMD on Jan 7 2016, 8:33 AM.

Details

Reviewers
arsenm
Commits
rGad8f5e811180: AMDGPU: Emit functions sizes
rL257172: AMDGPU: Emit functions sizes

Diff Detail

Event Timeline

• tstellarAMD updated this revision to Diff 44216.Jan 7 2016, 8:33 AM
• tstellarAMD retitled this revision from to AMDGPU: Emit functions sizes.
• tstellarAMD updated this object.
• tstellarAMD added a reviewer: arsenm.
• tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptJan 7 2016, 8:33 AM
• tstellarAMD added a child revision: D15953: Driver: Pass -flavor gnu to lld for AMDGPU rather than -flavor gnu-old.Jan 7 2016, 8:57 AM
arsenm added inline comments.Jan 7 2016, 10:16 AM
test/CodeGen/AMDGPU/hsa.ll
31

Should probably have a positive check Size: {{[1-9][0-9]?}}

• tstellarAMD updated this revision to Diff 44246.Jan 7 2016, 12:14 PM

Add positive check for size.

• tstellarAMD marked an inline comment as done.Jan 7 2016, 12:15 PM
arsenm accepted this revision.Jan 7 2016, 12:30 PM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 7 2016, 12:30 PM
Closed by commit rL257172: AMDGPU: Emit functions sizes (authored by tstellar). · Explain WhyJan 8 2016, 6:54 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
MCTargetDesc/
1 line
test/
CodeGen/
AMDGPU/
4 lines

Diff 44216

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

Show All 22 LinesAMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() {
//===--- Data Emission Directives -------------------------------------===// //===--- Data Emission Directives -------------------------------------===//
SunStyleELFSectionSwitchSyntax = true; SunStyleELFSectionSwitchSyntax = true;
UsesELFSectionDirectiveForBSS = true; UsesELFSectionDirectiveForBSS = true;
//===--- Global Variable Emission Directives --------------------------===// //===--- Global Variable Emission Directives --------------------------===//
HasAggressiveSymbolFolding = true; HasAggressiveSymbolFolding = true;
COMMDirectiveAlignmentIsInBytes = false; COMMDirectiveAlignmentIsInBytes = false;
HasDotTypeDotSizeDirective = false;
HasNoDeadStrip = true; HasNoDeadStrip = true;
WeakRefDirective = ".weakref\t"; WeakRefDirective = ".weakref\t";
//===--- Dwarf Emission Directives -----------------------------------===// //===--- Dwarf Emission Directives -----------------------------------===//
SupportsDebugInformation = true; SupportsDebugInformation = true;
} }
bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const { bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
return SectionName == ".hsatext" || SectionName == ".hsadata_global_agent" || return SectionName == ".hsatext" || SectionName == ".hsadata_global_agent" ||
SectionName == ".hsadata_global_program" || SectionName == ".hsadata_global_program" ||
SectionName == ".hsarodata_readonly_agent" || SectionName == ".hsarodata_readonly_agent" ||
MCAsmInfo::shouldOmitSectionDirective(SectionName); MCAsmInfo::shouldOmitSectionDirective(SectionName);
} }

test/CodeGen/AMDGPU/hsa.ll

Show All 22 Lines
; ELF: 0000: 04000000 08000000 01000000 414D4400 ; ELF: 0000: 04000000 08000000 01000000 414D4400
; ELF: 0010: 01000000 00000000 04000000 1B000000 ; ELF: 0010: 01000000 00000000 04000000 1B000000
; ELF: 0020: 03000000 414D4400 04000700 07000000 ; ELF: 0020: 03000000 414D4400 04000700 07000000
; ELF: 0030: 00000000 00000000 414D4400 414D4447 ; ELF: 0030: 00000000 00000000 414D4400 414D4447
; ELF: 0040: 50550000 ; ELF: 0040: 50550000
; ELF: Symbol { ; ELF: Symbol {
; ELF: Name: simple ; ELF: Name: simple
; ELF-NOT: Size: 0
arsenmUnsubmitted
Done
ReplyInline Actions

Should probably have a positive check Size: {{[1-9][0-9]?}}

arsenm: Should probably have a positive check Size: {{[1-9][0-9]?}}
; ELF: Type: AMDGPU_HSA_KERNEL (0xA) ; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
; ELF: } ; ELF: }
; HSA: .hsa_code_object_version 1,0 ; HSA: .hsa_code_object_version 1,0
; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
; HSA: .hsatext ; HSA: .hsatext
; HSA: .amdgpu_hsa_kernel simple ; HSA: .amdgpu_hsa_kernel simple
; HSA: {{^}}simple: ; HSA: {{^}}simple:
; HSA: .amd_kernel_code_t ; HSA: .amd_kernel_code_t
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
; HSA: .end_amd_kernel_code_t ; HSA: .end_amd_kernel_code_t
; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 ; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
; Make sure we are setting the ATC bit: ; Make sure we are setting the ATC bit:
; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000 ; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
; On VI+ we also need to set MTYPE = 2 ; On VI+ we also need to set MTYPE = 2
; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000 ; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
; Make sure we generate flat store for HSA ; Make sure we generate flat store for HSA
; HSA: flat_store_dword v{{[0-9]+}} ; HSA: flat_store_dword v{{[0-9]+}}
; HSA: .Lfunc_end0:
; HSA: .size simple, .Lfunc_end0-simple
define void @simple(i32 addrspace(1)* %out) { define void @simple(i32 addrspace(1)* %out) {
entry: entry:
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
ret void ret void
} }