[AArch64] Fixing broken tests when post RA Scheduler is enabled

[mcrosier]

Summary

This revision is not for upstreaming, but to help the reviewers of http://reviews.llvm.org/D15652.

[mcrosier]

Thanks, @MinSeongKIM. This was very helpful. It looks as though non of the tests required strict ordering, so adding the flag to disable the post-ra scheduler was fine. The associated change was committed in r256158.

lib/Target/AArch64/AArch64Subtarget.h

   const Triple &getTargetTriple() const { return TargetTriple; }
   bool enableMachineScheduler() const override { return true; }
   bool enablePostRAScheduler() const override {
-    return isCortexA53() || isCortexA57();
+    return isGeneric() || isCortexA53() || isCortexA57();
   }
 
   bool hasV8_1aOps() const { return HasV8_1aOps; }

   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
+  bool isGeneric() const { return CPUString == "generic"; }
   bool isCyclone() const { return CPUString == "cyclone"; }
   bool isCortexA57() const { return CPUString == "cortex-a57"; }
   bool isCortexA53() const { return CPUString == "cortex-a53"; }

test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

 ; CHECK: .cfi_offset w29, -16
 ; CHECK: .cfi_offset w19, -24
 ; CHECK: .cfi_offset w20, -32
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+; CHECK: mov  w9, w0
 ;   Check correct access to arguments passed on the stack, through frame pointer
 ; CHECK: ldr  w[[IARG:[0-9]+]], [x29, #24]
 ; CHECK: ldr  d[[DARG:[0-9]+]], [x29, #40]
-;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
-; CHECK: mov  w9, w0
-; CHECK: mov   x10, sp
 ; CHECK: lsl  x9, x9, #2
 ; CHECK: add  x9, x9, #15
+; CHECK: mov  x10, sp
 ; CHECK: and  x9, x9, #0x7fffffff0
 ; CHECK: sub   x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov   sp, x[[VLASPTMP]]

 ;   Check that space is reserved on the stack for the local variable,
 ;   rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned.
 ; CHECK: sub  sp, sp, #16
+;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
+; CHECK: mov  w9, w0
 ;   Check correctness of cfi pseudo-instructions
 ;   Check correct access to arguments passed on the stack, through frame pointer
 ; CHECK: ldr  w[[IARG:[0-9]+]], [x29, #24]
 ; CHECK: ldr  d[[DARG:[0-9]+]], [x29, #40]
-;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
-; CHECK: mov  w9, w0
-; CHECK: mov   x10, sp
 ; CHECK: lsl  x9, x9, #2
 ; CHECK: add  x9, x9, #15
+; CHECK: mov   x10, sp
 ; CHECK: and  x9, x9, #0x7fffffff0
 ; CHECK: sub   x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov   sp, x[[VLASPTMP]]

 ; CHECK: .cfi_offset w20, -32
 ; CHECK: .cfi_offset w21, -40
 ; CHECK: .cfi_offset w22, -48
-;   Check correct access to arguments passed on the stack, through frame pointer
-; CHECK: ldr  w[[IARG:[0-9]+]], [x29, #24]
-; CHECK: ldr  d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
 ;   and set-up of base pointer (x19).
 ; CHECK: mov  w9, w0
-; CHECK: mov   x10, sp
+;   Check correct access to arguments passed on the stack, through frame pointer
+; CHECK: ldr  w[[IARG:[0-9]+]], [x29, #24]
+; CHECK: ldr  d[[DARG:[0-9]+]], [x29, #40]
 ; CHECK: lsl  x9, x9, #2
 ; CHECK: add  x9, x9, #15
+; CHECK: mov   x10, sp
 ; CHECK: and  x9, x9, #0x7fffffff0
 ; CHECK: sub   x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov   sp, x[[VLASPTMP]]

 ;   spill slots
 ; CHECK: sub  x9, sp, #96
 ; CHECK: and  sp, x9, #0xffffffffffffff80
-; CHECK: mov    x19, sp
+; CHECK: mov  w9, w0
 ;   Check correct access to arguments passed on the stack, through frame pointer
 ; CHECK: ldr  w[[IARG:[0-9]+]], [x29, #24]
 ; CHECK: ldr  d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
 ;   and set-up of base pointer (x19).
-; CHECK: mov  w9, w0
-; CHECK: mov   x10, sp
 ; CHECK: lsl  x9, x9, #2
 ; CHECK: add  x9, x9, #15
+; CHECK: mov   x10, sp
 ; CHECK: and  x9, x9, #0x7fffffff0
+; CHECK: mov    x19, sp
 ; CHECK: sub   x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov   sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through base pointer

 ; CHECK-LABEL: vla_dynamicrealign_nocall_large_align
 ;   Check that used callee-saved registers are saved
 ; CHECK: stp  x20, x19, [sp, #-32]!
+; CHECK: sub  x9, sp, #7, lsl #12
 ;   Check that the frame pointer is created:
 ; CHECK: stp  x29, x30, [sp, #16]
 ; CHECK: add  x29, sp, #16

 ;   bytes & the base pointer (x19) gets initialized to
 ;   this 128-byte aligned area for local variables &
 ;   spill slots
-; CHECK: sub  x9, sp, #7, lsl #12
 ; CHECK: and  sp, x9, #0xffffffffffff8000
-; CHECK: mov    x19, sp
+; CHECK: mov  w9, w0
 ;   Check correct access to arguments passed on the stack, through frame pointer
 ; CHECK: ldr  w[[IARG:[0-9]+]], [x29, #24]
 ; CHECK: ldr  d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
 ;   and set-up of base pointer (x19).
-; CHECK: mov  w9, w0
-; CHECK: mov   x10, sp
 ; CHECK: lsl  x9, x9, #2
 ; CHECK: add  x9, x9, #15
+; CHECK: mov   x10, sp
 ; CHECK: and  x9, x9, #0x7fffffff0
+; CHECK: mov    x19, sp
 ; CHECK: sub   x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov   sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through base pointer

test/CodeGen/AArch64/alloca.ll

   %buf = alloca i8, i64 %n
   ; Make sure we align the stack change to 16 bytes:
 ; CHECK: {{mov|add}} x29
-; CHECK: mov [[TMP:x[0-9]+]], sp
 ; CHECK: add [[SPDELTA_TMP:x[0-9]+]], x0, #15
+; CHECK: mov [[TMP:x[0-9]+]], sp
 ; CHECK: and [[SPDELTA:x[0-9]+]], [[SPDELTA_TMP]], #0xfffffffffffffff0
 
   ; Make sure we change SP. It would be surprising if anything but x0 were used

   %loc = alloca i64
   %buf = alloca i8, i64 %n
   ; Make sure we align the stack change to 16 bytes:
-; CHECK: mov [[TMP:x[0-9]+]], sp
 ; CHECK: add [[SPDELTA_TMP:x[0-9]+]], x0, #15
+; CHECK: mov [[TMP:x[0-9]+]], sp
 ; CHECK: and [[SPDELTA:x[0-9]+]], [[SPDELTA_TMP]], #0xfffffffffffffff0
 
   ; Make sure we change SP. It would be surprising if anything but x0 were used

 ; [...]
 ; CHECK: stp     x2, x3, [x29, #-48]
 
+; CHECK-NOFP-ARM64: mov     x8, sp
 ; CHECK-NOFP-ARM64: stp     x29, x30, [sp, #-16]!
 ; CHECK-NOFP-ARM64: mov     x29, sp
 ; CHECK-NOFP-ARM64: sub     sp, sp, #64

 ; [...]
 ; CHECK-NOFP-ARM64: stp     x2, x3, [x29, #-48]
 ; [...]
-; CHECK-NOFP-ARM64: mov     x8, sp
 
   %addr = alloca i8, i64 %n
 

 ; CHECK-LABEL: test_scoped_alloca:
 
   %sp = call i8* @llvm.stacksave()
-; CHECK: mov [[SAVED_SP:x[0-9]+]], sp
 ; CHECK: mov [[OLDSP:x[0-9]+]], sp
 
   %addr = alloca i8, i64 %n
 ; CHECK: and [[SPDELTA:x[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
+; CHECK: mov [[SAVED_SP:x[0-9]+]], sp
 ; CHECK-DAG: sub [[NEWSP:x[0-9]+]], [[OLDSP]], [[SPDELTA]]
 ; CHECK: mov sp, [[NEWSP]]
 

test/CodeGen/AArch64/arm64-aapcs.ll

 ; CHECK-LABEL: @test_i128_align
 define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
   store i32 %after, i32* @var, align 4
-; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
-
   ret i128 %arg
 ; CHECK: mov x0, x2
 ; CHECK: mov x1, x3
+; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
 }
 
 ; CHECK-LABEL: @test_i64x2_align
 define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
   store i32 %after, i32* @var, align 4
-; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
-
   ret [2 x i64] %arg
 ; CHECK: mov x0, x1
 ; CHECK: mov x1, x2
+; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
 }
 
 @var64 = global i64 0, align 8

test/CodeGen/AArch64/arm64-hello.ll

 ; CHECK:  stp x29, x30, [sp, #-16]!
 ; CHECK-NEXT: mov x29, sp
 ; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: stur  wzr, [x29, #-4]
 ; CHECK:  adrp  x0, L_.str@PAGE
 ; CHECK:  add x0, x0, L_.str@PAGEOFF
+; CHECK-NEXT: stur  wzr, [x29, #-4]
 ; CHECK-NEXT: bl  _puts
 ; CHECK-NEXT: mov sp, x29
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 ; CHECK-LINUX:  stp x29, x30, [sp, #-16]!
 ; CHECK-LINUX-NEXT: mov x29, sp
 ; CHECK-LINUX-NEXT: sub sp, sp, #16
-; CHECK-LINUX-NEXT: stur  wzr, [x29, #-4]
 ; CHECK-LINUX:  adrp  x0, .L.str
 ; CHECK-LINUX:  add x0, x0, :lo12:.L.str
+; CHECK-LINUX-NEXT: stur  wzr, [x29, #-4]
 ; CHECK-LINUX-NEXT: bl  puts
 ; CHECK-LINUX-NEXT: mov sp, x29
 ; CHECK-LINUX-NEXT: ldp x29, x30, [sp], #16

test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

 define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2) {
 ; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load:
 ; CHECK: BB#0:
-; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
 ; CHECK-NEXT: movi.2d v0, #0000000000000000
+; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
 ; CHECK-NEXT: str q0, [x3]
 ; CHECK-NEXT: ldr q0, [x4]
-; CHECK-NEXT: ins.s v0[1], v[[LD]][0]
 ; CHECK-NEXT: add [[POST:x[0-9]]], x0, x2, lsl #2
 ; CHECK-NEXT: str [[POST]], [x1]
+; CHECK-NEXT: ins.s v0[1], v[[LD]][0]
 ; CHECK-NEXT: ret
   %tmp1 = load float, float* %bar
   store <4 x float> zeroinitializer, <4 x float>* %dep_ptr_1, align 16

test/CodeGen/AArch64/arm64-inline-asm.ll

 
 define void @test_zero_reg(i32* %addr) {
 ; CHECK-LABEL: test_zero_reg:
+; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1
 
   tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind
 ; CHECK: USE(xzr)

 ; CHECK: USE(wzr)
 
   tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1)
-; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1
 ; CHECK: USE([[VAL1]])
 
   tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind

test/CodeGen/AArch64/arm64-large-frame.ll

 
 
 ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
+; CHECK: add [[TMP2:x[0-9]+]], sp, #4095, lsl #12
 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
+; CHECK: add [[TMP3:x[0-9]+]], [[TMP2]], #787, lsl #12
 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
+; CHECK: add {{x[0-9]+}}, [[TMP3]], #3328
   store volatile i8* %var1, i8** @addr
 
   %var1plus2 = getelementptr i8, i8* %var1, i32 2
   store volatile i8* %var1plus2, i8** @addr
 
-; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
-; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
-; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
   store volatile i8* %var2, i8** @addr
 
   %var2plus2 = getelementptr i8, i8* %var2, i32 2

 ; CHECK-NEXT: sub sp, sp, #1168
 
   store volatile i8* %var1, i8** @addr
-; CHECK: add     [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
-; CHECK: add     [[VAR1ADDR]], [[VAR1ADDR]], #592
-
+; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
 ; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12
+; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #592
 ; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #576
 
   store volatile i8* %var2, i8** @addr

test/CodeGen/AArch64/arm64-shrink-wrapping.ll

 ;
 ; Next BB.
 ; Copy SUM into the returned register + << 3.
-; CHECK: lsl w0, [[SUM]], #3
 ;
 ; Jump to epilogue.
 ; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]

 ;
 ; Epilogue code.
 ; CHECK: ldp [[CSR3]], [[CSR4]], [sp, #16]
-; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK: ldp [[CSR1]], [[CSR2]], [sp], #32
 ; CHECK-NEXT: ret
 ;
 ; ENABLE: [[ELSE_LABEL]]: ; %if.else

 ; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
 ; Next BB.
 ; CHECK: ; %for.end
-; CHECK: mov w0, [[SUM]]
 ; CHECK-NEXT: ldp [[CSR3]], [[CSR4]], [sp, #16]
+; CHECK: mov w0, [[SUM]]
 ; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
 ; CHECK-NEXT: ret
 define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {

 ; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
 ; Next BB.
 ; CHECK: bl _somethingElse
-; CHECK-NEXT: lsl w0, [[SUM]], #3
 ;
 ; Jump to epilogue.
 ; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]

 ; DISABLE: [[EPILOG_BB]]: ; %if.end
 ; Epilogue code.
 ; CHECK-NEXT: ldp [[CSR3]], [[CSR4]], [sp, #16]
-; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK: ldp [[CSR1]], [[CSR2]], [sp], #32
 ; CHECK-NEXT: ret
 ;
 ; ENABLE: [[ELSE_LABEL]]: ; %if.else

 ; CHECK-NEXT: sub [[IV]], [[IV]], #1
 ; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
 ; Next BB.
-; CHECK: lsl w0, [[SUM]], #3
 ;
 ; Jump to epilogue.
 ; DISABLE: b [[EPILOG_BB:LBB[0-9_]+]]

 ; DISABLE: [[EPILOG_BB]]: ; %if.end
 ; Epilogue code.
 ; CHECK: ldp [[CSR3]], [[CSR4]], [sp, #16]
-; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #32
+; CHECK: ldp [[CSR1]], [[CSR2]], [sp], #32
 ; CHECK-NEXT: ret
 ;
 ; ENABLE: [[ELSE_LABEL]]: ; %if.else

 ;
 ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
 ; CHECK: ldr [[VA_ADDR:x[0-9]+]], [sp, #8]
+; CHECK-NEXT: sub w1, w1, #1
 ; CHECK-NEXT: add [[NEXT_VA_ADDR:x[0-9]+]], [[VA_ADDR]], #8
 ; CHECK-NEXT: str [[NEXT_VA_ADDR]], [sp, #8]
 ; CHECK-NEXT: ldr [[VA_VAL:w[0-9]+]], {{\[}}[[VA_ADDR]]]
 ; CHECK-NEXT: add [[SUM]], [[SUM]], [[VA_VAL]]
-; CHECK-NEXT: sub w1, w1, #1
 ; CHECK-NEXT: cbnz w1, [[LOOP_LABEL]]
 ;
 ; DISABLE-NEXT: b [[IFEND_LABEL]]

 ;
 ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
 ; Inline asm statement.
-; CHECK: add x19, x19, #1
 ; CHECK: sub [[IV]], [[IV]], #1
-; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
+; CHECK: add x19, x19, #1
+; CHECK: cbnz [[IV]], [[LOOP_LABEL]]
 ; Next BB.
 ; CHECK: mov w0, wzr
 ; Epilogue code.

 ;
 ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]]
 ; Setup of the varags.
+; CHECK: mov w0, w1
 ; CHECK: stp x1, x1, [sp, #32]
 ; CHECK-NEXT: stp x1, x1, [sp, #16]
 ; CHECK-NEXT: stp x1, x1, [sp]
-; CHECK-NEXT: mov w0, w1
 ; CHECK-NEXT: bl _someVariadicFunc
 ; CHECK-NEXT: lsl w0, w0, #3
 ;

test/CodeGen/AArch64/arm64-trunc-store.ll

 ; CHECK: fct32
 ; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr32@GOTPAGE
 ; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr32@GOTPAGEOFF]
-; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
 ; w0 is %arg
 ; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
+; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
 ; w1 is %var truncated
 ; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2]
 ; CHECK-NEXT: ret

 ; CHECK: fct16
 ; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr16@GOTPAGE
 ; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr16@GOTPAGEOFF]
-; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
 ; w0 is %arg
 ; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
+; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
 ; w1 is %var truncated
 ; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1]
 ; CHECK-NEXT: ret

test/CodeGen/AArch64/arm64-variadic-aapcs.ll

 define void @test_simple(i32 %n, ...) {
 ; CHECK-LABEL: test_simple:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
-
 ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
+; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
 ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
 ; CHECK: stp x1, x2, [sp, #[[GR_BASE:[0-9]+]]]

 define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 ; CHECK-LABEL: test_fewargs:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
-
 ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
+; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
 ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
 ; CHECK: stp x3, x4, [sp, #[[GR_BASE:[0-9]+]]]

 
 ; CHECK: stp q1, q2, [sp]
 ; ... omit middle ones ...
-; CHECK: str q7, [sp, #
-
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
-
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40
+; CHECK: str q7, [sp, #
 ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp

test/CodeGen/AArch64/arm64-xaluo.ll

 entry:
 ; CHECK-LABEL:  umulo.i64
 ; CHECK:        umulh [[MREG:x[0-9]+]], x0, x1
-; CHECK-NEXT:   cmp xzr, [[MREG]]
+; CHECK:        cmp xzr, [[MREG]]
 ; CHECK-NEXT:   cset {{w[0-9]+}}, ne
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0

test/CodeGen/AArch64/atomic-ops.ll

    %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic
    %old = extractvalue { i32, i1 } %pair, 0
 
-; CHECK: mov {{[xw]}}[[WANTED:[0-9]+]], {{[xw]}}0
-
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: mov {{[xw]}}[[WANTED:[0-9]+]], {{[xw]}}0
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:

test/CodeGen/AArch64/bitcast-v2i8.ll

 
 define i16 @test_bitcast_v2i8_to_i16(<2 x i8> %a) {
 ; CHECK-LABEL: test_bitcast_v2i8_to_i16
+; CHECK:      fmov    [[WREG_LO:w[0-9]+]], s0
 ; CHECK:      mov.s   [[WREG_HI:w[0-9]+]], v0[1]
-; CHECK-NEXT: fmov    [[WREG_LO:w[0-9]+]], s0
-; CHECK-NEXT: strb    [[WREG_HI]], [sp, #15]
 ; CHECK-NEXT: strb    [[WREG_LO]], [sp, #14]
+; CHECK-NEXT: strb    [[WREG_HI]], [sp, #15]
 ; CHECK-NEXT: ldrh    w0, [sp, #14]
 
   %aa = bitcast <2 x i8> %a to i16

test/CodeGen/AArch64/dag-combine-select.ll

 ; CHECK-LABEL: test1:
 ; CHECK-NOT: ccmp
 ; CHECK: cmp w0, #7
-; CHECK: adrp x[[OUTNUM:[0-9]+]], out
 ; CHECK: csel w[[SEL0NUM:[0-9]+]], w1, w2, eq
 ; CHECK: cmp w[[SEL0NUM]], #13
 ; CHECK: csel w[[SEL1NUM:[0-9]+]], w1, w2, lo
 ; CHECK: cmp w0, #42
+; CHECK: adrp x[[OUTNUM:[0-9]+]], out
 ; CHECK: csel w[[SEL2NUM:[0-9]+]], w1, w[[SEL1NUM]], eq
 ; CHECK: str w[[SEL1NUM]], [x[[OUTNUM]], :lo12:out]
 ; CHECK: str w[[SEL2NUM]], [x[[OUTNUM]], :lo12:out]

test/CodeGen/AArch64/f16-instructions.ll

 
 ; CHECK-LABEL: test_frem:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
 ; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}fmodf
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_call_flipped:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: mov.16b  v2, v0
 ; CHECK-NEXT: mov.16b  v0, v1
 ; CHECK-NEXT: mov.16b  v1, v2
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}test_callee
 ; CHECK-NEXT: ldp x29, x30, [sp], #16
 ; CHECK-NEXT: ret

 
 ; CHECK-LABEL: test_powi:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}__powisf2
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_sin:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}sinf
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_cos:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}cosf
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_pow:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
 ; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}powf
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_exp:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}expf
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_exp2:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}exp2f
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_log:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}logf
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_log10:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}log10f
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

 
 ; CHECK-LABEL: test_log2:
 ; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: mov  x29, sp
 ; CHECK-NEXT: bl {{_?}}log2f
 ; CHECK-NEXT: fcvt h0, s0
 ; CHECK-NEXT: ldp x29, x30, [sp], #16

test/CodeGen/AArch64/func-argpassing.ll

 ; CHECK-LABEL: check_i128_regalign
     store i128 %val1, i128* @var128
 ; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
+; CHECK: mov x0, x4
 ; CHECK-DAG: stp x2, x3, [x[[VAR128]]]
 
     ret i64 %val2
-; CHECK: mov x0, x4
 }
 
 define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,

test/CodeGen/AArch64/global-merge-3.ll

 
 define void @f1(i32 %a1, i32 %a2, i32 %a3) {
 ;CHECK-APPLE-IOS: adrp  x8, l__MergedGlobals@PAGE
-;CHECK-APPLE-IOS-NOT: adrp
-;CHECK-APPLE-IOS: add x8, x8, l__MergedGlobals@PAGEOFF
 ;CHECK-APPLE-IOS: adrp  x9, l__MergedGlobals.1@PAGE
+;CHECK-APPLE-IOS: add x8, x8, l__MergedGlobals@PAGEOFF
 ;CHECK-APPLE-IOS: add x9, x9, l__MergedGlobals.1@PAGEOFF
   %x3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @x, i32 0, i64 3
   %y3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @y, i32 0, i64 3

test/CodeGen/AArch64/nest-register.ll

 define i8* @nest_caller(i8* %arg) nounwind {
 ; CHECK-LABEL: nest_caller:
 ; CHECK: mov x18, x0
-; CHECK-NEXT: bl nest_receiver
+; CHECK: bl nest_receiver
 ; CHECK: ret
 
   %result = call i8* @nest_receiver(i8* nest %arg)

test/CodeGen/AArch64/nontemporal.ll

 
 define void @test_stnp_v4f32_offset_alloca(<4 x float> %v) #0 {
 ; CHECK-LABEL: test_stnp_v4f32_offset_alloca:
-; CHECK:       stnp d0, d{{.*}}, [sp]
-; CHECK-NEXT:  mov x0, sp
+; CHECK:       mov x0, sp
+; CHECK-NEXT:  stnp d0, d{{.*}}, [sp]
 ; CHECK-NEXT:  bl _dummy
   %tmp0 = alloca <4 x float>
   store <4 x float> %v, <4 x float>* %tmp0, align 1, !nontemporal !0

 
 define void @test_stnp_v4f32_offset_alloca_2(<4 x float> %v) #0 {
 ; CHECK-LABEL: test_stnp_v4f32_offset_alloca_2:
-; CHECK:       stnp d0, d{{.*}}, [sp, #16]
-; CHECK-NEXT:  mov x0, sp
+; CHECK:       mov x0, sp
+; CHECK-NEXT:  stnp d0, d{{.*}}, [sp, #16]
 ; CHECK-NEXT:  bl _dummy
   %tmp0 = alloca <4 x float>, i32 2
   %tmp1 = getelementptr <4 x float>, <4 x float>* %tmp0, i32 1

test/CodeGen/AArch64/tailcall-explicit-sret.ll

 ; CHECK: ldr [[PTRLOAD1:x[0-9]+]], [x0]
 ; CHECK: str [[PTRLOAD1]], [sp]
 ; CHECK: mov  x8, sp
-; CHECK-NEXT: bl _test_explicit_sret
+; CHECK: bl _test_explicit_sret
 ; CHECK: ret
 define void @test_tailcall_explicit_sret_alloca_dummyusers(i1024* %ptr) #0 {
   %l = alloca i1024, align 8

 
 ; CHECK-LABEL: _test_tailcall_explicit_sret_gep:
 ; CHECK: add  x8, x0, #128
-; CHECK-NEXT: bl _test_explicit_sret
+; CHECK: bl _test_explicit_sret
 ; CHECK: ret
 define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 {
   %ptr2 = getelementptr i1024, i1024* %ptr, i32 1

 }
 
 ; CHECK-LABEL: _test_indirect_tailcall_explicit_sret_nosret_arg:
-; CHECK-DAG: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK-DAG: mov  [[FPTR:x[0-9]+]], x0
 ; CHECK: mov  x0, sp
+; CHECK-DAG: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK-NEXT: blr [[FPTR]]
 ; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
 ; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]

test/CodeGen/AArch64/vector-fcopysign.ll

 ; WidenVecOp #1
 define <1 x double> @test_copysign_v1f64_v1f32(<1 x double> %a, <1 x float> %b) #0 {
 ; CHECK-LABEL: test_copysign_v1f64_v1f32:
-; CHECK-NEXT:    fcvt d1, s1
 ; CHECK-NEXT:    movi.2d v2, #0000000000000000
+; CHECK-NEXT:    fcvt d1, s1
 ; CHECK-NEXT:    fneg.2d v2, v2
 ; CHECK-NEXT:    bit.16b v0, v1, v2
 ; CHECK-NEXT:    ret

 ; SplitVecOp #1
 define <4 x float> @test_copysign_v4f32_v4f64(<4 x float> %a, <4 x double> %b) #0 {
 ; CHECK-LABEL: test_copysign_v4f32_v4f64:
-; CHECK-NEXT:    mov s3, v0[1]
 ; CHECK-NEXT:    mov d4, v1[1]
 ; CHECK-NEXT:    movi.4s v5, #0x80, lsl #24
 ; CHECK-NEXT:    fcvt s1, d1
+; CHECK-NEXT:    mov s3, v0[1]
 ; CHECK-NEXT:    mov s6, v0[2]
 ; CHECK-NEXT:    mov s7, v0[3]
-; CHECK-NEXT:    fcvt s16, d2
 ; CHECK-NEXT:    bit.16b v0, v1, v5
-; CHECK-NEXT:    bit.16b v6, v16, v5
 ; CHECK-NEXT:    fcvt s1, d4
+; CHECK-NEXT:    fcvt s16, d2
 ; CHECK-NEXT:    bit.16b v3, v1, v5
 ; CHECK-NEXT:    mov d1, v2[1]
+; CHECK-NEXT:    bit.16b v6, v16, v5
 ; CHECK-NEXT:    fcvt s1, d1
 ; CHECK-NEXT:    ins.s v0[1], v3[0]
 ; CHECK-NEXT:    ins.s v0[2], v6[0]