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Differential D15652

[AArch64] Enable PostRAScheduler for AArch64 generic build (take 2)
ClosedPublic

Authored by mcrosier on Dec 18 2015, 1:26 PM.

Details

Reviewers
aadg
t.p.northover
jmolloy
MinSeongKIM
Summary

This patch enables PostRAScheduler specifically for AArch64 generic build, which is beneficial from the performance perspective.
Speedups up to 2 to 7% for some benchmarks on A57 and A53 are observed. Also benchmarks from LLVM test-suite did not regress.

Original patch here: http://reviews.llvm.org/D15557

This was committed in r255896 and later reverted due to numerous lit test failures.

In this patch I've disabled the post-ra scheduler for all tests that were broken. Before committing my plan is to step through each test to determine if the ordering of instructions matters. If not, then I'm thinking we should leave the post-ra scheduler disabled in order to preserve the history of the test case. If the order of instructions matters then I'll updated the test accordingly. I suspect in most instances we'll just disable the post-ra scheduler.

Chad

Diff Detail

Event Timeline

mcrosier updated this revision to Diff 43260.Dec 18 2015, 1:26 PM
mcrosier retitled this revision from to [AArch64] Enable PostRAScheduler for AArch64 generic build (take 2).
mcrosier updated this object.
mcrosier added reviewers: aadg, jmolloy, t.p.northover, MinSeongKIM.
mcrosier set the repository for this revision to rL LLVM.
mcrosier added subscribers: llvm-commits, rengolin.
Herald added a subscriber: aemerson. · View Herald TranscriptDec 18 2015, 1:26 PM
MinSeongKIM accepted this revision.Dec 19 2015, 1:29 AM
MinSeongKIM edited edge metadata.

Hi Chad, LGTM.
This makes sense to me as the tests broken assume no post RA scheduler.
Also I did some work to mute the errors from the broken tests (Please see http://reviews.llvm.org/D15666 the revision is not for upstreaming, but to help the reviewers of "this revision"). I am not sure the changes are all legal and safe, but instruction orders for most of them do not seem matter. I hope it helps.

This revision is now accepted and ready to land.Dec 19 2015, 1:29 AM
flyingforyou added a subscriber: flyingforyou.Dec 20 2015, 5:06 PM
mcrosier closed this revision.Dec 21 2015, 6:47 AM

Committed in r256158.

Revision Contents

Diff 43260

lib/Target/AArch64/AArch64Subtarget.h

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} }
const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; } const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
const AArch64RegisterInfo *getRegisterInfo() const override { const AArch64RegisterInfo *getRegisterInfo() const override {
return &getInstrInfo()->getRegisterInfo(); return &getInstrInfo()->getRegisterInfo();
} }
const Triple &getTargetTriple() const { return TargetTriple; } const Triple &getTargetTriple() const { return TargetTriple; }
bool enableMachineScheduler() const override { return true; } bool enableMachineScheduler() const override { return true; }
bool enablePostRAScheduler() const override { bool enablePostRAScheduler() const override {
return isCortexA53() || isCortexA57(); return isGeneric() || isCortexA53() || isCortexA57();
} }
bool hasV8_1aOps() const { return HasV8_1aOps; } bool hasV8_1aOps() const { return HasV8_1aOps; }
bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_2aOps() const { return HasV8_2aOps; }
bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; } bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); } bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
bool isTargetWindows() const { return TargetTriple.isOSWindows(); } bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
bool isTargetAndroid() const { return TargetTriple.isAndroid(); } bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
bool isGeneric() const { return CPUString == "generic"; }
bool isCyclone() const { return CPUString == "cyclone"; } bool isCyclone() const { return CPUString == "cyclone"; }
bool isCortexA57() const { return CPUString == "cortex-a57"; } bool isCortexA57() const { return CPUString == "cortex-a57"; }
bool isCortexA53() const { return CPUString == "cortex-a53"; } bool isCortexA53() const { return CPUString == "cortex-a53"; }
bool useAA() const override { return isCortexA53(); } bool useAA() const override { return isCortexA53(); }
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call. /// that still makes it profitable to inline the call.
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test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -disable-post-ra < %s | FileCheck %s
; This test aims to check basic correctness of frame layout & ; This test aims to check basic correctness of frame layout &
; frame access code. There are 8 functions in this test file, ; frame access code. There are 8 functions in this test file,
; each function implements one element in the cartesian product ; each function implements one element in the cartesian product
; of: ; of:
; . a function having a VLA/noVLA ; . a function having a VLA/noVLA
; . a function with dynamic stack realignment/no dynamic stack realignment. ; . a function with dynamic stack realignment/no dynamic stack realignment.
; . a function needing a frame pionter/no frame pointer, ; . a function needing a frame pionter/no frame pointer,
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test/CodeGen/AArch64/alloca.ll

; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=aarch64-linux-gnu -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
declare void @use_addr(i8*) declare void @use_addr(i8*)
define void @test_simple_alloca(i64 %n) { define void @test_simple_alloca(i64 %n) {
; CHECK-LABEL: test_simple_alloca: ; CHECK-LABEL: test_simple_alloca:
%buf = alloca i8, i64 %n %buf = alloca i8, i64 %n
; Make sure we align the stack change to 16 bytes: ; Make sure we align the stack change to 16 bytes:
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test/CodeGen/AArch64/arm64-aapcs.ll

; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false < %s | FileCheck %s ; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s
@var = global i32 0, align 4 @var = global i32 0, align 4
; CHECK-LABEL: @test_i128_align ; CHECK-LABEL: @test_i128_align
define i128 @test_i128_align(i32, i128 %arg, i32 %after) { define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
store i32 %after, i32* @var, align 4 store i32 %after, i32* @var, align 4
; CHECK: str w4, [{{x[0-9]+}}, :lo12:var] ; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
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test/CodeGen/AArch64/arm64-hello.ll

; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra | FileCheck %s
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX ; RUN: llc < %s -mtriple=arm64-linux-gnu -disable-post-ra | FileCheck %s --check-prefix=CHECK-LINUX
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: stp x29, x30, [sp, #-16]! ; CHECK: stp x29, x30, [sp, #-16]!
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: stur wzr, [x29, #-4] ; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK: adrp x0, L_.str@PAGE ; CHECK: adrp x0, L_.str@PAGE
; CHECK: add x0, x0, L_.str@PAGEOFF ; CHECK: add x0, x0, L_.str@PAGEOFF
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test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-ios7.0 -disable-post-ra -o - %s | FileCheck %s
@ptr = global i8* null @ptr = global i8* null
define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) { define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) {
; CHECK-LABEL: test_v8i8_pre_load: ; CHECK-LABEL: test_v8i8_pre_load:
; CHECK: ldr d0, [x0, #40]! ; CHECK: ldr d0, [x0, #40]!
%newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5 %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5
%val = load <8 x i8>, <8 x i8>* %newaddr, align 8 %val = load <8 x i8>, <8 x i8>* %newaddr, align 8
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test/CodeGen/AArch64/arm64-inline-asm.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -no-integrated-as | FileCheck %s ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -no-integrated-as -disable-post-ra | FileCheck %s
; rdar://9167275 ; rdar://9167275
define i32 @t1() nounwind ssp { define i32 @t1() nounwind ssp {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: mov {{w[0-9]+}}, 7 ; CHECK: mov {{w[0-9]+}}, 7
%0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
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test/CodeGen/AArch64/arm64-large-frame.ll

; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -disable-fp-elim < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -disable-fp-elim -disable-post-ra < %s | FileCheck %s
declare void @use_addr(i8*) declare void @use_addr(i8*)
@addr = global i8* null @addr = global i8* null
define void @test_bigframe() { define void @test_bigframe() {
; CHECK-LABEL: test_bigframe: ; CHECK-LABEL: test_bigframe:
; CHECK: .cfi_startproc ; CHECK: .cfi_startproc
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test/CodeGen/AArch64/arm64-shrink-wrapping.ll

; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE ; RUN: llc %s -o - -enable-shrink-wrap=true -disable-post-ra | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE ; RUN: llc %s -o - -enable-shrink-wrap=false -disable-post-ra | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios" target triple = "arm64-apple-ios"
; Initial motivating example: Simple diamond with a call just on one side. ; Initial motivating example: Simple diamond with a call just on one side.
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; ;
; Compare the arguments and jump to exit. ; Compare the arguments and jump to exit.
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test/CodeGen/AArch64/arm64-trunc-store.ll

; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra | FileCheck %s
define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind { define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind {
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: xtn.8b v[[REG:[0-9]+]], v0 ; CHECK: xtn.8b v[[REG:[0-9]+]], v0
; CHECK-NEXT: str d[[REG]], [x0] ; CHECK-NEXT: str d[[REG]], [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = trunc <8 x i16> %arg to <8 x i8> %tmp = trunc <8 x i16> %arg to <8 x i8>
store <8 x i8> %tmp, <8 x i8>* %p, align 8 store <8 x i8> %tmp, <8 x i8>* %p, align 8
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test/CodeGen/AArch64/arm64-variadic-aapcs.ll

; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s
%va_list = type {i8*, i8*, i8*, i32, i32} %va_list = type {i8*, i8*, i8*, i32, i32}
@var = global %va_list zeroinitializer, align 8 @var = global %va_list zeroinitializer, align 8
declare void @llvm.va_start(i8*) declare void @llvm.va_start(i8*)
define void @test_simple(i32 %n, ...) { define void @test_simple(i32 %n, ...) {
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test/CodeGen/AArch64/arm64-xaluo.ll

; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
; ;
; Get the actual value of the overflow bit. ; Get the actual value of the overflow bit.
; ;
define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) { define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
entry: entry:
; CHECK-LABEL: saddo1.i32 ; CHECK-LABEL: saddo1.i32
; CHECK: adds {{w[0-9]+}}, w0, w1 ; CHECK: adds {{w[0-9]+}}, w0, w1
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test/CodeGen/AArch64/atomic-ops.ll

; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created ; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
; (i.e. reusing a register for status & data in store exclusive). ; (i.e. reusing a register for status & data in store exclusive).
; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}]
; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}] ; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}]
@var8 = global i8 0 @var8 = global i8 0
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test/CodeGen/AArch64/bitcast-v2i8.ll

; RUN: llc < %s -mtriple=aarch64-apple-ios | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck %s
; Part of PR21549: going through the stack isn't ideal but is correct. ; Part of PR21549: going through the stack isn't ideal but is correct.
define i16 @test_bitcast_v2i8_to_i16(<2 x i8> %a) { define i16 @test_bitcast_v2i8_to_i16(<2 x i8> %a) {
; CHECK-LABEL: test_bitcast_v2i8_to_i16 ; CHECK-LABEL: test_bitcast_v2i8_to_i16
; CHECK: mov.s [[WREG_HI:w[0-9]+]], v0[1] ; CHECK: mov.s [[WREG_HI:w[0-9]+]], v0[1]
; CHECK-NEXT: fmov [[WREG_LO:w[0-9]+]], s0 ; CHECK-NEXT: fmov [[WREG_LO:w[0-9]+]], s0
; CHECK-NEXT: strb [[WREG_HI]], [sp, #15] ; CHECK-NEXT: strb [[WREG_HI]], [sp, #15]
; CHECK-NEXT: strb [[WREG_LO]], [sp, #14] ; CHECK-NEXT: strb [[WREG_LO]], [sp, #14]
; CHECK-NEXT: ldrh w0, [sp, #14] ; CHECK-NEXT: ldrh w0, [sp, #14]
%aa = bitcast <2 x i8> %a to i16 %aa = bitcast <2 x i8> %a to i16
ret i16 %aa ret i16 %aa
} }

test/CodeGen/AArch64/dag-combine-select.ll

; RUN: llc -o - %s | FileCheck %s ; RUN: llc -disable-post-ra -o - %s | FileCheck %s
target triple = "arm64--" target triple = "arm64--"
@out = internal global i32 0, align 4 @out = internal global i32 0, align 4
; Ensure that we transform select(C0, x, select(C1, x, y)) towards ; Ensure that we transform select(C0, x, select(C1, x, y)) towards
; select(C0 | C1, x, y) so we can use CMP;CCMP for the implementation. ; select(C0 | C1, x, y) so we can use CMP;CCMP for the implementation.
; CHECK-LABEL: test0: ; CHECK-LABEL: test0:
; CHECK: cmp w0, #7 ; CHECK: cmp w0, #7
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test/CodeGen/AArch64/f16-instructions.ll

; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; CHECK-LABEL: test_fadd: ; CHECK-LABEL: test_fadd:
; CHECK-NEXT: fcvt s1, h1 ; CHECK-NEXT: fcvt s1, h1
; CHECK-NEXT: fcvt s0, h0 ; CHECK-NEXT: fcvt s0, h0
; CHECK-NEXT: fadd s0, s0, s1 ; CHECK-NEXT: fadd s0, s0, s1
; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: fcvt h0, s0
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test/CodeGen/AArch64/func-argpassing.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-post-ra | FileCheck --check-prefix=CHECK %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -disable-post-ra | FileCheck --check-prefix=CHECK-NOFP %s
%myStruct = type { i64 , i8, i32 } %myStruct = type { i64 , i8, i32 }
@var8 = global i8 0 @var8 = global i8 0
@var32 = global i32 0 @var32 = global i32 0
@var64 = global i64 0 @var64 = global i64 0
@var128 = global i128 0 @var128 = global i128 0
@varfloat = global float 0.0 @varfloat = global float 0.0
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test/CodeGen/AArch64/global-merge-3.ll

; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s ; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s
; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s ; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s
; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS ; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS
@x = global [1000 x i32] zeroinitializer, align 1 @x = global [1000 x i32] zeroinitializer, align 1
@y = global [1000 x i32] zeroinitializer, align 1 @y = global [1000 x i32] zeroinitializer, align 1
@z = internal global i32 1, align 4 @z = internal global i32 1, align 4
define void @f1(i32 %a1, i32 %a2, i32 %a3) { define void @f1(i32 %a1, i32 %a2, i32 %a3) {
;CHECK-APPLE-IOS: adrp x8, l__MergedGlobals@PAGE ;CHECK-APPLE-IOS: adrp x8, l__MergedGlobals@PAGE
;CHECK-APPLE-IOS-NOT: adrp ;CHECK-APPLE-IOS-NOT: adrp
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test/CodeGen/AArch64/nest-register.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s ; RUN: llc -disable-post-ra -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; Tests that the 'nest' parameter attribute causes the relevant parameter to be ; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register. ; passed in the right register.
define i8* @nest_receiver(i8* nest %arg) nounwind { define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver: ; CHECK-LABEL: nest_receiver:
; CHECK-NEXT: // BB#0: ; CHECK-NEXT: // BB#0:
; CHECK-NEXT: mov x0, x18 ; CHECK-NEXT: mov x0, x18
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test/CodeGen/AArch64/nontemporal.ll

; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false -disable-post-ra | FileCheck %s
define void @test_stnp_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 { define void @test_stnp_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 {
; CHECK-LABEL: test_stnp_v4i64: ; CHECK-LABEL: test_stnp_v4i64:
; CHECK-NEXT: mov d[[HI1:[0-9]+]], v1[1] ; CHECK-NEXT: mov d[[HI1:[0-9]+]], v1[1]
; CHECK-NEXT: mov d[[HI0:[0-9]+]], v0[1] ; CHECK-NEXT: mov d[[HI0:[0-9]+]], v0[1]
; CHECK-NEXT: stnp d1, d[[HI1]], [x0, #16] ; CHECK-NEXT: stnp d1, d[[HI1]], [x0, #16]
; CHECK-NEXT: stnp d0, d[[HI0]], [x0] ; CHECK-NEXT: stnp d0, d[[HI0]], [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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test/CodeGen/AArch64/tailcall-explicit-sret.ll

; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false -disable-post-ra | FileCheck %s
; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks. ; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks.
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; Check that we don't try to tail-call with a non-forwarded sret parameter. ; Check that we don't try to tail-call with a non-forwarded sret parameter.
declare void @test_explicit_sret(i1024* sret) #0 declare void @test_explicit_sret(i1024* sret) #0
; This is the only OK case, where we forward the explicit sret pointer. ; This is the only OK case, where we forward the explicit sret pointer.
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test/CodeGen/AArch64/vector-fcopysign.ll

; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple aarch64-apple-darwin -asm-verbose=false -disable-post-ra | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
;============ v1f32 ;============ v1f32
; WidenVecRes same ; WidenVecRes same
define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 { define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v1f32_v1f32: ; CHECK-LABEL: test_copysign_v1f32_v1f32:
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