[AVR] Enable verifyInstructionPredicates for AVR

[jacquesguan]

Summary

This patch fixes the failed test of verifyInstructionPredicates which is caused by verifyInstructionPredicates. verifyInstructionPredicates will add JMPk without checking the target predicate.

[benshi001]

LGTM. Thanks! One more suggestion, just remove the trailing dot in the title.

llvm/lib/Target/AVR/AVRAsmPrinter.cpp

assert(MI->getOperand(OpNum).getReg() != AVR::R27R26 &&
            "Base register X can not have offset/displacement.");
     O << '+' << MI->getOperand(OpNum + 1).getImm();
   }
 
   return false;
 }
 
 void AVRAsmPrinter::emitInstruction(const MachineInstr *MI) {
-  // FIXME: Enable feature predicate checks once all the test pass.
-  // AVR_MC::verifyInstructionPredicates(MI->getOpcode(),
-  //                                     getSubtargetInfo().getFeatureBits());
+  AVR_MC::verifyInstructionPredicates(MI->getOpcode(),
+                                      getSubtargetInfo().getFeatureBits());
 
   AVRMCInstLower MCInstLowering(OutContext, *this);
 
   MCInst I;
   MCInstLowering.lowerInstruction(*MI, I);
   EmitToStreamer(*OutStreamer, I);
 }
 

llvm/lib/Target/AVR/AVRInstrInfo.h

 #include "AVRRegisterInfo.h"
 
 #define GET_INSTRINFO_HEADER
 #include "AVRGenInstrInfo.inc"
 #undef GET_INSTRINFO_HEADER
 
 namespace llvm {
 
+class AVRSubtarget;
+
 namespace AVRCC {
 
 /// AVR specific condition codes.
 /// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
 /// They must be kept in synch.
 enum CondCodes {
   COND_EQ, //!< Equal
   COND_NE, //!< Not equal
enum TOF {
   MO_NEG = (1 << 3)
 };
 
 } // end of namespace AVRII
 
 /// Utilities related to the AVR instruction set.
 class AVRInstrInfo : public AVRGenInstrInfo {
 public:
-  explicit AVRInstrInfo();
+  explicit AVRInstrInfo(AVRSubtarget &STI);
 
   const AVRRegisterInfo &getRegisterInfo() const { return RI; }
   const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
   AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
   AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
public:
 
   void insertIndirectBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock &NewDestBB,
                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
                             int64_t BrOffset, RegScavenger *RS) const override;
 
 private:
   const AVRRegisterInfo RI;
+
+protected:
+  const AVRSubtarget &STI;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_INSTR_INFO_H

llvm/lib/Target/AVR/AVRInstrInfo.cpp

 #include "AVRTargetMachine.h"
 #include "MCTargetDesc/AVRMCTargetDesc.h"
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "AVRGenInstrInfo.inc"
 
 namespace llvm {
 
-AVRInstrInfo::AVRInstrInfo()
-    : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
+AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
+    : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
+      STI(STI) {}
 
 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MI,
                                const DebugLoc &DL, MCRegister DestReg,
                                MCRegister SrcReg, bool KillSrc) const {
   const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
   const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
   unsigned Opc;
void AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
                                         MachineBasicBlock &RestoreBB,
                                         const DebugLoc &DL, int64_t BrOffset,
                                         RegScavenger *RS) const {
   // This method inserts a *direct* branch (JMP), despite its name.
   // LLVM calls this method to fixup unconditional branches; it never calls
   // insertBranch or some hypothetical "insertDirectBranch".
   // See lib/CodeGen/RegisterRelaxation.cpp for details.
   // We end up here when a jump is too long for a RJMP instruction.
+  if (STI.hasJMPCALL())
     BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
+  else
+    report_fatal_error("cannot create long jump without FeatureJMPCALL");
 }
 
 } // end of namespace llvm

llvm/lib/Target/AVR/AVRSubtarget.cpp

 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "AVRGenSubtargetInfo.inc"
 
 namespace llvm {
 
 AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const AVRTargetMachine &TM)
-    : AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+    : AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(*this),
       TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)) {
   // Parse features string.
   ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
 }
 
 AVRSubtarget &
 AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                               const TargetMachine &TM) {
   // Parse features string.
   ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
   return *this;
 }
 
 } // end of namespace llvm

llvm/test/CodeGen/AVR/branch-relaxation-long.ll

-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr  -mattr=avr3 | FileCheck %s
 
 ; CHECK-LABEL: relax_to_jmp:
 ; CHECK: cpi     r{{[0-9]+}}, 0
 ; CHECK: brne    [[BB1:.LBB[0-9]+_[0-9]+]]
 ; CHECK: jmp     [[BB2:.LBB[0-9]+_[0-9]+]]
 ; CHECK: [[BB1]]:
 ; CHECK: nop
 ; CHECK: [[BB2]]: