[CSKY] Optimize conditional branches with floating point comparison

[benshi001]

ping ...

[zixuan-wu]

LGTM. Thank you.

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td

 def : Pat<(f32 fpimm16_16:$imm), (f32 (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), sFPR32))>,
         Requires<[HasFPUv2_SF]>;
 def : Pat<(f32 fpimm:$imm), (COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), sFPR32)>,
         Requires<[HasFPUv2_SF]>;
 
 def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,
         Requires<[HasFPUv2_DF]>;
 
-multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br, Instruction MV> {
+multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV> {
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv2_SF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
   let Predicates = [HasFPUv2_DF] in
   def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv2_DF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
 
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2))>;
   let Predicates = [HasFPUv2_DF] in
   def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2))>;
 }
 
-multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br, Instruction MV> {
+multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV> {
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv2_SF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
   let Predicates = [HasFPUv2_DF] in
   def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv2_DF] in
+  def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
 
   let Predicates = [HasFPUv2_SF] in
   def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1))>;
   let Predicates = [HasFPUv2_DF] in
   def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1))>;
 }
 
 // inverse (order && compare) to (unorder || inverse(compare))
 
-defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, MVCV32>;
-defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin<SETUO, "FCMPUO", BT32, MVC32>;
-defm : BRCond_Bin<SETO, "FCMPUO", BF32, MVCV32>;
-defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, MVC32>;
-
-defm : BRCond_Bin<SETNE, "FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, MVCV32>;
-defm : BRCond_Bin<SETGE, "FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin<SETLT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, BT32, MVCV32>;
+defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETUO, "FCMPUO", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETO, "FCMPUO", BF32, BT32, MVCV32>;
+defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, BF32, MVC32>;
+
+defm : BRCond_Bin<SETNE, "FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, BT32, MVCV32>;
+defm : BRCond_Bin<SETGE, "FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin<SETLT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, BF32, MVC32>;
 
 // -----------
 
 let Predicates = [HasFPUv2_SF] in {
   def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
             (BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
   def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
             (MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;

 let usesCustomInserter = 1 in  {
   let Predicates = [HasFPUv2_SF] in
   def FSELS : CSKYPseudo<(outs sFPR32Op:$dst), (ins CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2),
     "!fsels\t$dst, $src1, src2", [(set sFPR32Op:$dst, (select CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2))]>;
 
   let Predicates = [HasFPUv2_DF] in
   def FSELD : CSKYPseudo<(outs sFPR64Op:$dst), (ins CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2),
     "!fseld\t$dst, $src1, src2", [(set sFPR64Op:$dst, (select CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2))]>;
-}
+}
 

llvm/lib/Target/CSKY/CSKYInstrInfoF2.td

 def : Pat<(f32 fpimm16:$imm),(COPY_TO_REGCLASS (MOVI32 (fpimm32_lo16 fpimm16:$imm)), FPR32)>,
         Requires<[HasFPUv3_SF]>;
 def : Pat<(f32 fpimm16_16:$imm), (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), FPR32)>,
         Requires<[HasFPUv3_SF]>;
 def : Pat<(f32 fpimm:$imm),(COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), FPR32)>,
         Requires<[HasFPUv3_SF]>;
 
 
-multiclass BRCond_Bin_F2<CondCode CC, string Instr, Instruction Br, Instruction MV, bit IsSelectSwap = 0> {
+multiclass BRCond_Bin_F2<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV, bit IsSelectSwap = 0> {
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv3_SF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
   let Predicates = [HasFPUv3_DF] in
   def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
+  let Predicates = [HasFPUv3_DF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
 
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2))>;
   let Predicates = [HasFPUv3_DF] in
   def : Pat<(i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2))>;
 
def : Pat<(select (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), FPR64Op:$rx, FPR64Op:$false),
             !if(
                 !eq(IsSelectSwap, 0),
                 (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), FPR64Op:$rx, FPR64Op:$false),
                 (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), FPR64Op:$false, FPR64Op:$rx)
                )>;
   }
 }
 
-multiclass BRCond_Bin_SWAP_F2<CondCode CC, string Instr, Instruction Br, Instruction MV, bit IsSelectSwap = 0> {
+multiclass BRCond_Bin_SWAP_F2<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV, bit IsSelectSwap = 0> {
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv3_SF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
   let Predicates = [HasFPUv3_DF] in
   def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
-            (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
+            (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
+  let Predicates = [HasFPUv3_DF] in
+  def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
+            (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
 
   let Predicates = [HasFPUv3_SF] in
   def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1))>;
   let Predicates = [HasFPUv3_DF] in
   def : Pat<(i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)),
             (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1))>;
 
def : Pat<(select (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), FPR64Op:$rx, FPR64Op:$false),
                 (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), FPR64Op:$rx, FPR64Op:$false),
                 (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), FPR64Op:$false, FPR64Op:$rx)
                )>;
   }
 }
 
 // inverse (order && compare) to (unorder || inverse(compare))
 
-defm : BRCond_Bin_F2<SETUNE, "f2FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETOEQ, "f2FCMPNE", BF32, MVCV32, 1>;
-defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETUO, "f2FCMPUO", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETO, "f2FCMPUO", BF32, MVCV32, 1>;
-defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP_F2<SETOLE, "f2FCMPHS", BT32, MVC32>;
-
-defm : BRCond_Bin_F2<SETNE, "f2FCMPNE", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, MVCV32, 1>;
-defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, MVC32>;
-defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, MVC32>;
-defm : BRCond_Bin_SWAP_F2<SETLE, "f2FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETUNE, "f2FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETOEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
+defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETUO, "f2FCMPUO", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETO, "f2FCMPUO", BF32, BT32, MVCV32, 1>;
+defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETOLE, "f2FCMPHS", BT32, BF32, MVC32>;
+
+defm : BRCond_Bin_F2<SETNE, "f2FCMPNE", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
+defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, BF32, MVC32>;
+defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, BF32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETLE, "f2FCMPHS", BT32, BF32, MVC32>;
 
 // ------
 
 let Predicates = [HasFPUv3_SF] in {
   def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
             (BT32 (f2FCMPHSZ_S FPR32Op:$rs1), bb:$imm16)>;
   def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)),
             (MVC32 (f2FCMPHSZ_S FPR32Op:$rs1))>;

 }
 
 
 let Predicates = [HasFPUv3_SF] in
 def : Pat<(select CARRY:$ca, FPR32Op:$rx, FPR32Op:$false),
           (f2FSEL_S CARRY:$ca, FPR32Op:$rx, FPR32Op:$false)>;
 let Predicates = [HasFPUv3_DF] in
 def : Pat<(select CARRY:$ca, FPR64Op:$rx, FPR64Op:$false),
-          (f2FSEL_D CARRY:$ca, FPR64Op:$rx, FPR64Op:$false)>;
+          (f2FSEL_D CARRY:$ca, FPR64Op:$rx, FPR64Op:$false)>;
 

llvm/test/CodeGen/CSKY/fpu/br-d.ll

 
 ;SGT
 define i32 @brRR_ogt(double %x, double %y) {
 ;
 ;
 ; CHECK-DF-LABEL: brRR_ogt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmpltd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB18_2
+; CHECK-DF-NEXT:    bf32 .LBB18_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB18_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ;
 ; CHECK-DF2-LABEL: brRR_ogt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmplt.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB18_2
+; CHECK-DF2-NEXT:    bf32 .LBB18_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB18_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ogt double %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_ogt(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brRI_ogt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI19_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB19_2
+; CHECK-DF-NEXT:    bf32 .LBB19_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB19_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI19_0:
 ; CHECK-DF-NEXT:    .quad 0x4024000000000000 # double 10
 ;
 ; CHECK-DF2-LABEL: brRI_ogt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI19_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB19_2
+; CHECK-DF2-NEXT:    bf32 .LBB19_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB19_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 define i32 @brR0_ogt(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brR0_ogt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI20_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB20_2
+; CHECK-DF-NEXT:    bf32 .LBB20_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB20_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI20_0:
 ; CHECK-DF-NEXT:    .quad 0x0000000000000000 # double 0
 ;
 ; CHECK-DF2-LABEL: brR0_ogt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI20_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB20_2
+; CHECK-DF2-NEXT:    bf32 .LBB20_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB20_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 
 ;SGE
 define i32 @brRR_oge(double %x, double %y) {
 ;
 ;
 ; CHECK-DF-LABEL: brRR_oge:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmphsd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB21_2
+; CHECK-DF-NEXT:    bf32 .LBB21_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB21_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ;
 ; CHECK-DF2-LABEL: brRR_oge:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmphs.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB21_2
+; CHECK-DF2-NEXT:    bf32 .LBB21_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB21_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 entry:
   %fcmp = fcmp oge double %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_oge(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brRI_oge:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI22_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB22_2
+; CHECK-DF-NEXT:    bf32 .LBB22_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB22_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI22_0:
 ; CHECK-DF-NEXT:    .quad 0x4024000000000000 # double 10
 ;
 ; CHECK-DF2-LABEL: brRI_oge:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI22_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB22_2
+; CHECK-DF2-NEXT:    bf32 .LBB22_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB22_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 define i32 @brR0_oge(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brR0_oge:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI23_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB23_2
+; CHECK-DF-NEXT:    bf32 .LBB23_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB23_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI23_0:
 ; CHECK-DF-NEXT:    .quad 0x0000000000000000 # double 0
 ;
 ; CHECK-DF2-LABEL: brR0_oge:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI23_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB23_2
+; CHECK-DF2-NEXT:    bf32 .LBB23_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB23_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 
 ;SLT
 define i32 @brRR_olt(double %x, double %y) {
 ;
 ;
 ; CHECK-DF-LABEL: brRR_olt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmpltd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB24_2
+; CHECK-DF-NEXT:    bf32 .LBB24_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB24_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ;
 ; CHECK-DF2-LABEL: brRR_olt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmplt.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB24_2
+; CHECK-DF2-NEXT:    bf32 .LBB24_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB24_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 entry:
   %fcmp = fcmp olt double %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_olt(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brRI_olt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI25_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB25_2
+; CHECK-DF-NEXT:    bf32 .LBB25_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB25_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI25_0:
 ; CHECK-DF-NEXT:    .quad 0x4024000000000000 # double 10
 ;
 ; CHECK-DF2-LABEL: brRI_olt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI25_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB25_2
+; CHECK-DF2-NEXT:    bf32 .LBB25_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB25_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 define i32 @brR0_olt(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brR0_olt:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI26_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmpltd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB26_2
+; CHECK-DF-NEXT:    bf32 .LBB26_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB26_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI26_0:
 ; CHECK-DF-NEXT:    .quad 0x0000000000000000 # double 0
 ;
 ; CHECK-DF2-LABEL: brR0_olt:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI26_0]
 ; CHECK-DF2-NEXT:    fcmplt.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB26_2
+; CHECK-DF2-NEXT:    bf32 .LBB26_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB26_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 
 ;SLE
 define i32 @brRR_ole(double %x, double %y) {
 ;
 ;
 ; CHECK-DF-LABEL: brRR_ole:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fcmphsd vr0, vr1
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB27_2
+; CHECK-DF-NEXT:    bf32 .LBB27_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB27_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ;
 ; CHECK-DF2-LABEL: brRR_ole:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fcmphs.64 vr0, vr1
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB27_2
+; CHECK-DF2-NEXT:    bf32 .LBB27_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB27_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ole double %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_ole(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brRI_ole:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI28_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB28_2
+; CHECK-DF-NEXT:    bf32 .LBB28_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB28_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI28_0:
 ; CHECK-DF-NEXT:    .quad 0x4024000000000000 # double 10
 ;
 ; CHECK-DF2-LABEL: brRI_ole:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI28_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB28_2
+; CHECK-DF2-NEXT:    bf32 .LBB28_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB28_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

 define i32 @brR0_ole(double %x) {
 ;
 ;
 ; CHECK-DF-LABEL: brR0_ole:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI29_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fcmphsd vr1, vr0
-; CHECK-DF-NEXT:    mvc32 a0
-; CHECK-DF-NEXT:    xori32 a0, a0, 1
-; CHECK-DF-NEXT:    btsti16 a0, 0
-; CHECK-DF-NEXT:    bt32 .LBB29_2
+; CHECK-DF-NEXT:    bf32 .LBB29_2
 ; CHECK-DF-NEXT:  # %bb.1: # %label1
 ; CHECK-DF-NEXT:    movi16 a0, 1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:  .LBB29_2: # %label2
 ; CHECK-DF-NEXT:    movi16 a0, 0
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.3:
 ; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI29_0:
 ; CHECK-DF-NEXT:    .quad 0x0000000000000000 # double 0
 ;
 ; CHECK-DF2-LABEL: brR0_ole:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI29_0]
 ; CHECK-DF2-NEXT:    fcmphs.64 vr1, vr0
-; CHECK-DF2-NEXT:    mvc32 a0
-; CHECK-DF2-NEXT:    xori32 a0, a0, 1
-; CHECK-DF2-NEXT:    btsti16 a0, 0
-; CHECK-DF2-NEXT:    bt32 .LBB29_2
+; CHECK-DF2-NEXT:    bf32 .LBB29_2
 ; CHECK-DF2-NEXT:  # %bb.1: # %label1
 ; CHECK-DF2-NEXT:    movi16 a0, 1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:  .LBB29_2: # %label2
 ; CHECK-DF2-NEXT:    movi16 a0, 0
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.3:

llvm/test/CodeGen/CSKY/fpu/br-f.ll

 }
 
 ;SGT
 define i32 @brRR_ogt(float %x, float %y) {
 ;
 ; CHECK-SF-LABEL: brRR_ogt:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmplts vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB18_2
+; CHECK-SF-NEXT:    bf32 .LBB18_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB18_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRR_ogt:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmplt.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB18_2
+; CHECK-SF2-NEXT:    bf32 .LBB18_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB18_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ogt float %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_ogt(float %x) {
 ;
 ; CHECK-SF-LABEL: brRI_ogt:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmplts vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB19_2
+; CHECK-SF-NEXT:    bf32 .LBB19_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB19_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRI_ogt:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmplt.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB19_2
+; CHECK-SF2-NEXT:    bf32 .LBB19_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB19_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ogt float %x, 10.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brR0_ogt(float %x) {
 ;
 ; CHECK-SF-LABEL: brR0_ogt:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzlss vr0
-; CHECK-SF-NEXT:    mvcv16 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB20_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmplts vr1, vr0
+; CHECK-SF-NEXT:    bf32 .LBB20_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB20_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_ogt:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmphz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB20_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT:    bf32 .LBB20_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB20_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ogt float %x, 0.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 ;SGE
 define i32 @brRR_oge(float %x, float %y) {
 ;
 ; CHECK-SF-LABEL: brRR_oge:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmphss vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB21_2
+; CHECK-SF-NEXT:    bf32 .LBB21_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB21_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRR_oge:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmphs.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB21_2
+; CHECK-SF2-NEXT:    bf32 .LBB21_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB21_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp oge float %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_oge(float %x) {
 ;
 ; CHECK-SF-LABEL: brRI_oge:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmphss vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB22_2
+; CHECK-SF-NEXT:    bf32 .LBB22_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB22_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRI_oge:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmphs.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB22_2
+; CHECK-SF2-NEXT:    bf32 .LBB22_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB22_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp oge float %x, 10.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brR0_oge(float %x) {
 ;
 ; CHECK-SF-LABEL: brR0_oge:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzhss vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB23_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmphss vr0, vr1
+; CHECK-SF-NEXT:    bf32 .LBB23_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB23_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_oge:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmphsz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB23_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT:    bf32 .LBB23_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB23_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp oge float %x, 0.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 ;SLT
 define i32 @brRR_olt(float %x, float %y) {
 ;
 ; CHECK-SF-LABEL: brRR_olt:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmplts vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB24_2
+; CHECK-SF-NEXT:    bf32 .LBB24_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB24_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRR_olt:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmplt.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB24_2
+; CHECK-SF2-NEXT:    bf32 .LBB24_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB24_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp olt float %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_olt(float %x) {
 ;
 ; CHECK-SF-LABEL: brRI_olt:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmplts vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB25_2
+; CHECK-SF-NEXT:    bf32 .LBB25_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB25_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRI_olt:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmplt.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB25_2
+; CHECK-SF2-NEXT:    bf32 .LBB25_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB25_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp olt float %x, 10.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brR0_olt(float %x) {
 ;
 ; CHECK-SF-LABEL: brR0_olt:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzhss vr0
-; CHECK-SF-NEXT:    mvcv16 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB26_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmplts vr0, vr1
+; CHECK-SF-NEXT:    bf32 .LBB26_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB26_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_olt:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmpltz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB26_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT:    bf32 .LBB26_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB26_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp olt float %x, 0.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 ;SLE
 define i32 @brRR_ole(float %x, float %y) {
 ;
 ; CHECK-SF-LABEL: brRR_ole:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    fcmphss vr0, vr1
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB27_2
+; CHECK-SF-NEXT:    bf32 .LBB27_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB27_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRR_ole:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    fcmphs.32 vr0, vr1
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB27_2
+; CHECK-SF2-NEXT:    bf32 .LBB27_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB27_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ole float %y, %x
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brRI_ole(float %x) {
 ;
 ; CHECK-SF-LABEL: brRI_ole:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fcmphss vr1, vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB28_2
+; CHECK-SF-NEXT:    bf32 .LBB28_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
 ; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB28_2: # %label2
 ; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brRI_ole:
 ; CHECK-SF2:       # %bb.0: # %entry
 ; CHECK-SF2-NEXT:    movih32 a0, 16672
 ; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
 ; CHECK-SF2-NEXT:    fcmphs.32 vr1, vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB28_2
+; CHECK-SF2-NEXT:    bf32 .LBB28_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
 ; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB28_2: # %label2
 ; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ole float %x, 10.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @brR0_ole(float %x) {
 ;
 ; CHECK-SF-LABEL: brR0_ole:
 ; CHECK-SF:       # %bb.0: # %entry
-; CHECK-SF-NEXT:    fcmpzlss vr0
-; CHECK-SF-NEXT:    mvc32 a0
-; CHECK-SF-NEXT:    xori32 a0, a0, 1
-; CHECK-SF-NEXT:    btsti16 a0, 0
-; CHECK-SF-NEXT:    bt32 .LBB29_2
+; CHECK-SF-NEXT:    movi16 a0, 0
+; CHECK-SF-NEXT:    fmtvrl vr1, a0
+; CHECK-SF-NEXT:    fcmphss vr1, vr0
+; CHECK-SF-NEXT:    bf32 .LBB29_2
 ; CHECK-SF-NEXT:  # %bb.1: # %label1
 ; CHECK-SF-NEXT:    movi16 a0, 1
-; CHECK-SF-NEXT:    rts16
 ; CHECK-SF-NEXT:  .LBB29_2: # %label2
-; CHECK-SF-NEXT:    movi16 a0, 0
 ; CHECK-SF-NEXT:    rts16
 ;
 ; CHECK-SF2-LABEL: brR0_ole:
 ; CHECK-SF2:       # %bb.0: # %entry
-; CHECK-SF2-NEXT:    fcmplsz.32 vr0
-; CHECK-SF2-NEXT:    mvc32 a0
-; CHECK-SF2-NEXT:    xori32 a0, a0, 1
-; CHECK-SF2-NEXT:    btsti16 a0, 0
-; CHECK-SF2-NEXT:    bt32 .LBB29_2
+; CHECK-SF2-NEXT:    movi16 a0, 0
+; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT:    fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT:    bf32 .LBB29_2
 ; CHECK-SF2-NEXT:  # %bb.1: # %label1
 ; CHECK-SF2-NEXT:    movi16 a0, 1
-; CHECK-SF2-NEXT:    rts16
 ; CHECK-SF2-NEXT:  .LBB29_2: # %label2
-; CHECK-SF2-NEXT:    movi16 a0, 0
 ; CHECK-SF2-NEXT:    rts16
 entry:
   %fcmp = fcmp ole float %x, 0.0
   br i1 %fcmp, label %label1, label %label2
 label1:
   ret i32 1
 label2:
   ret i32 0