[mips][microMIPS] Add R_MICROMIPS_PC21_S1 relocation

[dsanders]

LGTM

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

165

This is for another patch, but we ought to warn when we lose fractional bits because of these divisions.

include/llvm/Support/ELFRelocs/Mips.def

 ELF_RELOC(R_MICROMIPS_TLS_LDM,          163)
 ELF_RELOC(R_MICROMIPS_TLS_DTPREL_HI16,  164)
 ELF_RELOC(R_MICROMIPS_TLS_DTPREL_LO16,  165)
 ELF_RELOC(R_MICROMIPS_TLS_GOTTPREL,     166)
 ELF_RELOC(R_MICROMIPS_TLS_TPREL_HI16,   169)
 ELF_RELOC(R_MICROMIPS_TLS_TPREL_LO16,   170)
 ELF_RELOC(R_MICROMIPS_GPREL7_S2,        172)
 ELF_RELOC(R_MICROMIPS_PC23_S2,          173)
-ELF_RELOC(R_MICROMIPS_PC21_S2,          174)
+ELF_RELOC(R_MICROMIPS_PC21_S1,          174)
 ELF_RELOC(R_MICROMIPS_PC26_S2,          175)
 ELF_RELOC(R_MICROMIPS_PC18_S3,          176)
 ELF_RELOC(R_MICROMIPS_PC19_S2,          177)
 ELF_RELOC(R_MIPS_NUM,                218)
 ELF_RELOC(R_MIPS_PC32,               248)
 ELF_RELOC(R_MIPS_EH,                 249)

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

case Mips::fixup_MIPS_PC26_S2:
     // Forcing a signed division because Value can be negative.
     Value = (int64_t) Value / 4;
     // We now check if Value can be encoded as a 26-bit signed immediate.
     if (!isInt<26>(Value) && Ctx) {
       Ctx->reportError(Fixup.getLoc(), "out of range PC26 fixup");
       return 0;
     }
     break;
+  case Mips::fixup_MICROMIPS_PC21_S1:
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 2;
+    // We now check if Value can be encoded as a 21-bit signed immediate.
+    if (!isInt<21>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
+      return 0;
+    }
+    break;
   }
 
   return Value;
 }
 
 MCObjectWriter *
 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
   return createMipsELFObjectWriter(OS,
const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_MIPS_PCLO16",       0,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   0,     26,   0 },
     { "fixup_MICROMIPS_HI16",    0,     16,   0 },
     { "fixup_MICROMIPS_LO16",    0,     16,   0 },
     { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
     { "fixup_MICROMIPS_PC7_S1",  0,      7,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC10_S1", 0,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1", 0,     16,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC21_S1", 0,     21,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_OFST",        0,     16,   0 },
     { "fixup_MICROMIPS_TLS_GD",          0,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0,     16,   0 },
const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_MIPS_PCLO16",      16,     16,  MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_26_S1",   6,     26,   0 },
     { "fixup_MICROMIPS_HI16",   16,     16,   0 },
     { "fixup_MICROMIPS_LO16",   16,     16,   0 },
     { "fixup_MICROMIPS_GOT16",  16,     16,   0 },
     { "fixup_MICROMIPS_PC7_S1",  9,      7,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC10_S1", 6,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1",16,     16,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC21_S1",11,     21,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_OFST",        16,     16,   0 },
     { "fixup_MICROMIPS_TLS_GD",          16,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16,     16,   0 },

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

if (IsPCRel) {
     case Mips::fixup_Mips_PC16:
       return ELF::R_MIPS_PC16;
     case Mips::fixup_MICROMIPS_PC7_S1:
       return ELF::R_MICROMIPS_PC7_S1;
     case Mips::fixup_MICROMIPS_PC10_S1:
       return ELF::R_MICROMIPS_PC10_S1;
     case Mips::fixup_MICROMIPS_PC16_S1:
       return ELF::R_MICROMIPS_PC16_S1;
+    case Mips::fixup_MICROMIPS_PC21_S1:
+      return ELF::R_MICROMIPS_PC21_S1;
     case Mips::fixup_MIPS_PC19_S2:
       return ELF::R_MIPS_PC19_S2;
     case Mips::fixup_MIPS_PC18_S3:
       return ELF::R_MIPS_PC18_S3;
     case Mips::fixup_MIPS_PC21_S2:
       return ELF::R_MIPS_PC21_S2;
     case Mips::fixup_MIPS_PC26_S2:
       return ELF::R_MIPS_PC26_S2;

lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

enum Fixups {
     fixup_MICROMIPS_PC7_S1,
 
     // resulting in - R_MICROMIPS_PC10_S1
     fixup_MICROMIPS_PC10_S1,
 
     // resulting in - R_MICROMIPS_PC16_S1
     fixup_MICROMIPS_PC16_S1,
 
+    // resulting in - R_MICROMIPS_PC21_S1
+    fixup_MICROMIPS_PC21_S1,
+
     // resulting in - R_MICROMIPS_CALL16
     fixup_MICROMIPS_CALL16,
 
     // resulting in - R_MICROMIPS_GOT_DISP
     fixup_MICROMIPS_GOT_DISP,
 
     // resulting in - R_MICROMIPS_GOT_PAGE
     fixup_MICROMIPS_GOT_PAGE,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
 
   // If the destination is an immediate, divide by 2.
   if (MO.isImm()) return MO.getImm() >> 1;
 
   assert(MO.isExpr() &&
     "getBranchTarget21OpValueMM expects only expressions or immediates");
 
-  // TODO: Push fixup.
+  const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
+      MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
+  Fixups.push_back(MCFixup::create(0, FixupExpression,
+                                   MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
   return 0;
 }
 
 /// getBranchTarget26OpValue - Return binary encoding of the branch
 /// target operand. If the machine operand requires relocation,
 /// record the relocation and return zero.
 unsigned MipsMCCodeEmitter::
 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,

test/MC/Mips/micromips32r6/relocations.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
+# RUN:   -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
+# RUN:   -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax for fixups.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqzc $3, bar        # encoding: [0x80,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+# CHECK-FIXUP: bnezc $3, bar        # encoding: [0xa0,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF:     0x0 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x4 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF: ]
+
+  beqzc  $3, bar
+  bnezc  $3, bar
+

test/MC/Mips/micromips64r6/relocations.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
+# RUN:   -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
+# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
+# RUN:   -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
+#------------------------------------------------------------------------------
+# Check that the assembler can handle the documented syntax for fixups.
+#------------------------------------------------------------------------------
+# CHECK-FIXUP: beqzc $3, bar        # encoding: [0x80,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+# CHECK-FIXUP: bnezc $3, bar        # encoding: [0xa0,0b011AAAAA,A,A]
+# CHECK-FIXUP:                      #   fixup A - offset: 0,
+# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
+#------------------------------------------------------------------------------
+# Check that the appropriate relocations were created.
+#------------------------------------------------------------------------------
+# CHECK-ELF: Relocations [
+# CHECK-ELF:     0x0 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x4 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF: ]
+
+  beqzc  $3, bar
+  bnezc  $3, bar
+