[SystemZ] Use named MI sub-operands

[iii]

Summary

Prepare for removing the MemOpsEmitted workaround for symbolic
displacements by letting TableGen know about the offsets of the
displacement sub-operands within the instruction.

There are alternative ways to do this that were tried and rejected:

• Creating encoders and decoders for each possible displacement offset. This is too repetitive.

• Use VarLenCodeEmitter [1]. The resulting diff is quite large.

Instead, use the named sub-operand support introduced by commit
a538d1f13a13 ("[TableGen][CodeEmitterGen] Allow local names for
sub-operands in a operand list.").

Describe instruction encodings in terms of sub-operands instead of
operands (e.g. B, D, L vs BDL) - this also better matches the pictures
from the Principles of Operation. Decompose operands into sub-operands
using the new (bdaddr12only $B1, $D1):$BD1 syntax. Replace the
encoders and the decoders of the operands with these of the
sub-operands.

Since DecodeADDR64BitRegisterClass() is now used for bases and indices,
change it to return NoRegister when decoding 0. This also changes the
disassembly of some instructions, e.g., br %r0 becomes br 0. Since this
better captures the instruction semantics, namely, that the value of
%r0 is not used, keep this change and update the tests.

[1] https://m680x0.github.io/blog/2022/02/varlen-encoder.html

[iii]

This depends on https://reviews.llvm.org/D155158.

[uweigand]

This looks really nice, thanks for that improvement! A couple of trivial nits inline, otherwise LGTM.

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

612

Minor nit: can you move this next to the InstRSY definitions?

2857–2858

Looks like you accidentally removed the space after comma here.

5167

I see, the original $XBD was actually a bug. Good catch!

[iii]

• Rebase (the dependency CL was merged).
• New prep patch: ADDR64/GR64 cleanup.
• Move InstRSEa.
• Improve whitespace.

[iii]

• Drop the ADDR64/GR64 patch.
• Adjust the tests to accept 0 instead of %r0 instead.
• There already are a lot of assembler tests that check that %r0 is accepted for ADDR64.

[uweigand]

Yes, I agree that this is the best approach for the ADD64 issue. This version LGTM, thanks!

llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp

static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
                                      uint64_t Address, uint64_t Offset,
                                      uint64_t Width, MCInst &MI,
                                      const MCDisassembler *Decoder) {
   return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
                                            Width, /*InstSize=*/0);
 }
 
 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
-                                        const unsigned *Regs, unsigned Size) {
+                                        const unsigned *Regs, unsigned Size,
+                                        bool IsAddr = false) {
   assert(RegNo < Size && "Invalid register");
+  if (IsAddr && RegNo == 0) {
+    RegNo = SystemZ::NoRegister;
+  } else {
     RegNo = Regs[RegNo];
     if (RegNo == 0)
       return MCDisassembler::Fail;
+  }
   Inst.addOperand(MCOperand::createReg(RegNo));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);

 
 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
                                                 const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
 }
 
 static DecodeStatus
+DecodeADDR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+                             const MCDisassembler *Decoder) {
+  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16, true);
+}
+
+static DecodeStatus
 DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
                              const MCDisassembler *Decoder) {
-  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
+  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16, true);
 }
 
 static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder) {
   return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
 }
 

 }
 
 static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
                                         uint64_t Address,
                                         const MCDisassembler *Decoder) {
   return decodeSImmOperand<16>(Inst, Imm);
 }
 
+static DecodeStatus decodeS20ImmOperand(MCInst &Inst, uint64_t Imm,
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
+  return decodeSImmOperand<20>(Inst, Imm);
+}
+
 static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
                                         uint64_t Address,
                                         const MCDisassembler *Decoder) {
   return decodeSImmOperand<32>(Inst, Imm);
 }
 
 template <unsigned N>
+static DecodeStatus decodeLenOperand(MCInst &Inst, uint64_t Imm,
+                                     uint64_t Address,
+                                     const MCDisassembler *Decoder) {
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createImm(Imm + 1));
+  return MCDisassembler::Success;
+}
+
+template <unsigned N>
 static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
                                        uint64_t Address, bool isBranch,
                                        const MCDisassembler *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
   uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
 
   if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
                                 Inst, Decoder))

 }
 
 static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
                                          uint64_t Address,
                                          const MCDisassembler *Decoder) {
   return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
 }
 
-static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
-                                          const unsigned *Regs) {
-  uint64_t Base = Field >> 12;
-  uint64_t Disp = Field & 0xfff;
-  assert(Base < 16 && "Invalid BDAddr12");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(Disp));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
-                                          const unsigned *Regs) {
-  uint64_t Base = Field >> 20;
-  uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
-  assert(Base < 16 && "Invalid BDAddr20");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
-                                           const unsigned *Regs) {
-  uint64_t Index = Field >> 16;
-  uint64_t Base = (Field >> 12) & 0xf;
-  uint64_t Disp = Field & 0xfff;
-  assert(Index < 16 && "Invalid BDXAddr12");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
-                                           const unsigned *Regs) {
-  uint64_t Index = Field >> 24;
-  uint64_t Base = (Field >> 20) & 0xf;
-  uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
-  assert(Index < 16 && "Invalid BDXAddr20");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
-  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field,
-                                               const unsigned *Regs) {
-  uint64_t Length = Field >> 16;
-  uint64_t Base = (Field >> 12) & 0xf;
-  uint64_t Disp = Field & 0xfff;
-  assert(Length < 16 && "Invalid BDLAddr12Len4");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createImm(Length + 1));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
-                                               const unsigned *Regs) {
-  uint64_t Length = Field >> 16;
-  uint64_t Base = (Field >> 12) & 0xf;
-  uint64_t Disp = Field & 0xfff;
-  assert(Length < 256 && "Invalid BDLAddr12Len8");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createImm(Length + 1));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field,
-                                           const unsigned *Regs) {
-  uint64_t Length = Field >> 16;
-  uint64_t Base = (Field >> 12) & 0xf;
-  uint64_t Disp = Field & 0xfff;
-  assert(Length < 16 && "Invalid BDRAddr12");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createReg(Regs[Length]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
-                                           const unsigned *Regs) {
-  uint64_t Index = Field >> 16;
-  uint64_t Base = (Field >> 12) & 0xf;
-  uint64_t Disp = Field & 0xfff;
-  assert(Index < 32 && "Invalid BDVAddr12");
-  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
-  Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
-  return MCDisassembler::Success;
-}
-
-static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
-                                                uint64_t Address,
-                                                const MCDisassembler *Decoder) {
-  return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
-}
-
-static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
-                                                uint64_t Address,
-                                                const MCDisassembler *Decoder) {
-  return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
-}
-
-static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
-                                                uint64_t Address,
-                                                const MCDisassembler *Decoder) {
-  return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
-                                                uint64_t Address,
-                                                const MCDisassembler *Decoder) {
-  return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
-                             const MCDisassembler *Decoder) {
-  return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
-                             const MCDisassembler *Decoder) {
-  return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
-                                 const MCDisassembler *Decoder) {
-  return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
-                                 const MCDisassembler *Decoder) {
-  return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
-                             const MCDisassembler *Decoder) {
-  return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
-static DecodeStatus
-decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
-                             const MCDisassembler *Decoder) {
-  return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
-}
-
 #include "SystemZGenDisassemblerTables.inc"
 
 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                  ArrayRef<uint8_t> Bytes,
                                                  uint64_t Address,
                                                  raw_ostream &CS) const {
   // Get the first two bytes of the instruction.
   Size = 0;

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

private:
   uint64_t getDispOpValue(const MCInst &MI, unsigned OpNum,
                           SmallVectorImpl<MCFixup> &Fixups,
                           SystemZ::FixupKind Kind) const;
 
   // Called by the TableGen code to get the binary encoding of an address.
   // The index or length, if any, is encoded first, followed by the base,
   // followed by the displacement.  In a 20-bit displacement,
   // the low 12 bits are encoded before the high 8 bits.
-  uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
-                               SmallVectorImpl<MCFixup> &Fixups,
-                               const MCSubtargetInfo &STI) const;
-  uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
-                               SmallVectorImpl<MCFixup> &Fixups,
-                               const MCSubtargetInfo &STI) const;
-  uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
-                                SmallVectorImpl<MCFixup> &Fixups,
-                                const MCSubtargetInfo &STI) const;
-  uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
-                                SmallVectorImpl<MCFixup> &Fixups,
-                                const MCSubtargetInfo &STI) const;
-  uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
-                                    SmallVectorImpl<MCFixup> &Fixups,
-                                    const MCSubtargetInfo &STI) const;
-  uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
-                                    SmallVectorImpl<MCFixup> &Fixups,
-                                    const MCSubtargetInfo &STI) const;
-  uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
-                                SmallVectorImpl<MCFixup> &Fixups,
-                                const MCSubtargetInfo &STI) const;
-  uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
-                                SmallVectorImpl<MCFixup> &Fixups,
-                                const MCSubtargetInfo &STI) const;
+  template <unsigned N>
+  uint64_t getLenEncoding(const MCInst &MI, unsigned OpNum,
+  uint64_t getDisp12Encoding(const MCInst &MI, unsigned OpNum,
+  uint64_t getDisp20Encoding(const MCInst &MI, unsigned OpNum,
 
   // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
   // Offset bytes from the start of MI.  Add the fixup to Fixups
   // and return the in-place addend, which since we're a RELA target
   // is always 0.  If AllowTLS is true and optional operand OpNum + 1
   // is present, also emit a TLS call fixup for it.
   uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
                             SmallVectorImpl<MCFixup> &Fixups,
if (MO.isExpr()) {
     Fixups.push_back(MCFixup::create(ByteOffs, MO.getExpr(), (MCFixupKind)Kind,
                                      MI.getLoc()));
     assert(Fixups.size() <= 2 && "More than two memory operands in MI?");
     return 0;
   }
   llvm_unreachable("Unexpected operand type!");
 }
 
-uint64_t SystemZMCCodeEmitter::
-getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
-                    SmallVectorImpl<MCFixup> &Fixups,
-                    const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
-  assert(isUInt<4>(Base) && isUInt<12>(Disp));
-  return (Base << 12) | Disp;
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
-                    SmallVectorImpl<MCFixup> &Fixups,
-                    const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_20);
-  assert(isUInt<4>(Base) && isInt<20>(Disp));
-  return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
-                     SmallVectorImpl<MCFixup> &Fixups,
-                     const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
-  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
-  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
-  return (Index << 16) | (Base << 12) | Disp;
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
-                     SmallVectorImpl<MCFixup> &Fixups,
-                     const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_20);
-  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
-  assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
-  return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
-    | ((Disp & 0xff000) >> 12);
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum,
-                         SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
-  uint64_t Len  = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
-  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
-  return (Len << 16) | (Base << 12) | Disp;
-}
-
-uint64_t SystemZMCCodeEmitter::
-getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
+template <unsigned N>
+uint64_t
+SystemZMCCodeEmitter::getLenEncoding(const MCInst &MI, unsigned OpNum,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
-  uint64_t Len  = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
-  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
-  return (Len << 16) | (Base << 12) | Disp;
+  return getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI) - 1;
 }
 
-uint64_t SystemZMCCodeEmitter::
-getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum,
+uint64_t
+SystemZMCCodeEmitter::getDisp12Encoding(const MCInst &MI, unsigned OpNum,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
-  uint64_t Len  = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
-  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
-  return (Len << 16) | (Base << 12) | Disp;
+  return getDispOpValue(MI, OpNum, Fixups, SystemZ::FixupKind::FK_390_12);
 }
 
-uint64_t SystemZMCCodeEmitter::
-getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
+uint64_t
+SystemZMCCodeEmitter::getDisp20Encoding(const MCInst &MI, unsigned OpNum,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
-  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
-  uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12);
-  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
-  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
-  return (Index << 16) | (Base << 12) | Disp;
+  return getDispOpValue(MI, OpNum, Fixups, SystemZ::FixupKind::FK_390_20);
 }
 
 uint64_t
 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        unsigned Kind, int64_t Offset,
                                        bool AllowTLS) const {
   SMLoc Loc = MI.getLoc();

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

 // Instruction formats
 //===----------------------------------------------------------------------===//
 //
 // Formats are specified using operand field declarations of the form:
 //
 //   bits<4> Rn   : register input or output for operand n
 //   bits<5> Vn   : vector register input or output for operand n
 //   bits<m> In   : immediate value of width m for operand n
-//   bits<4> BDn  : address operand n, which has a base and a displacement
-//   bits<m> XBDn : address operand n, which has an index, a base and a
-//                  displacement
-//   bits<m> VBDn : address operand n, which has a vector index, a base and a
-//                  displacement
+//   bits<4> Bn   : base register for address operand n
+//   bits<m> Dn   : displacement for address operand n
+//   bits<5> Vn   : vector index for address operand n
 //   bits<4> Xn   : index register for address operand n
 //   bits<4> Mn   : mode value for operand n
 //
 // The operand numbers ("n" in the list above) follow the architecture manual.
 // Assembly operands sometimes have a different order; in particular, R3 often
 // is often written between operands 1 and 2.
 //
 //===----------------------------------------------------------------------===//

 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
   bits<4> M3;
-  bits<16> BD4;
+  bits<4> B4;
+  bits<12> D4;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
   let Inst{35-32} = M3;
-  let Inst{31-16} = BD4;
+  let Inst{31-28} = B4;
+  let Inst{27-16} = D4;
   let Inst{15-8}  = I2;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
   field bits<16> SoftFail = 0;

 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
   bits<4> M3;
-  bits<16> BD4;
+  bits<4> B4;
+  bits<12> D4;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
   let Inst{35-32} = R2;
-  let Inst{31-16} = BD4;
+  let Inst{31-28} = B4;
+  let Inst{27-16} = D4;
   let Inst{15-12} = M3;
   let Inst{11-8}  = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<4> R1;
-  bits<20> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{31-24} = op;
   let Inst{23-20} = R1;
-  let Inst{19-0}  = XBD2;
+  let Inst{19-16} = X2;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 
   let HasIndex = 1;
 }
 
 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<4> M1;
-  bits<20> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{31-24} = op;
   let Inst{23-20} = M1;
-  let Inst{19-0}  = XBD2;
+  let Inst{19-16} = X2;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 
   let HasIndex = 1;
 }
 
 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
-  bits<20> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> M3;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
-  let Inst{35-16} = XBD2;
+  let Inst{35-32} = X2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = M3;
   let Inst{11-8}  = 0;
   let Inst{7-0}   = op{7-0};
 
   let HasIndex = 1;
 }
 
 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
-  bits<20> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R3;
-  let Inst{35-16} = XBD2;
+  let Inst{35-32} = X2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = R1;
   let Inst{11-8}  = 0;
   let Inst{7-0}   = op{7-0};
 
   let HasIndex = 1;
 }
 
 class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
-  bits<28> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<20> D2;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
-  let Inst{35-8}  = XBD2;
+  let Inst{35-32} = X2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2{11-0};
+  let Inst{15-8}  = D2{19-12};
   let Inst{7-0}   = op{7-0};
 
   let Has20BitOffset = 1;
   let HasIndex = 1;
 }
 
 class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> M1;
-  bits<28> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<20> D2;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = M1;
-  let Inst{35-8}  = XBD2;
+  let Inst{35-32} = X2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2{11-0};
+  let Inst{15-8}  = D2{19-12};
   let Inst{7-0}   = op{7-0};
 
   let Has20BitOffset = 1;
   let HasIndex = 1;
 }
 
 class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{31-24} = op;
   let Inst{23-20} = R1;
   let Inst{19-16} = R3;
-  let Inst{15-0}  = BD2;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> M3;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{31-24} = op;
   let Inst{23-20} = R1;
   let Inst{19-16} = M3;
-  let Inst{15-0}  = BD2;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
+}
+
+class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<6, outs, ins, asmstr, pattern> {
+  field bits<48> Inst;
+  field bits<48> SoftFail = 0;
+
+  bits<4> R1;
+  bits<4> R3;
+  bits<4> B2;
+  bits<12> D2;
+
+  let Inst{47-40} = op{15-8};
+  let Inst{39-36} = R1;
+  let Inst{35-32} = R3;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
+  let Inst{15-8}  = 0;
+  let Inst{7-0}   = op{7-0};
 }
 
 class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
   bits<16> RI2;
 
   let Inst{31-24} = op;
   let Inst{23-20} = R1;
   let Inst{19-16} = R3;
   let Inst{15-0}  = RI2;
 }
 
 class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<20> BDL1;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> L1;
 
   let Inst{47-40} = op{15-8};
-  let Inst{39-36} = BDL1{19-16};
+  let Inst{39-36} = L1;
   let Inst{35-32} = 0;
-  let Inst{31-16} = BDL1{15-0};
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
   let Inst{15-8}  = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
-  bits<24> BDL2;
+  bits<4> B2;
+  bits<12> D2;
+  bits<8> L2;
   bits<4> M3;
 
   let Inst{47-40} = op{15-8};
-  let Inst{39-16} = BDL2;
+  let Inst{39-32} = L2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = R1;
   let Inst{11-8}  = M3;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
-  bits<24> BD2;
+  bits<4> B2;
+  bits<20> D2;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
   let Inst{35-32} = R3;
-  let Inst{31-8}  = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2{11-0};
+  let Inst{15-8}  = D2{19-12};
   let Inst{7-0}   = op{7-0};
 
   let Has20BitOffset = 1;
 }
 
 class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> M3;
-  bits<24> BD2;
+  bits<4> B2;
+  bits<20> D2;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
   let Inst{35-32} = M3;
-  let Inst{31-8}  = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2{11-0};
+  let Inst{15-8}  = D2{19-12};
   let Inst{7-0}   = op{7-0};
 
   let Has20BitOffset = 1;
 }
 
 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
-  bits<16> BD1;
+  bits<4> B1;
+  bits<12> D1;
   bits<8> I2;
 
   let Inst{31-24} = op;
   let Inst{23-16} = I2;
-  let Inst{15-0}  = BD1;
+  let Inst{15-12} = B1;
+  let Inst{11-0}  = D1;
 }
 
 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<16> BD1;
+  bits<4> B1;
+  bits<12> D1;
   bits<16> I2;
 
   let Inst{47-32} = op;
-  let Inst{31-16} = BD1;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
   let Inst{15-0}  = I2;
 }
 
 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<24> BD1;
+  bits<4> B1;
+  bits<20> D1;
   bits<8> I2;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-32} = I2;
-  let Inst{31-8}  = BD1;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1{11-0};
+  let Inst{15-8}  = D1{19-12};
   let Inst{7-0}   = op{7-0};
 
   let Has20BitOffset = 1;
 }
 
 class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<16> RI2;
-  bits<16> BD3;
+  bits<4> B3;
+  bits<12> D3;
 
   let Inst{47-40} = op;
   let Inst{39-36} = M1;
   let Inst{35-32} = 0;
-  let Inst{31-16} = BD3;
+  let Inst{31-28} = B3;
+  let Inst{27-16} = D3;
   let Inst{15-0}  = RI2;
 }
 
 class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<24> BDL1;
-  bits<16> BD2;
+  bits<4> B1;
+  bits<12> D1;
+  bits<8> L1;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{47-40} = op;
-  let Inst{39-16} = BDL1;
-  let Inst{15-0}  = BD2;
+  let Inst{39-32} = L1;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<20> BDL1;
-  bits<20> BDL2;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> L1;
+  bits<4> B2;
+  bits<12> D2;
+  bits<4> L2;
 
   let Inst{47-40} = op;
-  let Inst{39-36} = BDL1{19-16};
-  let Inst{35-32} = BDL2{19-16};
-  let Inst{31-16} = BDL1{15-0};
-  let Inst{15-0}  = BDL2{15-0};
+  let Inst{39-36} = L1;
+  let Inst{35-32} = L2;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0} = D2;
 }
 
 class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<20> BDL1;
-  bits<16> BD2;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> L1;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> I3;
 
   let Inst{47-40} = op;
-  let Inst{39-36} = BDL1{19-16};
+  let Inst{39-36} = L1;
   let Inst{35-32} = I3;
-  let Inst{31-16} = BDL1{15-0};
-  let Inst{15-0}  = BD2;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<20> RBD1;
-  bits<16> BD2;
+  bits<4> R1;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> R3;
 
   let Inst{47-40} = op;
-  let Inst{39-36} = RBD1{19-16};
+  let Inst{39-36} = R1;
   let Inst{35-32} = R3;
-  let Inst{31-16} = RBD1{15-0};
-  let Inst{15-0}  = BD2;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> R3;
-  bits<16> BD4;
+  bits<4> B4;
+  bits<12> D4;
 
   let Inst{47-40} = op;
   let Inst{39-36} = R1;
   let Inst{35-32} = R3;
-  let Inst{31-16} = BD2;
-  let Inst{15-0}  = BD4;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
+  let Inst{15-12} = B4;
+  let Inst{11-0}  = D4;
 }
 
 class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<16> BD1;
-  bits<24> BDL2;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> B2;
+  bits<12> D2;
+  bits<8> L2;
 
   let Inst{47-40} = op;
-  let Inst{39-32} = BDL2{23-16};
-  let Inst{31-16} = BD1;
-  let Inst{15-0}  = BDL2{15-0};
+  let Inst{39-32} = L2;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<16> BD1;
-  bits<16> BD2;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{47-32} = op;
-  let Inst{31-16} = BD1;
-  let Inst{15-0}  = BD2;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
-  bits<16> BD1;
-  bits<16> BD2;
+  bits<4> B1;
+  bits<12> D1;
+  bits<4> B2;
+  bits<12> D2;
   bits<4>  R3;
 
   let Inst{47-40} = op{11-4};
   let Inst{39-36} = R3;
   let Inst{35-32} = op{3-0};
-  let Inst{31-16} = BD1;
-  let Inst{15-0}  = BD2;
+  let Inst{31-28} = B1;
+  let Inst{27-16} = D1;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
 
   let Inst{31-16} = op;
-  let Inst{15-0}  = BD2;
+  let Inst{15-12} = B2;
+  let Inst{11-0}  = D2;
 }
 
 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;

 }
 
 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
   bits<5> V3;
   bits<4> M4;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = V1{3-0};
   let Inst{35-32} = V3{3-0};
-  let Inst{31-16} = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = M4;
   let Inst{11}    = V1{4};
   let Inst{10}    = V3{4};
   let Inst{9-8}   = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> R3;
   bits<4> M4;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = V1{3-0};
   let Inst{35-32} = R3;
-  let Inst{31-16} = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = M4;
   let Inst{11}    = V1{4};
   let Inst{10-8}  = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
   bits<5> V3;
   bits<4> M4;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = R1;
   let Inst{35-32} = V3{3-0};
-  let Inst{31-16} = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = M4;
   let Inst{11}    = 0;
   let Inst{10}    = V3{4};
   let Inst{9-8}   = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> R3;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = 0;
   let Inst{35-32} = R3;
-  let Inst{31-16} = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = V1{3-0};
   let Inst{11-9}  = 0;
   let Inst{8}     = V1{4};
   let Inst{7-0}   = op{7-0};
 }
 
 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;
-  bits<21> VBD2;
+  bits<5> V2;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> M3;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = V1{3-0};
-  let Inst{35-16} = VBD2{19-0};
+  let Inst{35-32} = V2{3-0};
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = M3;
   let Inst{11}    = V1{4};
-  let Inst{10}    = VBD2{20};
+  let Inst{10}    = V2{4};
   let Inst{9-8}   = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;
-  bits<20> XBD2;
+  bits<4> X2;
+  bits<4> B2;
+  bits<12> D2;
   bits<4> M3;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-36} = V1{3-0};
-  let Inst{35-16} = XBD2;
+  let Inst{35-32} = X2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = M3;
   let Inst{11}    = V1{4};
   let Inst{10-8}  = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<5> V1;
-  bits<16> BD2;
+  bits<4> B2;
+  bits<12> D2;
   bits<8> I3;
 
   let Inst{47-40} = op{15-8};
   let Inst{39-32} = I3;
-  let Inst{31-16} = BD2;
+  let Inst{31-28} = B2;
+  let Inst{27-16} = D2;
   let Inst{15-12} = V1{3-0};
   let Inst{11-9}  = 0;
   let Inst{8}     = V1{4};
   let Inst{7-0}   = op{7-0};
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction classes for .insn directives

 
 class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstRSa<0, outs, ins, asmstr, pattern> {
   bits<32> enc;
 
   let Inst{31-24} = enc{31-24};
 }
 
-// RSE is like RSY except with a 12 bit displacement (instead of 20).
 class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRSYa<6, outs, ins, asmstr, pattern> {
+  : InstRSEa<6, outs, ins, asmstr, pattern> {
   bits <48> enc;
 
   let Inst{47-40} = enc{47-40};
-  let Inst{31-16} = BD2{15-0};
-  let Inst{15-8}  = 0;
   let Inst{7-0}   = enc{7-0};
 }
 
 class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstRSI<0, outs, ins, asmstr, pattern> {
   bits<32> enc;
 
   let Inst{31-24} = enc{31-24};

 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
   : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
   let I2 = value;
   let M3 = 0;
 }
 
 class StoreInherentS<string mnemonic, bits<16> opcode,
                      SDPatternOperator operator, bits<5> bytes>
-  : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
+  : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2),
           mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class SideEffectInherentE<string mnemonic, bits<16>opcode>
   : InstE<opcode, (outs), (ins), mnemonic, []>;
 
 class SideEffectInherentS<string mnemonic, bits<16> opcode,
                           SDPatternOperator operator>
   : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
-  let BD2 = 0;
+  let B2 = 0;
+  let D2 = 0;
 }
 
 class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
   : InstRRE<opcode, (outs), (ins), mnemonic, []> {
   let R1 = 0;
   let R2 = 0;
 }
 
 // Allow an optional TLS marker symbol to generate TLS call relocations.
 class CallRI<string mnemonic, bits<12> opcode>
   : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
             mnemonic#"\t$R1, $RI2", []>;
 
 // Allow an optional TLS marker symbol to generate TLS call relocations.
 class CallRIL<string mnemonic, bits<12> opcode>
   : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
              mnemonic#"\t$R1, $RI2", []>;
 
 class CallRR<string mnemonic, bits<8> opcode>
   : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
            mnemonic#"\t$R1, $R2", []>;
 
 class CallRX<string mnemonic, bits<8> opcode>
-  : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
+  : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2", []>;
 
 class CondBranchRI<string mnemonic, bits<12> opcode,
                    SDPatternOperator operator = null_frag>
   : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
             !subst("#", "${M1}", mnemonic)#"\t$RI2",
             [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
   let CCMaskFirst = 1;
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
   : InstRR<opcode, (outs), (ins ADDR64:$R2),
            !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let R1 = V.ccmask;
 }
 
 class CondBranchRX<string mnemonic, bits<8> opcode>
-  : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
+  : InstRXb<opcode, (outs),
+            (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
   let CCMaskFirst = 1;
 }
 
 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
-  : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
+  : InstRXb<opcode, (outs),
+            (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$M1, $XBD2", []>;
 
 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
-  : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
+  : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
             !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M1 = V.ccmask;
 }
 
 class CondBranchRXY<string mnemonic, bits<16> opcode>
-  : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
+  : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1,
+             (bdxaddr20only $B2, $D2, $X2):$XBD2),
              !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
   let CCMaskFirst = 1;
   let mayLoad = 1;
 }
 
 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
-  : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
+  : InstRXYb<opcode, (outs),
+             (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$M1, $XBD2", []> {
   let mayLoad = 1;
 }
 
 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
                          SDPatternOperator operator = null_frag>
-  : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
+  : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
              !subst("#", V.suffix, mnemonic)#"\t$XBD2",
              [(operator (load bdxaddr20only:$XBD2))]> {
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M1 = V.ccmask;
   let mayLoad = 1;
 }
 
class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 class CmpBranchRRS<string mnemonic, bits<16> opcode,
                    RegisterOperand cls>
   : InstRRS<opcode, (outs),
-            (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
+            (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#"$M3\t$R1, $R2, $BD4", []>;
 
 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
                       RegisterOperand cls>
   : InstRRS<opcode, (outs),
-            (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
+            (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
 
 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls>
-  : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
+  : InstRRS<opcode, (outs),
+            (ins cls:$R1, cls:$R2, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
                             RegisterOperand cls> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRRS<mnemonic, opcode, cls>;
   def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
 }
 
 class CmpBranchRIS<string mnemonic, bits<16> opcode,
                    RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIS<opcode, (outs),
-            (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
+            (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#"$M3\t$R1, $I2, $BD4", []>;
 
 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
                       RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIS<opcode, (outs),
-            (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
+            (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
 
 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls, ImmOpWithPattern imm>
-  : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
+  : InstRIS<opcode, (outs),
+            (ins cls:$R1, imm:$I2, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
                             RegisterOperand cls, ImmOpWithPattern imm> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
   def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
 }
 
 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
                     RegisterOperand cls>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
+  : InstRSYb<opcode, (outs),
+             (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
              mnemonic#"$M3\t$R1, $BD2", []>;
 
 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
                        RegisterOperand cls>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
+  : InstRSYb<opcode, (outs),
+             (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
              mnemonic#"\t$R1, $M3, $BD2", []>;
 
 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
                              RegisterOperand cls> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
   def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
 }
 
 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
                           RegisterOperand cls>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
+  : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2),
              mnemonic#V.suffix#"\t$R1, $BD2", []> {
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
   : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),

 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
   : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
             mnemonic#"\t$R1, $R2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
-  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
+  : InstRXa<opcode, (outs cls:$R1),
+            (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
-  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
+  : InstRXYa<opcode, (outs cls:$R1),
+             (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
   : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
             mnemonic#"\t$R1, $R3, $RI2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
   : InstRIEe<opcode, (outs cls:$R1),
              (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
              mnemonic#"\t$R1, $R3, $RI2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
   : InstRSa<opcode, (outs cls:$R1),
-            (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
+            (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
             mnemonic#"\t$R1, $R3, $BD2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
   : InstRSYa<opcode,
-             (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
+             (outs cls:$R1),
+             (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
                      AddressingMode mode = bdaddr12only>
-  : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
+  : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
             mnemonic#"\t$R1, $R3, $BD2", []> {
   let mayLoad = 1;
 }
 
 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
                       AddressingMode mode = bdaddr20only>
-  : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
+  : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2", []> {
   let mayLoad = 1;
 }
 
 multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
                               bits<16> rsyOpcode, RegisterOperand cls> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
     let DispSize = "20" in
       def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
   }
 }
 
 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
   : InstSSe<opcode, (outs cls:$R1, cls:$R3),
-            (ins bdaddr12only:$BD2, bdaddr12only:$BD4),
+            (ins (bdaddr12only $B2, $D2):$BD2, (bdaddr12only $B4, $D4):$BD4),
             mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
   let mayLoad = 1;
 }
 
 multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
   let mayLoad = 1 in {
     def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
-                        (ins bdaddr12only:$BD2, imm32zx4:$M4),
+                        (ins (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
                         mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
     let M4 = 0 in
       def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
-                        (ins bdaddr12only:$BD2),
+                        (ins (bdaddr12only $B2, $D2):$BD2),
                         mnemonic#"\t$V1, $V3, $BD2", []>;
   }
 }
 
 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
                  RegisterOperand cls>
   : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
              mnemonic#"\t$R1, $RI2",
              [(operator cls:$R1, pcrel32:$RI2)]> {
   let mayStore = 1;
   // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
   // However, BDXs have two extra operands and are therefore 6 units more
   // complex.
   let AddedComplexity = 7;
 }
 
 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
               RegisterOperand cls, bits<5> bytes,
               AddressingMode mode = bdxaddr12only>
-  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+  : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(operator cls:$R1, mode:$XBD2)]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                RegisterOperand cls, bits<5> bytes,
                AddressingMode mode = bdxaddr20only>
-  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+  : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2",
              [(operator cls:$R1, mode:$XBD2)]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
                        SDPatternOperator operator, RegisterOperand cls,
                        bits<5> bytes> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
     let DispSize = "20" in
       def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
                         bdxaddr20pair>;
   }
 }
 
 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                TypedReg tr, bits<5> bytes, bits<4> type = 0>
-  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
+  : InstVRX<opcode, (outs),
+            (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$V1, $XBD2",
             [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2)]> {
   let M3 = type;
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreVRXGeneric<string mnemonic, bits<16> opcode>
-  : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
+  : InstVRX<opcode, (outs),
+            (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
             mnemonic#"\t$V1, $XBD2, $M3", []> {
   let mayStore = 1;
 }
 
 multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
   let mayStore = 1, AccessBytes = 16 in {
     def Align : InstVRX<opcode, (outs),
-                        (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
+                        (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
+                             imm32zx4:$M3),
                         mnemonic#"\t$V1, $XBD2, $M3", []>;
     let M3 = 0 in
-      def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
+      def "" : InstVRX<opcode, (outs),
+                       (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
                        mnemonic#"\t$V1, $XBD2", []>;
   }
 }
 
 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
                       SDPatternOperator operator, bits<5> bytes>
-  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
+  : InstVRSb<opcode, (outs),
+             (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
              mnemonic#"\t$V1, $R3, $BD2",
              [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
   let M4 = 0;
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreLengthVRSd<string mnemonic, bits<16> opcode,
                       SDPatternOperator operator, bits<5> bytes>
-  : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
+  : InstVRSd<opcode, (outs),
+             (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
              mnemonic#"\t$V1, $R3, $BD2",
              [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreLengthVSI<string mnemonic, bits<16> opcode,
                      SDPatternOperator operator, bits<5> bytes>
-  : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
+  : InstVSI<opcode, (outs),
+            (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
             mnemonic#"\t$V1, $BD2, $I3",
             [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
                       AddressingMode mode = bdaddr12only>
-  : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
+  : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
             mnemonic#"\t$R1, $R3, $BD2", []> {
   let mayStore = 1;
 }
 
 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
                        AddressingMode mode = bdaddr20only>
-  : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
+  : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2", []> {
   let mayStore = 1;
 }
 
 multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
                                bits<16> rsyOpcode, RegisterOperand cls> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
     let DispSize = "20" in
       def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
   }
 }
 
 multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
   let mayStore = 1 in {
     def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
-                                              bdaddr12only:$BD2, imm32zx4:$M4),
+                                              (bdaddr12only $B2, $D2):$BD2,
+                                              imm32zx4:$M4),
                          mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
     let M4 = 0 in
       def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
-                                             bdaddr12only:$BD2),
+                                             (bdaddr12only $B2, $D2):$BD2),
                         mnemonic#"\t$V1, $V3, $BD2", []>;
   }
 }
 
 // StoreSI* instructions are used to store an integer to memory, but the
 // addresses are more restricted than for normal stores.  If we are in the
 // situation of having to force either the address into a register or the
 // constant into a register, it's usually better to do the latter.
 // We therefore match the address in the same way as a normal store and
 // only use the StoreSI* instruction if the matched address is suitable.
 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
               ImmOpWithPattern imm>
-  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
+  : InstSI<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
            mnemonic#"\t$BD1, $I2",
            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
   let mayStore = 1;
 }
 
 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                ImmOpWithPattern imm>
-  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
+  : InstSIY<opcode, (outs), (ins (mviaddr20pair $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(operator imm:$I2, mviaddr20pair:$BD1)]> {
   let mayStore = 1;
 }
 
 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                ImmOpWithPattern imm>
-  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
+  : InstSIL<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(operator imm:$I2, mviaddr12pair:$BD1)]> {
   let mayStore = 1;
 }
 
 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
                        SDPatternOperator operator, ImmOpWithPattern imm> {
   let DispKey = mnemonic in {
     let DispSize = "12" in
       def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
     let DispSize = "20" in
       def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
   }
 }
 
 class StoreSSE<string mnemonic, bits<16> opcode>
-  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
+  : InstSSE<opcode, (outs),
+            (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
             mnemonic#"\t$BD1, $BD2", []> {
   let mayStore = 1;
 }
 
 class CondStoreRSY<string mnemonic, bits<16> opcode,
                    RegisterOperand cls, bits<5> bytes,
                    AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
+  : InstRSYb<opcode, (outs),
+             (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
              mnemonic#"$M3\t$R1, $BD2", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
   let CCMaskLast = 1;
 }
 
 // Like CondStoreRSY, but used for the raw assembly form.  The condition-code
 // mask is the third operand rather than being part of the mnemonic.
 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
                       RegisterOperand cls, bits<5> bytes,
                       AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
+  : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
              mnemonic#"\t$R1, $BD2, $M3", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 // Like CondStoreRSY, but with a fixed CC mask.
 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls, bits<5> bytes,
                         AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
+  : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2),
              mnemonic#V.suffix#"\t$R1, $BD2", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
   : InstRRE<opcode, (outs), (ins cls:$R1),
             mnemonic#"\t$R1", [(operator cls:$R1)]> {
   let R2 = 0;
 }
 
 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
                        SDPatternOperator operator, bits<5> bytes,
                        AddressingMode mode = bdaddr12only>
-  : InstS<opcode, (outs), (ins mode:$BD2),
+  : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
           mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
                          bits<5> bytes,
                          AddressingMode mode = bdaddr20only>
-  : InstSIY<opcode, (outs), (ins mode:$BD1),
+  : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1),
             mnemonic#"\t$BD1", []> {
   let mayLoad = 1;
   let AccessBytes = bytes;
   let I2 = 0;
 }
 
 class SideEffectAddressS<string mnemonic, bits<16> opcode,
                         SDPatternOperator operator,
                         AddressingMode mode = bdaddr12only>
-  : InstS<opcode, (outs), (ins mode:$BD2),
+  : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
           mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
 
 class LoadAddressRX<string mnemonic, bits<8> opcode,
                     SDPatternOperator operator, AddressingMode mode>
-  : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
+  : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set GR64:$R1, (operator mode:$XBD2))]>;
 
 class LoadAddressRXY<string mnemonic, bits<16> opcode,
                      SDPatternOperator operator, AddressingMode mode>
-  : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
+  : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2",
              [(set GR64:$R1, (operator mode:$XBD2))]>;
 
 multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
                              bits<16> rxyOpcode, SDPatternOperator operator> {
   let DispKey = mnemonic in {
     let DispSize = "12" in
       def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
   // complex.
   let AddedComplexity = 7;
 }
 
 class CondUnaryRSY<string mnemonic, bits<16> opcode,
                    SDPatternOperator operator, RegisterOperand cls,
                    bits<5> bytes, AddressingMode mode = bdaddr20only>
   : InstRSYb<opcode, (outs cls:$R1),
-             (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
+             (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
              mnemonic#"$M3\t$R1, $BD2",
              [(set cls:$R1,
                    (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
                                     cond4:$valid, cond4:$M3))]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
   let CCMaskLast = 1;
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let MemKey = mnemonic#cls;
   let MemType = "target";
 }
 
 // Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
 // mask is the third operand rather than being part of the mnemonic.
 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
                       RegisterOperand cls, bits<5> bytes,
                       AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
+  : InstRSYb<opcode, (outs cls:$R1),
+             (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
              mnemonic#"\t$R1, $BD2, $M3", []> {
   let mayLoad = 1;
   let AccessBytes = bytes;
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 // Like CondUnaryRSY, but with a fixed CC mask.
 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls, bits<5> bytes,
                         AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
+  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
              mnemonic#V.suffix#"\t$R1, $BD2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
   let isAsmParserOnly = V.alternate;
   let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
                             SDPatternOperator operator,
                             RegisterOperand cls, bits<5> bytes,
                             AddressingMode mode = bdaddr20only> {
   let isCodeGenOnly = 1 in
     def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
   def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
 }
 
 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
               RegisterOperand cls, bits<5> bytes,
               AddressingMode mode = bdxaddr12only>
-  : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
+  : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set cls:$R1, (operator mode:$XBD2))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                RegisterOperand cls, bits<5> bytes>
-  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
+  : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let mayLoad = 1;
   let AccessBytes = bytes;
   let M3 = 0;
 }
 
 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                RegisterOperand cls, bits<5> bytes,
                AddressingMode mode = bdxaddr20only>
-  : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
+  : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2",
              [(set cls:$R1, (operator mode:$XBD2))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
def "" : InstVRRa<opcode, (outs VR128:$V1),
                      mnemonic#"\t$V1, $V2, $M3, $M5", []>;
   def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
                                             imm32zx4:$M3, 0)>;
 }
 
 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                TypedReg tr, bits<5> bytes, bits<4> type = 0>
-  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
+  : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$V1, $XBD2",
             [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> {
   let M3 = type;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
-  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+  : InstVRX<opcode, (outs VR128:$V1),
+            (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
             mnemonic#"\t$V1, $XBD2, $M3", []> {
   let mayLoad = 1;
 }
 
 multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
   let mayLoad = 1, AccessBytes = 16 in {
     def Align : InstVRX<opcode, (outs VR128:$V1),
-                        (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+                        (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
                         mnemonic#"\t$V1, $XBD2, $M3", []>;
     let M3 = 0 in
-      def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
+      def "" : InstVRX<opcode, (outs VR128:$V1),
+                       (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
                        mnemonic#"\t$V1, $XBD2", []>;
   }
 }
 
 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
                          RegisterOperand cls>
-  : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+  : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2", []>;
 
 class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
                           RegisterOperand cls>
-  : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
+  : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2", []>;
 
 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
                             RegisterOperand cls>
   : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
              mnemonic#"\t$R1, $RI2", []> {
   // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
   // However, BDXs have two extra operands and are therefore 6 units more

 }
 
 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
                          ImmOpWithPattern imm1, ImmOpWithPattern imm2>
   : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
            mnemonic#"\t$I1, $I2", []>;
 
 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
-  : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+  : InstSI<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
            mnemonic#"\t$BD1, $I2", []>;
 
 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
                           SDPatternOperator operator, ImmOpWithPattern imm>
-  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+  : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
 
 class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
-  : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
+  : InstSSa<opcode, (outs), (ins (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
+                                 (bdaddr12only $B2, $D2):$BD2),
             mnemonic#"\t$BDL1, $BD2", []>;
 
 class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
   : InstSSb<opcode,
-            (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
+            (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+                         (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
             mnemonic#"\t$BDL1, $BDL2", []>;
 
 class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
-  : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
+  : InstSSf<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1,
+                                 (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
             mnemonic#"\t$BD1, $BDL2", []>;
 
 class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
-  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
+  : InstSSE<opcode, (outs),
+            (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
             mnemonic#"\t$BD1, $BD2", []>;
 
 class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
                                RegisterOperand cls1, RegisterOperand cls2>
   : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
            mnemonic#"\t$R1, $R2", []> {
     let Constraints = "$R1 = $R1src, $R2 = $R2src";
     let DisableEncoding = "$R1src, $R2src";
: InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
              mnemonic#"\t$R1, $I2",
              [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                RegisterOperand cls>
-  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
+  : InstRSa<opcode, (outs cls:$R1),
+            (ins cls:$R1src, (shift12only $B2, $D2):$BD2),
             mnemonic#"\t$R1, $BD2",
             [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
   let R3 = 0;
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 RegisterOperand cls>
-  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
+  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2",
              [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
 
 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
                         SDPatternOperator operator, RegisterOperand cls> {
   let NumOpsKey = mnemonic in {
     let NumOpsValue = "3" in
       def K  : BinaryRSY<mnemonic#"k", opcode2, operator, cls>,
                Requires<[FeatureDistinctOps]>;
     let NumOpsValue = "2" in
       def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
   }
 }
 
 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
   : InstRSLb<opcode, (outs cls:$R1),
-             (ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
+             (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
              mnemonic#"\t$R1, $BDL2, $M3", []> {
   let mayLoad = 1;
 }
 
 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
                AddressingMode mode = bdxaddr12only>
-  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
+  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                   RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
-  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
+  : InstRXE<opcode, (outs cls:$R1),
+            (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set cls:$R1, (operator cls:$R1src,
                                      (load bdxaddr12only:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
   let M3 = 0;
 }
 
 class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 RegisterOperand cls1, RegisterOperand cls2,
                 SDPatternOperator load, bits<5> bytes>
-  : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
+  : InstRXF<opcode, (outs cls1:$R1),
+            (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $R3, $XBD2",
             [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
                 AddressingMode mode = bdxaddr20only>
-  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
+  : InstRXYa<opcode, (outs cls:$R1),
+             (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2",
              [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
let DispKey = mnemonic # cls in {
     let DispSize = "20" in
       def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
                          bdxaddr20pair>;
   }
 }
 
 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                Operand imm, AddressingMode mode = bdaddr12only>
-  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
+  : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
            mnemonic#"\t$BD1, $I2",
            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
   let mayLoad = 1;
   let mayStore = 1;
 }
 
 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 Operand imm, AddressingMode mode = bdaddr20only>
-  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
+  : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
   let mayLoad = 1;
   let mayStore = 1;
 }
 
 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
                         bits<16> siyOpcode, SDPatternOperator operator,
                         Operand imm> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
     let DispSize = "20" in
       def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
   }
 }
 
 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
-  : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
+  : InstSSF<opcode, (outs cls:$R3),
+            (ins (bdaddr12pair $B1, $D1):$BD1, (bdaddr12pair $B2, $D2):$BD2),
             mnemonic#"\t$R3, $BD1, $BD2", []> {
   let mayLoad = 1;
 }
 
 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  TypedReg tr, bits<4> type>
   : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
              mnemonic#"\t$V1, $I2, $I3",

 }
 
 class BinaryVRRk<string mnemonic, bits<16> opcode>
   : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
              mnemonic#"\t$V1, $V2, $M3", []>;
 
 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  TypedReg tr1, TypedReg tr2, bits<4> type>
-  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
+  : InstVRSa<opcode, (outs tr1.op:$V1),
+             (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2),
              mnemonic#"\t$V1, $V3, $BD2",
              [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
                                                   shift12only:$BD2))]> {
   let M4 = type;
 }
 
 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
   : InstVRSa<opcode, (outs VR128:$V1),
-             (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
+             (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
              mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
 
 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  bits<5> bytes>
-  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
+  : InstVRSb<opcode, (outs VR128:$V1),
+             (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
              mnemonic#"\t$V1, $R3, $BD2",
              [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
   let M4 = 0;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  TypedReg tr, bits<4> type>
-  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
+  : InstVRSc<opcode, (outs GR64:$R1),
+             (ins tr.op:$V3, (shift12only $B2, $D2):$BD2),
              mnemonic#"\t$R1, $V3, $BD2",
              [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
   let M4 = type;
 }
 
 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
   : InstVRSc<opcode, (outs GR64:$R1),
-             (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
+             (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
              mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
 
 class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  bits<5> bytes>
-  : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
+  : InstVRSd<opcode, (outs VR128:$V1),
+             (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
              mnemonic#"\t$V1, $R3, $BD2",
              [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 TypedReg tr, bits<5> bytes>
-  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+  : InstVRX<opcode, (outs VR128:$V1),
+            (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
             mnemonic#"\t$V1, $XBD2, $M3",
             [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2,
                                                imm32zx4_timm:$M3))]> {
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
                     bits<5> bytes, AddressingMode mode = bdaddr12only>
-  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
             mnemonic#"\t$R1, $M3, $BD2", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
                      bits<5> bytes, AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $M3, $BD2", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
                              bits<16> rsyOpcode, RegisterOperand cls,
                              bits<5> bytes> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
     let DispSize = "20" in
       def Y  : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
                               bdaddr20pair>;
   }
 }
 
 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
   : InstRSLb<opcode, (outs),
-             (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
+             (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
+                  imm32zx4:$M3),
              mnemonic#"\t$R1, $BDL2, $M3", []> {
   let mayStore = 1;
 }
 
 class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 bits<5> bytes>
-  : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
+  : InstVSI<opcode, (outs VR128:$V1),
+            (ins (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
             mnemonic#"\t$V1, $BD2, $I3",
             [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
                      ImmOpWithPattern index>
-  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
+  : InstVRV<opcode, (outs),
+            (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
             mnemonic#"\t$V1, $VBD2, $M3", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
                      SDPatternOperator operator, TypedReg tr, bits<5> bytes,
                      ImmOpWithPattern index>
-  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
+  : InstVRX<opcode, (outs),
+            (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
             mnemonic#"\t$V1, $XBD2, $M3",
             [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
   let mayStore = 1;
   let AccessBytes = bytes;
 }
 
 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
                       RegisterOperand cls>
   : InstSSd<opcode, (outs),
-            (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
+            (ins (bdraddr12only $B1, $D1, $R1):$RBD1,
+                 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
             mnemonic#"\t$RBD1, $BD2, $R3", []>;
 
 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                 RegisterOperand cls1, RegisterOperand cls2>
   : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
            mnemonic#"\t$R1, $R2",
            [(set CC, (operator cls1:$R1, cls2:$R2))]> {
   let OpKey = mnemonic#cls1;
class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
   // However, BDXs have two extra operands and are therefore 6 units more
   // complex.
   let AddedComplexity = 7;
 }
 
 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
                 AddressingMode mode = bdxaddr12only>
-  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+  : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let isCompare = 1;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
-  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+  : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let isCompare = 1;
   let mayLoad = 1;
   let AccessBytes = bytes;
   let M3 = 0;
 }
 
 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
                  AddressingMode mode = bdxaddr20only>
-  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
+  : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$R1, $XBD2",
              [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let isCompare = 1;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
                          SDPatternOperator operator, RegisterOperand cls,
                          SDPatternOperator load, bits<5> bytes> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
                          load, bytes, bdxaddr12pair>;
     let DispSize = "20" in
       def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
                           load, bytes, bdxaddr20pair>;
   }
 }
 
 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
                 bits<5> bytes, AddressingMode mode = bdaddr12only>
-  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
             mnemonic#"\t$R1, $M3, $BD2", []> {
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
                  bits<5> bytes, AddressingMode mode = bdaddr20only>
-  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
+  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $M3, $BD2", []> {
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
                          RegisterOperand cls, bits<5> bytes> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
     let DispSize = "20" in
       def Y  : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
   }
 }
 
 class CompareSSb<string mnemonic, bits<8> opcode>
   : InstSSb<opcode,
-            (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
+            (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+                         (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
             mnemonic#"\t$BDL1, $BDL2", []> {
   let isCompare = 1;
   let mayLoad = 1;
 }
 
 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                 SDPatternOperator load, ImmOpWithPattern imm,
                 AddressingMode mode = bdaddr12only>
-  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
+  : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
            mnemonic#"\t$BD1, $I2",
            [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
   let isCompare = 1;
   let mayLoad = 1;
 }
 
 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  SDPatternOperator load, ImmOpWithPattern imm>
-  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+  : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> {
   let isCompare = 1;
   let mayLoad = 1;
 }
 
 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  SDPatternOperator load, ImmOpWithPattern imm,
                  AddressingMode mode = bdaddr20only>
-  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
+  : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
   let isCompare = 1;
   let mayLoad = 1;
 }
 
 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
                          SDPatternOperator operator, SDPatternOperator load,
class CompareVRRh<string mnemonic, bits<16> opcode>
   : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
              mnemonic#"\t$V1, $V2, $M3", []> {
   let isCompare = 1;
 }
 
 class TestInherentS<string mnemonic, bits<16> opcode,
                     SDPatternOperator operator>
   : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> {
-  let BD2 = 0;
+  let B2 = 0;
+  let D2 = 0;
 }
 
 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
               RegisterOperand cls>
-  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+  : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> {
   let M3 = 0;
 }
 
 class TestBinarySIL<string mnemonic, bits<16> opcode,
                     SDPatternOperator operator, ImmOpWithPattern imm>
-  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+  : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
 
 class TestRSL<string mnemonic, bits<16> opcode>
-  : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
+  : InstRSLa<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
              mnemonic#"\t$BDL1", []> {
   let mayLoad = 1;
 }
 
 class TestVRRg<string mnemonic, bits<16> opcode>
   : InstVRRg<opcode, (outs), (ins VR128:$V1),
              mnemonic#"\t$V1", []>;
 
 class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
-  : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
-                                 shift12only:$BD2, imm32zx4:$I3),
+  : InstSSc<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
+                                 (shift12only $B2, $D2):$BD2, imm32zx4:$I3),
             mnemonic#"\t$BDL1, $BD2, $I3", []>;
 
 class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
                             RegisterOperand cls1, RegisterOperand cls2,
                             RegisterOperand cls3>
   : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
              mnemonic#"\t$R1, $R2, $R3", []> {
   let M4 = 0;
multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
                                           RegisterOperand cls2> {
   def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
   def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
 }
 
 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
                            RegisterOperand cls>
   : InstSSF<opcode, (outs),
-            (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
+            (ins (bdaddr12only $B1, $D1):$BD1,
+                 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
             mnemonic#"\t$BD1, $BD2, $R3", []>;
 
 class TernaryRRFa<string mnemonic, bits<16> opcode,
                  RegisterOperand cls1, RegisterOperand cls2,
                  RegisterOperand cls3>
   : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
              mnemonic#"\t$R1, $R2, $R3, $M4", []>;
 
class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
   let OpType = "reg";
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
                 bits<5> bytes, AddressingMode mode = bdaddr12only>
   : InstRSb<opcode, (outs cls:$R1),
-            (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
+            (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
             mnemonic#"\t$R1, $M3, $BD2", []> {
 
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
                 bits<5> bytes, AddressingMode mode = bdaddr20only>
   : InstRSYb<opcode, (outs cls:$R1),
-             (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
+             (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $M3, $BD2", []> {
 
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
                          RegisterOperand cls, bits<5> bytes> {
   let DispKey = mnemonic # cls in {
     let DispSize = "12" in
       def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
     let DispSize = "20" in
       def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
   }
 }
 
 class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
                           RegisterOperand cls1, RegisterOperand cls2>
   : InstRSa<opcode, (outs),
-            (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
+            (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2),
             mnemonic#"\t$R1, $R3, $BD2", []>;
 
 class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
                            RegisterOperand cls1, RegisterOperand cls2>
   : InstRSYa<opcode, (outs),
-             (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
+             (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2", []>;
 
 class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
                                 RegisterOperand cls1, RegisterOperand cls2>
   : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
-            (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
+            (ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2),
             mnemonic#"\t$R1, $R3, $BD2", []> {
     let Constraints = "$R1 = $R1src, $R3 = $R3src";
     let DisableEncoding = "$R1src, $R3src";
 }
 
 class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
                                  RegisterOperand cls1, RegisterOperand cls2>
   : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
-             (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
+             (ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2", []> {
     let Constraints = "$R1 = $R1src, $R3 = $R3src";
     let DisableEncoding = "$R1src, $R3src";
 }
 
 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  RegisterOperand cls1, RegisterOperand cls2,
                  SDPatternOperator load, bits<5> bytes>
   : InstRXF<opcode, (outs cls1:$R1),
-            (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
+            (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
             mnemonic#"\t$R1, $R3, $XBD2",
             [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
                                       (load bdxaddr12only:$XBD2)))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;

 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
   : InstVRRe<opcode, (outs VR128:$V1),
              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
              mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
 
 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                   TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
   : InstVRSb<opcode, (outs tr1.op:$V1),
-             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
+             (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2),
              mnemonic#"\t$V1, $R3, $BD2",
              [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
                                                   cls:$R3,
                                                   shift12only:$BD2))]> {
   let Constraints = "$V1 = $V1src";
   let DisableEncoding = "$V1src";
   let M4 = type;
 }
 
 class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
                                       imm32zx4:$M3, imm32zx4:$M4),
              mnemonic#"\t$R1, $V2, $M3, $M4", []>;
 
 class TernaryVRRj<string mnemonic, bits<16> opcode>
   : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
                                         VR128:$V3, imm32zx4:$M4),
              mnemonic#"\t$V1, $V2, $V3, $M4", []>;
 
 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
   : InstVRSb<opcode, (outs VR128:$V1),
-             (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
+             (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
+                  imm32zx4:$M4),
              mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
   let Constraints = "$V1 = $V1src";
   let DisableEncoding = "$V1src";
 }
 
 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
                  ImmOpWithPattern index>
   : InstVRV<opcode, (outs VR128:$V1),
-           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
+           (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
            mnemonic#"\t$V1, $VBD2, $M3", []> {
   let Constraints = "$V1 = $V1src";
   let DisableEncoding = "$V1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
 
 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index>
   : InstVRX<opcode, (outs tr1.op:$V1),
-           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
+           (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
            mnemonic#"\t$V1, $XBD2, $M3",
            [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
                                                 bdxaddr12only:$XBD2,
                                                 index:$M3))]> {
   let Constraints = "$V1 = $V1src";
   let DisableEncoding = "$V1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
                                        RegisterOperand cls3> {
   def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
   def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
 }
 
 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
                               RegisterOperand cls>
   : InstSSe<opcode, (outs),
-            (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
+            (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3,
+                 (bdaddr12only $B4, $D4):$BD4),
             mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
 
 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                   RegisterOperand cls, AddressingMode mode = bdaddr20only>
-  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
+  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2",
              [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
   let mayLoad = 1;
   let mayStore = 1;
 }
 
 class CmpSwapRRE<string mnemonic, bits<16> opcode,
                  RegisterOperand cls1, RegisterOperand cls2>
   : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
             mnemonic#"\t$R1, $R2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let mayStore = 1;
 }
 
 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
                 RegisterOperand cls, AddressingMode mode = bdaddr12only>
-  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
+  : InstRSa<opcode, (outs cls:$R1),
+            (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
             mnemonic#"\t$R1, $R3, $BD2",
             [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let mayStore = 1;
 }
 
 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
-  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
+  : InstRSYa<opcode, (outs cls:$R1),
+             (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
              mnemonic#"\t$R1, $R3, $BD2",
              [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let mayStore = 1;
 }
 
: InstRIEf<opcode, (outs cls1:$R1),
              (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
                   imm32zx8:$I5),
              mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
-  : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
+  : InstRXYb<opcode, (outs),
+             (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
              mnemonic#"\t$M1, $XBD2",
              [(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>;
 
 class PrefetchRILPC<string mnemonic, bits<12> opcode,
                     SDPatternOperator operator>
   : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2),
              mnemonic#"\t$M1, $RI2",
              [(operator imm32zx4_timm:$M1, pcrel32:$RI2)]> {
   // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
   // However, BDXs have two extra operands and are therefore 6 units more
   // complex.
   let AddedComplexity = 7;
 }
 
 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
   : InstSMI<opcode, (outs),
-            (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
+            (ins imm32zx4:$M1, brtarget16bpp:$RI2,
+                 (bdaddr12only $B3, $D3):$BD3),
             mnemonic#"\t$M1, $RI2, $BD3", []>;
 
 class BranchPreloadMII<string mnemonic, bits<8> opcode>
   : InstMII<opcode, (outs),
             (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
             mnemonic#"\t$M1, $RI2, $RI3", []>;
 
 // A floating-point load-and test operation.  Create both a normal unary
class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
                     ImmOpWithPattern imm>
   : Pseudo<(outs cls:$R1), (ins imm:$I2),
            [(set cls:$R1, (operator imm:$I2))]>;
 
 // Like UnaryRXY, but expanded after RA depending on the choice of register.
 class UnaryRXYPseudo<string key, SDPatternOperator operator,
                      RegisterOperand cls, bits<5> bytes,
                      AddressingMode mode = bdxaddr20only>
-  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
+  : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
            [(set cls:$R1, (operator mode:$XBD2))]> {
   let OpKey = key#"r"#cls;
   let OpType = "mem";
   let mayLoad = 1;
   let Has20BitOffset = 1;
   let HasIndex = 1;
   let AccessBytes = bytes;
 }

 }
 
 // A pseudo that is used during register allocation when folding a memory
 // operand. The 3-address register instruction with a spilled source cannot
 // be converted directly to a target 2-address reg/mem instruction.
 // Mapping:  <INSN>R  ->  MemFoldPseudo  ->  <INSN>
 class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
                     AddressingMode mode>
-  : Pseudo<(outs cls:$R1), (ins cls:$R2, mode:$XBD2), []> {
+  : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
     let OpKey = !subst("mscrk", "msrkc",
                 !subst("msgcrk", "msgrkc",
                 mnemonic#"rk"#cls));
     let OpType = "mem";
     let MemKey = mnemonic#cls;
     let MemType = "pseudo";
     let mayLoad = 1;
     let AccessBytes = bytes;
     let HasIndex = 1;
     let hasNoSchedulingInfo = 1;
 }
 
 // Same as MemFoldPseudo but for mapping a W... vector instruction
 class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes,
                     AddressingMode mode>
   : MemFoldPseudo<mnemonic, cls, bytes, mode> {
     let OpKey = mnemonic#"r"#"MemFold"#cls;
 }
 
 class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
                            AddressingMode mode>
-  : Pseudo<(outs cls:$R1), (ins cls:$R2, cls:$R3, mode:$XBD2), []> {
+  : Pseudo<(outs cls:$R1),
+           (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
     let OpKey = mnemonic#"r"#"MemFold"#cls;
     let OpType = "mem";
     let MemKey = mnemonic#cls;
     let MemType = "pseudo";
     let mayLoad = 1;
     let AccessBytes = bytes;
     let HasIndex = 1;
     let hasNoSchedulingInfo = 1;
 }
 
 // Same as MemFoldPseudo but for Load On Condition with CC operands.
 class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
                              AddressingMode mode>
   : Pseudo<(outs cls:$R1),
-           (ins cls:$R2, mode:$XBD2, cond4:$valid, cond4:$M3), []> {
+           (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
     let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls;
     let OpType = "mem";
     let MemKey = mnemonic#cls;
     let MemType = "pseudo";
     let mayLoad = 1;
     let AccessBytes = bytes;
     let hasNoSchedulingInfo = 1;
 }
 
 // Like CompareRI, but expanded after RA depending on the choice of register.
 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
                       ImmOpWithPattern imm>
   : Pseudo<(outs), (ins cls:$R1, imm:$I2),
            [(set CC, (operator cls:$R1, imm:$I2))]> {
   let isCompare = 1;
 }
 
 // Like CompareRXY, but expanded after RA depending on the choice of register.
 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
                        SDPatternOperator load, bits<5> bytes,
                        AddressingMode mode = bdxaddr20only>
-  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
+  : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
            [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
   let mayLoad = 1;
   let Has20BitOffset = 1;
   let HasIndex = 1;
   let AccessBytes = bytes;
 }
 
 // Like TestBinarySIL, but expanded later.
 class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm>
-  : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
+  : Pseudo<(outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
            [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
 
 // Like CondBinaryRRF, but expanded after RA depending on the choice of
 // register.
 class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1,
                           RegisterOperand cls2>
   : Pseudo<(outs cls1:$R1),
            (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),

 }
 
 // Like CondUnaryRSY, but expanded after RA depending on the choice of
 // register.
 class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator,
                          RegisterOperand cls, bits<5> bytes,
                          AddressingMode mode = bdaddr20only>
   : Pseudo<(outs cls:$R1),
-           (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
+           (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
            [(set cls:$R1,
                  (z_select_ccmask (operator mode:$BD2), cls:$R1src,
                                   cond4:$valid, cond4:$R3))]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
   let CCMaskLast = 1;
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";
   let MemKey = mnemonic#cls;
   let MemType = "target";
 }
 
 // Like CondStoreRSY, but expanded after RA depending on the choice of
 // register.
 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
                          AddressingMode mode = bdaddr20only>
-  : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
+  : Pseudo<(outs),
+           (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {
   let mayStore = 1;
   let AccessBytes = bytes;
   let CCMaskLast = 1;
 }
 
 // Like StoreRXY, but expanded after RA depending on the choice of register.
 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
                      bits<5> bytes, AddressingMode mode = bdxaddr20only>
-  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
+  : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
            [(operator cls:$R1, mode:$XBD2)]> {
   let mayStore = 1;
   let Has20BitOffset = 1;
   let HasIndex = 1;
   let AccessBytes = bytes;
 }
 
 // Like RotateSelectRIEf, but expanded after RA depending on the choice

 // An alias of a UnaryVRR*, but with different register sizes.
 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
   : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
           [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>;
 
 // An alias of a UnaryVRX, but with different register sizes.
 class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
                     AddressingMode mode = bdxaddr12only>
-  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
+  : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2),
           [(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>;
 
 // An alias of a StoreVRX, but with different register sizes.
 class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
                     AddressingMode mode = bdxaddr12only>
-  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
+  : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2),
           [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
 
 // An alias of a BinaryRI, but with different register sizes.
 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
                     ImmOpWithPattern imm>
   : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
   let Constraints = "$R1 = $R1src";

llvm/lib/Target/SystemZ/SystemZInstrInfo.td

def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>,
              Requires<[FeatureMiscellaneousExtensions2]>;
   }
 }
 
 // NOPs.  These are again variants of the conditional branches, with the
 // condition mask set to "never".  NOP_bare can't be an InstAlias since it
 // would need R0D hard coded which is not part of ADDR64BitRegClass.
 def NOP  : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
-let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in
+let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
   def NOP_bare  : InstRXb<0x47,(outs), (ins), "nop", []>;
 def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
 def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
 
 // An alias of BRC 0, label
 def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
 
 // An alias of BRCL 0, label
def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
                                               brtarget32:$I2),
                                  ".insn ril,$enc,$R1,$I2", []>;
   def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
                                                uimm32:$I2),
                                   ".insn rilu,$enc,$R1,$I2", []>;
   def InsnRIS : DirectiveInsnRIS<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1,
                                       imm32sx8:$I2, imm32zx4:$M3,
-                                      bdaddr12only:$BD4),
+                                      (bdaddr12only $B4, $D4):$BD4),
                                  ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
   def InsnRR : DirectiveInsnRR<(outs),
                                (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
                                ".insn rr,$enc,$R1,$R2", []>;
   def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,
                                               AnyReg:$R1, AnyReg:$R2),
                                  ".insn rre,$enc,$R1,$R2", []>;
   def InsnRRF : DirectiveInsnRRF<(outs),
                                  (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
                                       AnyReg:$R3, imm32zx4:$M4),
                                  ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
   def InsnRRS : DirectiveInsnRRS<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1,
                                       AnyReg:$R2, imm32zx4:$M3,
-                                      bdaddr12only:$BD4),
+                                      (bdaddr12only $B4, $D4):$BD4),
                                  ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
   def InsnRS  : DirectiveInsnRS<(outs),
                                 (ins imm64zx32:$enc, AnyReg:$R1,
-                                     AnyReg:$R3, bdaddr12only:$BD2),
+                                     AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
                                 ".insn rs,$enc,$R1,$R3,$BD2", []>;
   def InsnRSE : DirectiveInsnRSE<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1,
-                                      AnyReg:$R3, bdaddr12only:$BD2),
+                                      AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
                                  ".insn rse,$enc,$R1,$R3,$BD2", []>;
   def InsnRSI : DirectiveInsnRSI<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1,
                                       AnyReg:$R3, brtarget16:$RI2),
                                  ".insn rsi,$enc,$R1,$R3,$RI2", []>;
   def InsnRSY : DirectiveInsnRSY<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1,
-                                      AnyReg:$R3, bdaddr20only:$BD2),
+                                      AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2),
                                  ".insn rsy,$enc,$R1,$R3,$BD2", []>;
   def InsnRX  : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
-                                             bdxaddr12only:$XBD2),
+                                             (bdxaddr12only $B2, $D2, $X2):$XBD2),
                                 ".insn rx,$enc,$R1,$XBD2", []>;
   def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
-                                              bdxaddr12only:$XBD2),
+                                              (bdxaddr12only $B2, $D2, $X2):$XBD2),
                                  ".insn rxe,$enc,$R1,$XBD2", []>;
   def InsnRXF : DirectiveInsnRXF<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1,
-                                      AnyReg:$R3, bdxaddr12only:$XBD2),
+                                      AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
                                  ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
   def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
-                                              bdxaddr20only:$XBD2),
+                                              (bdxaddr20only $B2, $D2, $X2):$XBD2),
                                  ".insn rxy,$enc,$R1,$XBD2", []>;
   def InsnS : DirectiveInsnS<(outs),
-                             (ins imm64zx32:$enc, bdaddr12only:$BD2),
+                             (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
                              ".insn s,$enc,$BD2", []>;
   def InsnSI : DirectiveInsnSI<(outs),
-                               (ins imm64zx32:$enc, bdaddr12only:$BD1,
+                               (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1,
                                     imm32sx8:$I2),
                                ".insn si,$enc,$BD1,$I2", []>;
   def InsnSIY : DirectiveInsnSIY<(outs),
                                  (ins imm64zx48:$enc,
-                                      bdaddr20only:$BD1, imm32zx8:$I2),
+                                      (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2),
                                  ".insn siy,$enc,$BD1,$I2", []>;
   def InsnSIL : DirectiveInsnSIL<(outs),
-                                 (ins imm64zx48:$enc, bdaddr12only:$BD1,
+                                 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
                                       imm32zx16:$I2),
                                  ".insn sil,$enc,$BD1,$I2", []>;
   def InsnSS : DirectiveInsnSS<(outs),
-                               (ins imm64zx48:$enc, bdraddr12only:$RBD1,
-                                    bdaddr12only:$BD2, AnyReg:$R3),
+                               (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
+                                    (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
                                ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
   def InsnSSE : DirectiveInsnSSE<(outs),
                                  (ins imm64zx48:$enc,
-                                      bdaddr12only:$BD1,bdaddr12only:$BD2),
+                                      (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2),
                                  ".insn sse,$enc,$BD1,$BD2", []>;
   def InsnSSF : DirectiveInsnSSF<(outs),
-                                 (ins imm64zx48:$enc, bdaddr12only:$BD1,
-                                      bdaddr12only:$BD2, AnyReg:$R3),
+                                 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
+                                      (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
                                  ".insn ssf,$enc,$BD1,$BD2,$R3", []>;
   def InsnVRI : DirectiveInsnVRI<(outs),
                                  (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
                                   imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
                                  ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
   def InsnVRR : DirectiveInsnVRR<(outs),
                                  (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
                                   VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
                                   imm32zx4:$M6),
                                   ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
   def InsnVRS : DirectiveInsnVRS<(outs),
                                  (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
-                                  bdaddr12only:$BD2, imm32zx4:$M4),
+                                  (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
                                  ".insn vrs,$enc,$BD2,$M4", []>;
   def InsnVRV : DirectiveInsnVRV<(outs),
                                  (ins imm64zx48:$enc, VR128:$V1,
-                                      bdvaddr12only:$VBD2, imm32zx4:$M3),
+                                      (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
                                  ".insn vrv,$enc,$V1,$VBD2,$M3", []>;
   def InsnVRX : DirectiveInsnVRX<(outs),
                                  (ins imm64zx48:$enc, VR128:$V1,
-                                  bdxaddr12only:$XBD2, imm32zx4:$M3),
+                                  (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
                                  ".insn vrx,$enc,$V1,$XBD2,$M3", []>;
   def InsnVSI : DirectiveInsnVSI<(outs),
                                  (ins imm64zx48:$enc, VR128:$V1,
-                                  bdaddr12only:$BD2, imm32zx8:$I3),
+                                  (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
                                   ".insn vsi,$enc,$V1,$BD2,$I3", []>;
 }
 
 //===----------------------------------------------------------------------===//
 // Peepholes.
 //===----------------------------------------------------------------------===//
 
 // Avoid generating 2 XOR instructions. (xor (and x, y), y) is

llvm/lib/Target/SystemZ/SystemZInstrVector.td

let Predicates = [FeatureVector] in {
   // Load to block boundary.  The number of loaded bytes is only known
   // at run time.  The instruction is really polymorphic, but v128b matches
   // the return type of the associated intrinsic.
   def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>;
 
   // Load count to block boundary.
   let Defs = [CC] in
     def LCBB : InstRXE<0xE727, (outs GR32:$R1),
-                               (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
+                               (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
                        "lcbb\t$R1, $XBD2, $M3",
                        [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2,
                                                       imm32zx4_timm:$M3))]>;
 
   // Load with length.  The number of loaded bytes is only known at run time.
   def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>;
 
   // Load multiple.

llvm/lib/Target/SystemZ/SystemZOperands.td

 // Constructs an instruction operand for an addressing mode.  FORMAT,
 // BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
 // AddressAsmOperand.  OPERANDS is a list of individual operands
 // (base register, displacement, etc.).
 class AddressOperand<string bitsize, string dispsize, string length,
                      string format, dag operands>
   : Operand<!cast<ValueType>("i"#bitsize)> {
   let PrintMethod = "print"#format#"Operand";
-  let EncoderMethod = "get"#format#dispsize#length#"Encoding";
-  let DecoderMethod =
-    "decode"#format#bitsize#"Disp"#dispsize#length#"Operand";
   let OperandType = "OPERAND_MEMORY";
   let MIOperandInfo = operands;
   let ParserMatchClass =
     !cast<AddressAsmOperand>(format#bitsize#"Disp"#dispsize#length);
 }
 
 // Constructs both a DAG pattern and instruction operand for an addressing mode.
 // FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated

 
 // A BDMode paired with an immediate length operand of LENSIZE bits.
 class BDLMode<string type, string bitsize, string dispsize, string suffix,
               string lensize>
   : AddressingMode<type, bitsize, dispsize, suffix, "Len"#lensize, 3,
                    "BDLAddr",
                    (ops !cast<RegisterOperand>("ADDR"#bitsize),
                         !cast<Operand>("disp"#dispsize#"imm"#bitsize),
-                        !cast<Operand>("imm"#bitsize))>;
+                        !cast<Operand>("len"#lensize#"imm"#bitsize))>;
 
 // A BDMode paired with a register length operand.
 class BDRMode<string type, string bitsize, string dispsize, string suffix>
   : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDRAddr",
                    (ops !cast<RegisterOperand>("ADDR"#bitsize),
                         !cast<Operand>("disp"#dispsize#"imm"#bitsize),
                         !cast<RegisterOperand>("GR"#bitsize))>;
 

 defm imm64zx32n : Immediate<i64, [{
   return isUInt<32>(-N->getSExtValue());
 }], NEGUIMM32, "U32Imm">;
 
 defm imm64zx48 : Immediate<i64, [{
   return isUInt<64>(N->getZExtValue());
 }], UIMM48, "U48Imm">;
 
-let OperandType = "OPERAND_IMMEDIATE" in
-  def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
+class Imm64 : ImmLeaf<i64, [{}]>, Operand<i64> {
+  let OperandType = "OPERAND_IMMEDIATE";
+}
+def imm64 : Imm64;
+def len4imm64 : Imm64 {
+  let EncoderMethod = "getLenEncoding<4>";
+  let DecoderMethod = "decodeLenOperand<4>";
+}
+def len8imm64 : Imm64 {
+  let EncoderMethod = "getLenEncoding<8>";
+  let DecoderMethod = "decodeLenOperand<8>";
+}
 
 //===----------------------------------------------------------------------===//
 // Floating-point immediates
 //===----------------------------------------------------------------------===//
 
 // Floating-point zero.
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 
def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
   let DecoderMethod = "decodePC32DBLOperand";
 }
 
 //===----------------------------------------------------------------------===//
 // Addressing modes
 //===----------------------------------------------------------------------===//
 
 // 12-bit displacement operands.
+let EncoderMethod = "getDisp12Encoding",
+    DecoderMethod = "decodeU12ImmOperand" in {
   def disp12imm32 : Operand<i32>;
   def disp12imm64 : Operand<i64>;
+}
 
 // 20-bit displacement operands.
+let EncoderMethod = "getDisp20Encoding",
+    DecoderMethod = "decodeS20ImmOperand" in {
   def disp20imm32 : Operand<i32>;
   def disp20imm64 : Operand<i64>;
+}
 
 def BDAddr32Disp12      : AddressAsmOperand<"BDAddr",   "32", "12">;
 def BDAddr32Disp20      : AddressAsmOperand<"BDAddr",   "32", "20">;
 def BDAddr64Disp12      : AddressAsmOperand<"BDAddr",   "64", "12">;
 def BDAddr64Disp20      : AddressAsmOperand<"BDAddr",   "64", "20">;
 def BDXAddr64Disp12     : AddressAsmOperand<"BDXAddr",  "64", "12">;
 def BDXAddr64Disp20     : AddressAsmOperand<"BDXAddr",  "64", "20">;
 def BDLAddr64Disp12Len4 : AddressAsmOperand<"BDLAddr",  "64", "12", "Len4">;

llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt

 # CHECK: clij %r0, 0, 14, 0x9cc
 0xec 0x0e 0x00 0x00 0x00 0x7f
 
 # 0x000009d2:
 # CHECK: clij %r0, 0, 15, 0x9d2
 0xec 0x0f 0x00 0x00 0x00 0x7f
 
 # 0x000009d8:
-# CHECK: exrl %r0, 0x9d8
+# CHECK: exrl 0, 0x9d8
 0xc6 0x00 0x00 0x00 0x00 0x00
 
 # 0x000009de:
 # CHECK: exrl %r15, 0x9de
 0xc6 0xf0 0x00 0x00 0x00 0x00
 
 # 0x000009e4:
-# CHECK: exrl %r0, 0x9e2
+# CHECK: exrl 0, 0x9e2
 0xc6 0x00 0xff 0xff 0xff 0xff
 
 # 0x000009ea:
 # CHECK: exrl %r15, 0x9e8
 0xc6 0xf0 0xff 0xff 0xff 0xff
 
 # 0x000009f0:
-# CHECK: exrl %r0, 0xffffffff000009f0
+# CHECK: exrl 0, 0xffffffff000009f0
 0xc6 0x00 0x80 0x00 0x00 0x00
 
 # 0x000009f6:
 # CHECK: exrl %r15, 0xffffffff000009f6
 0xc6 0xf0 0x80 0x00 0x00 0x00
 
 # 0x000009fc:
-# CHECK: exrl %r0, 0x1000009fa
+# CHECK: exrl 0, 0x1000009fa
 0xc6 0x00 0x7f 0xff 0xff 0xff
 
 # 0x00000a02:
 # CHECK: exrl %r15, 0x100000a00
 0xc6 0xf0 0x7f 0xff 0xff 0xff
 
 # 0x00000a08:
 # CHECK: brxh %r0, %r1, 0xa08

llvm/test/MC/Disassembler/SystemZ/insns.txt

 0x45 0xff 0x1f 0xff
 
 # CHECK: balr %r0, %r1
 0x05 0x01
 
 # CHECK: balr %r0, %r15
 0x05 0x0f
 
+# CHECK: balr %r1, 0
+0x05 0x10
+
 # CHECK: balr %r14, %r9
 0x05 0xe9
 
 # CHECK: balr %r15, %r1
 0x05 0xf1
 
 # CHECK: bas %r0, 0
 0x4d 0x00 0x00 0x00

 0x4d 0xff 0x1f 0xff
 
 # CHECK: basr %r0, %r1
 0x0d 0x01
 
 # CHECK: basr %r0, %r15
 0x0d 0x0f
 
+# CHECK: basr %r1, 0
+0x0d 0x10
+
 # CHECK: basr %r14, %r9
 0x0d 0xe9
 
 # CHECK: basr %r15, %r1
 0x0d 0xf1
 
 # CHECK: bassm %r0, %r1
 0x0c 0x01
 
 # CHECK: bassm %r0, %r15
 0x0c 0x0f
 
+# CHECK: bassm %r1, 0
+0x0c 0x10
+
 # CHECK: bassm %r14, %r9
 0x0c 0xe9
 
 # CHECK: bassm %r15, %r1
 0x0c 0xf1
 
 # CHECK: bc 0, 0
 0x47 0x00 0x00 0x00

 0x07 0xb3
 
 # CHECK: bler %r2
 0x07 0xc2
 
 # CHECK: bnhr %r1
 0x07 0xd1
 
-# CHECK: bnor %r0
+# CHECK: bnor 0
 0x07 0xe0
 
 # CHECK: br %r1
 0x07 0xf1
 
 # CHECK: br %r14
 0x07 0xfe
 

 0xb2 0x58 0x00 0x78
 
 # CHECK: bsm %r0, %r1
 0x0b 0x01
 
 # CHECK: bsm %r0, %r15
 0x0b 0x0f
 
+# CHECK: bsm %r1, 0
+0x0b 0x10
+
 # CHECK: bsm %r14, %r9
 0x0b 0xe9
 
 # CHECK: bsm %r15, %r1
 0x0b 0xf1
 
 # CHECK: bxh %r0, %r0, 0
 0x86 0x00 0x00 0x00

 0xb2 0xec 0x00 0x00
 
 # CHECK: etnd %r15
 0xb2 0xec 0x00 0xf0
 
 # CHECK: etnd %r7
 0xb2 0xec 0x00 0x70
 
-# CHECK: ex %r0, 0
+# CHECK: ex 0, 0
 0x44 0x00 0x00 0x00
 
-# CHECK: ex %r0, 4095
+# CHECK: ex 0, 4095
 0x44 0x00 0x0f 0xff
 
-# CHECK: ex %r0, 0(%r1)
+# CHECK: ex 0, 0(%r1)
 0x44 0x00 0x10 0x00
 
-# CHECK: ex %r0, 0(%r15)
+# CHECK: ex 0, 0(%r15)
 0x44 0x00 0xf0 0x00
 
-# CHECK: ex %r0, 4095(%r1,%r15)
+# CHECK: ex 0, 4095(%r1,%r15)
 0x44 0x01 0xff 0xff
 
-# CHECK: ex %r0, 4095(%r15,%r1)
+# CHECK: ex 0, 4095(%r15,%r1)
 0x44 0x0f 0x1f 0xff
 
 # CHECK: ex %r15, 0
 0x44 0xf0 0x00 0x00
 
 # CHECK: fidbr %f0, 0, %f0
 0xb3 0x5f 0x00 0x00