[CSKY] Add more patterns to select FNMUL

[benshi001]

ping ...

[zixuan-wu]

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td

146

(f32 (fmul sFPR32Op:$vrx (fneg sFPR32Op:$vry))) is also possible?

[benshi001]

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td

146

We need not specify it explictly, since fmul is commutable operation. I have added tests for both cases.

[zixuan-wu]

Good. Thanks.

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td

 defm FCMPUO : FT_CMPXY<0b001111, "fcmpuo">;
 defm FCMPZHS : FT_CMPZX<0b001000, "fcmpzhs">;
 defm FCMPZLS : FT_CMPZX<0b001001, "fcmpzls">;
 defm FCMPZNE : FT_CMPZX<0b001010, "fcmpzne">;
 defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;
 
 defm FRECIP   : FT_MOV<0b011001, "frecip">;
 
+// multiplication
+let Predicates = [HasFPUv2_SF] in {
+  def : Pat<(f32 (fmul (fneg sFPR32Op:$vrx), sFPR32Op:$vry)),
+            (FNMUL_S sFPR32Op:$vrx, sFPR32Op:$vry)>;
+}
+let Predicates = [HasFPUv2_DF] in {
+  def : Pat<(f64 (fmul (fneg sFPR64Op:$vrx), sFPR64Op:$vry)),
+            (FNMUL_D sFPR64Op:$vrx, sFPR64Op:$vry)>;
+}
+
 //fmov, fmtvr, fmfvr
 defm FMOV : FT_MOV<0b000100, "fmov">;
 def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),
                      "fmfvrl\t$rz, $vrx", [(set GPR:$rz, (bitconvert sFPR32Op:$vrx))]>;
 def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32Op:$vrz), (ins GPR:$rx),
                      "fmtvrl\t$vrz, $rx", [(set sFPR32Op:$vrz, (bitconvert GPR:$rx))]>;
 
 let Predicates = [HasFPUv2_DF] in {

llvm/lib/Target/CSKY/CSKYInstrInfoF2.td

defm f2FNMULA : F2_XYZZ_T<0b010111, "fnmula",
   TriOpFrag<(fneg (fadd (fmul node:$LHS, node:$MHS), node:$RHS))>>;
 
 defm f2FNMULS : F2_XYZZ_T<0b010101, "fnmuls",
   TriOpFrag<(fneg (fsub node:$RHS, (fmul node:$LHS, node:$MHS)))>>;
 
 defm f2FNMUL : F2_XYZ_T<0b010001, "fnmul",
   BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
 
+// multiplication
+let Predicates = [HasFPUv3_SF] in {
+  def : Pat<(f32 (fmul (fneg FPR32Op:$vrx), FPR32Op:$vry)),
+            (f2FNMUL_S FPR32Op:$vrx, FPR32Op:$vry)>;
+}
+let Predicates = [HasFPUv3_DF] in {
+  def : Pat<(f64 (fmul (fneg FPR64Op:$vrx), FPR64Op:$vry)),
+            (f2FNMUL_D FPR64Op:$vrx, FPR64Op:$vry)>;
+}
+
 // fcvt
 def f2FFTOS32_S  : F2_XZ_P<0b01000, 0b011011, "fftoi.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FFTOU32_S  : F2_XZ_P<0b01000, 0b011010, "fftoi.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FS32TOF_S  : F2_XZ_P<0b01001, 0b011011, "fitof.s32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FU32TOF_S  : F2_XZ_P<0b01001, 0b011010, "fitof.u32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FFTOXU32_S  : F2_XZ_P<0b01000, 0b001010, "fftox.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FFTOXS32_S  : F2_XZ_P<0b01000, 0b001011, "fftox.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FXTOFU32_S  : F2_XZ_P<0b01001, 0b001010, "fxtof.u32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;

llvm/test/CodeGen/CSKY/fpu/base-d.ll

 ; CHECK-DF-LABEL: FADD_DOUBLE_I:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI1_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    faddd vr0, vr0, vr1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
+; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI1_0:
 ; CHECK-DF-NEXT:    .quad 0xbff0000000000000 # double -1
 ;
 ; CHECK-DF2-LABEL: FADD_DOUBLE_I:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI1_0]
 ; CHECK-DF2-NEXT:    fadd.64 vr0, vr0, vr1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
 ; CHECK-DF2-NEXT:  .LCPI1_0:
 ; CHECK-DF2-NEXT:    .quad 0xbff0000000000000 # double -1
 entry:
   %fadd = fadd  double %x, -1.0
   ret double %fadd
 }
 
 define double @FSUB_DOUBLE(double %x, double %y) {

 ; CHECK-DF-LABEL: FSUB_DOUBLE_I:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    grs32 a0, .LCPI3_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    faddd vr0, vr0, vr1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
+; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI3_0:
 ; CHECK-DF-NEXT:    .quad 0x3ff0000000000000 # double 1
 ;
 ; CHECK-DF2-LABEL: FSUB_DOUBLE_I:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI3_0]
 ; CHECK-DF2-NEXT:    fadd.64 vr0, vr0, vr1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
 ; CHECK-DF2-NEXT:  .LCPI3_0:
 ; CHECK-DF2-NEXT:    .quad 0x3ff0000000000000 # double 1
 
 entry:
   %fsub = fsub  double %x, -1.0
   ret double %fsub
 }
 
 define double @FMUL_DOUBLE(double %x, double %y) {
 ;
 ; CHECK-DF-LABEL: FMUL_DOUBLE:
 ; CHECK-DF:       # %bb.0: # %entry
 ; CHECK-DF-NEXT:    fmuld vr0, vr1, vr0
 ; CHECK-DF-NEXT:    rts16
 ;
 ; CHECK-DF2-LABEL: FMUL_DOUBLE:
 ; CHECK-DF2:       # %bb.0: # %entry
 ; CHECK-DF2-NEXT:    fmul.64 vr0, vr1, vr0
 ; CHECK-DF2-NEXT:    rts16
 entry:
   %fmul = fmul  double %y, %x
   ret double %fmul
 }
 
+define double @FNMUL_DOUBLE_a(double %x, double %y) {
+;
+; CHECK-DF-LABEL: FNMUL_DOUBLE_a:
+; CHECK-DF:       # %bb.0: # %entry
+; CHECK-DF-NEXT:    fnmuld vr0, vr1, vr0
+; CHECK-DF-NEXT:    rts16
+;
+; CHECK-DF2-LABEL: FNMUL_DOUBLE_a:
+; CHECK-DF2:       # %bb.0: # %entry
+; CHECK-DF2-NEXT:    fnmul.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT:    rts16
+entry:
+  %z = fneg double %y
+  %fnmul = fmul double %z, %x
+  ret double %fnmul
+}
+
+define double @FNMUL_DOUBLE_b(double %x, double %y) {
+; CHECK-DF-LABEL: FNMUL_DOUBLE_b:
+; CHECK-DF:       # %bb.0: # %entry
+; CHECK-DF-NEXT:    fnmuld vr0, vr0, vr1
+; CHECK-DF-NEXT:    rts16
+;
+; CHECK-DF2-LABEL: FNMUL_DOUBLE_b:
+; CHECK-DF2:       # %bb.0: # %entry
+; CHECK-DF2-NEXT:    fnmul.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT:    rts16
+entry:
+  %z = fneg double %x
+  %fnmul = fmul double %y, %z
+  ret double %fnmul
+}
+
 define double @FMUL_DOUBLE_I(double %x) {
 ;
 ; CHECK-DF-LABEL: FMUL_DOUBLE_I:
 ; CHECK-DF:       # %bb.0: # %entry
-; CHECK-DF-NEXT:    grs32 a0, .LCPI5_0
+; CHECK-DF-NEXT:    grs32 a0, .LCPI7_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fmuld vr0, vr0, vr1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
-; CHECK-DF-NEXT:  .LCPI5_0:
+; CHECK-DF-NEXT:    .p2align 2, 0x0
+; CHECK-DF-NEXT:  .LCPI7_0:
 ; CHECK-DF-NEXT:    .quad 0xc01c000000000000 # double -7
 ;
 ; CHECK-DF2-LABEL: FMUL_DOUBLE_I:
 ; CHECK-DF2:       # %bb.0: # %entry
-; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI5_0]
+; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI7_0]
 ; CHECK-DF2-NEXT:    fmul.64 vr0, vr0, vr1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
-; CHECK-DF2-NEXT:  .LCPI5_0:
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
+; CHECK-DF2-NEXT:  .LCPI7_0:
 ; CHECK-DF2-NEXT:    .quad 0xc01c000000000000 # double -7
 entry:
   %fmul = fmul  double %x, -7.0
   ret double %fmul
 }
 
 define double @FDIV_DOUBLE(double %x, double %y) {
 ;
entry:
   %fdiv = fdiv  double %y, %x
   ret double %fdiv
 }
 
 define double @FDIV_DOUBLE_I(double %x) {
 ;
 ; CHECK-DF-LABEL: FDIV_DOUBLE_I:
 ; CHECK-DF:       # %bb.0: # %entry
-; CHECK-DF-NEXT:    grs32 a0, .LCPI7_0
+; CHECK-DF-NEXT:    grs32 a0, .LCPI9_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fdivd vr0, vr0, vr1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
-; CHECK-DF-NEXT:  .LCPI7_0:
+; CHECK-DF-NEXT:    .p2align 2, 0x0
+; CHECK-DF-NEXT:  .LCPI9_0:
 ; CHECK-DF-NEXT:    .quad 0xc01c000000000000 # double -7
 ;
 ; CHECK-DF2-LABEL: FDIV_DOUBLE_I:
 ; CHECK-DF2:       # %bb.0: # %entry
-; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI7_0]
+; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI9_0]
 ; CHECK-DF2-NEXT:    fdiv.64 vr0, vr0, vr1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
-; CHECK-DF2-NEXT:  .LCPI7_0:
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
+; CHECK-DF2-NEXT:  .LCPI9_0:
 ; CHECK-DF2-NEXT:    .quad 0xc01c000000000000 # double -7
 entry:
   %fdiv = fdiv  double %x, -7.0
   ret double %fdiv
 }
 
 define double @FNEG_DOUBLE(double %x) {
 ;

llvm/test/CodeGen/CSKY/fpu/base-f.ll

 ; CHECK-SF2-NEXT:    fmul.32 vr0, vr1, vr0
 ; CHECK-SF2-NEXT:    rts16
 
 entry:
   %fmul = fmul  float %y, %x
   ret float %fmul
 }
 
+define float @fnmulRR_a(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fnmulRR_a:
+; CHECK-SF:       # %bb.0: # %entry
+; CHECK-SF-NEXT:    fnmuls vr0, vr1, vr0
+; CHECK-SF-NEXT:    rts16
+;
+; CHECK-SF2-LABEL: fnmulRR_a:
+; CHECK-SF2:       # %bb.0: # %entry
+; CHECK-SF2-NEXT:    fnmul.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT:    rts16
+
+entry:
+  %z = fneg float %y
+  %fnmul = fmul float %z, %x
+  ret float %fnmul
+}
+
+define float @fnmulRR_b(float %x, float %y) {
+; CHECK-SF-LABEL: fnmulRR_b:
+; CHECK-SF:       # %bb.0: # %entry
+; CHECK-SF-NEXT:    fnmuls vr0, vr0, vr1
+; CHECK-SF-NEXT:    rts16
+;
+; CHECK-SF2-LABEL: fnmulRR_b:
+; CHECK-SF2:       # %bb.0: # %entry
+; CHECK-SF2-NEXT:    fnmul.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT:    rts16
+entry:
+  %z = fneg float %x
+  %fnmul = fmul float %y, %z
+  ret float %fnmul
+}
+
 define float @fmulRI(float %x) {
 ;
 ; CHECK-SF-LABEL: fmulRI:
 ; CHECK-SF:       # %bb.0: # %entry
 ; CHECK-SF-NEXT:    movih32 a0, 16672
 ; CHECK-SF-NEXT:    fmtvrl vr1, a0
 ; CHECK-SF-NEXT:    fmuls vr0, vr0, vr1
 ; CHECK-SF-NEXT:    rts16