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Differential D155012

Fix types of arm64 MSVC __readx18/__writex18 intrinsics
ClosedPublic

Authored by ahatanak on Jul 11 2023, 1:16 PM.

Details

Reviewers
ravikandhadai
Bigcheese
steplong
Commits
rG4ae87b3f8adc: Fix types of arm64 MSVC __readx18/__writex18 intrinsics
Summary

Using L for type long results in clang passing 64-bit integers to these intrinsics on LP64 operating systems. This isn't correct as the intrinsics accept 32-bit integers.

Use N instead of L so that 32-bit integers are passed to the intrinsics on LP64 operating systems too. This is the same fix as the following two commits:

33703fb9f908113f93bd9af83a79eb56f5131735
afa47c91ce5085d446ebb5ac1312dc98b6a68a6c

Diff Detail

Event Timeline

ahatanak created this revision.Jul 11 2023, 1:16 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2023, 1:16 PM
Herald added a subscriber: kristof.beyls. · View Herald Transcript
ahatanak requested review of this revision.Jul 11 2023, 1:16 PM
Herald added a subscriber: wangpc. · View Herald TranscriptJul 11 2023, 1:16 PM
Harbormaster completed remote builds in B244589: Diff 539258.Jul 11 2023, 7:04 PM
ravikandhadai accepted this revision.Jul 18 2023, 4:25 PM

Thanks Akira. LGTM!

This revision is now accepted and ready to land.Jul 18 2023, 4:25 PM
This revision was landed with ongoing or failed builds.Jul 18 2023, 6:16 PM
Closed by commit rG4ae87b3f8adc: Fix types of arm64 MSVC __readx18/__writex18 intrinsics (authored by ahatanak). · Explain Why
This revision was automatically updated to reflect the committed changes.
ahatanak added a commit: rG4ae87b3f8adc: Fix types of arm64 MSVC __readx18/__writex18 intrinsics.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
19 lines
test/
CodeGen/
227 lines

Diff 541802

clang/include/clang/Basic/BuiltinsAArch64.def

Show First 20 Lines • Show All 253 Lines • ▼ Show 20 Lines
TARGET_HEADER_BUILTIN(_WriteStatusReg, "viLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_WriteStatusReg, "viLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_AddressOfReturnAddress, "v*", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_AddressOfReturnAddress, "v*", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__mulh, "SLLiSLLiSLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__mulh, "SLLiSLLiSLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__umulh, "ULLiULLiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__umulh, "ULLiULLiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__break, "vi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__break, "vi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__writex18byte, "vULiUc", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__writex18word, "vULiUs", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__writex18byte, "vUNiUc", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__writex18dword, "vULiULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__writex18word, "vUNiUs", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__writex18qword, "vULiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__writex18dword, "vUNiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__writex18qword, "vUNiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18byte, "UcULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18word, "UsULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__readx18byte, "UcUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18dword, "ULiULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__readx18word, "UsUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18qword, "ULLiULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(__readx18dword, "UNiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(__readx18qword, "ULLiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
#undef BUILTIN #undef BUILTIN
#undef LANGBUILTIN #undef LANGBUILTIN
#undef TARGET_BUILTIN #undef TARGET_BUILTIN
#undef TARGET_HEADER_BUILTIN #undef TARGET_HEADER_BUILTIN

clang/test/CodeGen/arm64-microsoft-intrinsics.c

// RUN: %clang_cc1 -triple arm64-windows -Wno-implicit-function-declaration -fms-compatibility -emit-llvm -o - %s \ // RUN: %clang_cc1 -triple arm64-windows -Wno-implicit-function-declaration -fms-compatibility -emit-llvm -o - %s \
// RUN: | FileCheck %s -check-prefix CHECK-MSVC // RUN: | FileCheck %s --check-prefix=CHECK-MSVC --check-prefix=CHECK-MSCOMPAT
// RUN: not %clang_cc1 -triple arm64-linux -Werror -S -o /dev/null %s 2>&1 \ // RUN: not %clang_cc1 -triple arm64-linux -Werror -S -o /dev/null %s 2>&1 \
// RUN: | FileCheck %s -check-prefix CHECK-LINUX // RUN: | FileCheck %s -check-prefix CHECK-LINUX
// RUN: %clang_cc1 -triple arm64-darwin -Wno-implicit-function-declaration -fms-compatibility -emit-llvm -o - %s \
// RUN: | FileCheck %s -check-prefix CHECK-MSCOMPAT
long test_InterlockedAdd(long volatile *Addend, long Value) { long test_InterlockedAdd(long volatile *Addend, long Value) {
return _InterlockedAdd(Addend, Value); return _InterlockedAdd(Addend, Value);
} }
long test_InterlockedAdd_constant(long volatile *Addend) { long test_InterlockedAdd_constant(long volatile *Addend) {
return _InterlockedAdd(Addend, -1); return _InterlockedAdd(Addend, -1);
} }
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
unsigned __int64 check__getReg(void) { unsigned __int64 check__getReg(void) {
unsigned volatile __int64 reg; unsigned volatile __int64 reg;
reg = __getReg(18); reg = __getReg(18);
reg = __getReg(31); reg = __getReg(31);
return reg; return reg;
} }
// CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]]) // CHECK-MSCOMPAT: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
// CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]]) // CHECK-MSCOMPAT: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
void check__writex18byte(unsigned long offset, unsigned char data) { #ifdef __LP64__
#define LONG __int32
#else
#define LONG long
#endif
#ifdef __LP64__
void check__writex18byte(unsigned char data, unsigned LONG offset) {
#else
void check__writex18byte(unsigned LONG offset, unsigned char data) {
#endif
__writex18byte(offset, data); __writex18byte(offset, data);
} }
// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i8, align 1 // CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i8, align 1
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i8 %data, ptr %[[DATA_ADDR]], align 1 // CHECK-MSCOMPAT: store i8 %data, ptr %[[DATA_ADDR]], align 1
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[DATA:.*]] = load i8, ptr %[[DATA_ADDR]], align 1 // CHECK-MSCOMPAT: %[[DATA:.*]] = load i8, ptr %[[DATA_ADDR]], align 1
// CHECK-MSVC: store i8 %[[DATA]], ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: store i8 %[[DATA]], ptr %[[PTR]], align 1
void check__writex18word(unsigned long offset, unsigned short data) { #ifdef __LP64__
void check__writex18word(unsigned short data, unsigned LONG offset) {
#else
void check__writex18word(unsigned LONG offset, unsigned short data) {
#endif
__writex18word(offset, data); __writex18word(offset, data);
} }
// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i16, align 2 // CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i16, align 2
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i16 %data, ptr %[[DATA_ADDR]], align 2 // CHECK-MSCOMPAT: store i16 %data, ptr %[[DATA_ADDR]], align 2
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[DATA:.*]] = load i16, ptr %[[DATA_ADDR]], align 2 // CHECK-MSCOMPAT: %[[DATA:.*]] = load i16, ptr %[[DATA_ADDR]], align 2
// CHECK-MSVC: store i16 %[[DATA]], ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: store i16 %[[DATA]], ptr %[[PTR]], align 1
void check__writex18dword(unsigned long offset, unsigned long data) { #ifdef __LP64__
void check__writex18dword(unsigned LONG data, unsigned LONG offset) {
#else
void check__writex18dword(unsigned LONG offset, unsigned LONG data) {
#endif
__writex18dword(offset, data); __writex18dword(offset, data);
} }
// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %data, ptr %[[DATA_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %data, ptr %[[DATA_ADDR]], align 4
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[DATA:.*]] = load i32, ptr %[[DATA_ADDR]], align 4 // CHECK-MSCOMPAT: %[[DATA:.*]] = load i32, ptr %[[DATA_ADDR]], align 4
// CHECK-MSVC: store i32 %[[DATA]], ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: store i32 %[[DATA]], ptr %[[PTR]], align 1
void check__writex18qword(unsigned long offset, unsigned __int64 data) { #ifdef __LP64__
void check__writex18qword(unsigned __int64 data, unsigned LONG offset) {
#else
void check__writex18qword(unsigned LONG offset, unsigned __int64 data) {
#endif
__writex18qword(offset, data); __writex18qword(offset, data);
} }
// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i64, align 8 // CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i64, align 8
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i64 %data, ptr %[[DATA_ADDR]], align 8 // CHECK-MSCOMPAT: store i64 %data, ptr %[[DATA_ADDR]], align 8
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[DATA:.*]] = load i64, ptr %[[DATA_ADDR]], align 8 // CHECK-MSCOMPAT: %[[DATA:.*]] = load i64, ptr %[[DATA_ADDR]], align 8
// CHECK-MSVC: store i64 %[[DATA]], ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: store i64 %[[DATA]], ptr %[[PTR]], align 1
unsigned char check__readx18byte(unsigned long offset) { unsigned char check__readx18byte(unsigned LONG offset) {
return __readx18byte(offset); return __readx18byte(offset);
} }
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[RETVAL:.*]] = load i8, ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i8, ptr %[[PTR]], align 1
// CHECK-MSVC: ret i8 %[[RETVAL]] // CHECK-MSCOMPAT: ret i8 %[[RETVAL]]
unsigned short check__readx18word(unsigned long offset) { unsigned short check__readx18word(unsigned LONG offset) {
return __readx18word(offset); return __readx18word(offset);
} }
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[RETVAL:.*]] = load i16, ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i16, ptr %[[PTR]], align 1
// CHECK-MSVC: ret i16 %[[RETVAL]] // CHECK-MSCOMPAT: ret i16 %[[RETVAL]]
unsigned long check__readx18dword(unsigned long offset) { unsigned LONG check__readx18dword(unsigned LONG offset) {
return __readx18dword(offset); return __readx18dword(offset);
} }
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[RETVAL:.*]] = load i32, ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i32, ptr %[[PTR]], align 1
// CHECK-MSVC: ret i32 %[[RETVAL]] // CHECK-MSCOMPAT: ret i32 %[[RETVAL]]
unsigned __int64 check__readx18qword(unsigned long offset) { unsigned __int64 check__readx18qword(unsigned LONG offset) {
return __readx18qword(offset); return __readx18qword(offset);
} }
// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4 // CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]]) // CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr // CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4 // CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64 // CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]] // CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
// CHECK-MSVC: %[[RETVAL:.*]] = load i64, ptr %[[PTR]], align 1 // CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i64, ptr %[[PTR]], align 1
// CHECK-MSVC: ret i64 %[[RETVAL]] // CHECK-MSCOMPAT: ret i64 %[[RETVAL]]
// CHECK-MSVC: ![[MD2]] = !{!"x18"} // CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSVC: ![[MD3]] = !{!"sp"} // CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}