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Differential D154789

[InstCombine] Add tests for bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise(A<0, icmp)) fold (NFC)
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Authored by XChy on Jul 9 2023, 7:13 AM.

Details

Reviewers
nikic
goldstein.w.n
spatel
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Commits
rG724e2b1225cd: [InstCombine] Add tests for bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise…
Summary

Tests for an upcoming bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise(A<0, icmp)) fold.
Related issue:
a < b | a >b
a < b & a >= b - 1

Diff Detail

Unit TestsFailed

TimeTest
3,720 msx64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases/Linux::auto_memory_profile_test.cpp

Event Timeline

XChy created this revision.Jul 9 2023, 7:13 AM
Herald added a subscriber: StephenFan. · View Herald TranscriptJul 9 2023, 7:13 AM
XChy requested review of this revision.Jul 9 2023, 7:13 AM
Herald added a subscriber: llvm-commits. · View Herald TranscriptJul 9 2023, 7:13 AM
Harbormaster completed remote builds in B243982: Diff 538429.Jul 9 2023, 7:54 AM
XChy added a child revision: D154791: [InstCombine] Transform bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise(A < 0, icmp)) fold..Jul 9 2023, 5:05 PM
XChy retitled this revision from [InstCombine] Add tests for bitwise (A << X, zext(icmp)) -> zext (bitwise(A<0, icmp)) fold (NFC) to [InstCombine] Add tests for bitwise (A << C - 1, zext(icmp)) -> zext (bitwise(A<0, icmp)) fold (NFC).
XChy edited the summary of this revision. (Show Details)
XChy retitled this revision from [InstCombine] Add tests for bitwise (A << C - 1, zext(icmp)) -> zext (bitwise(A<0, icmp)) fold (NFC) to [InstCombine] Add tests for bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise(A<0, icmp)) fold (NFC).Jul 9 2023, 5:28 PM
XChy edited the summary of this revision. (Show Details)
XChy updated this revision to Diff 538615.Jul 10 2023, 6:41 AM
Harbormaster completed remote builds in B244121: Diff 538615.Jul 10 2023, 7:38 AM
XChy updated this revision to Diff 539022.Jul 11 2023, 4:44 AM
XChy set the repository for this revision to rG LLVM Github Monorepo.
Harbormaster completed remote builds in B244419: Diff 539022.Jul 11 2023, 6:46 AM
XChy updated this revision to Diff 539398.Jul 11 2023, 11:25 PM
Harbormaster completed remote builds in B244678: Diff 539398.Jul 12 2023, 1:44 AM
XChy updated this revision to Diff 540409.Jul 14 2023, 7:17 AM
XChy set the repository for this revision to rG LLVM Github Monorepo.
Harbormaster completed remote builds in B245385: Diff 540409.Jul 14 2023, 8:25 AM
nikic accepted this revision.Jul 24 2023, 4:01 AM
This revision is now accepted and ready to land.Jul 24 2023, 4:01 AM
This revision was landed with ongoing or failed builds.Jul 24 2023, 4:04 AM
Closed by commit rG724e2b1225cd: [InstCombine] Add tests for bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise… (authored by XChy, committed by nikic). · Explain Why
This revision was automatically updated to reflect the committed changes.
nikic added a commit: rG724e2b1225cd: [InstCombine] Add tests for bitwise (A >> C - 1, zext(icmp)) -> zext (bitwise….

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
293 lines

Diff 538615

llvm/test/Transforms/InstCombine/and-or-icmps.ll

Show First 20 Lines • Show All 2,676 Lines • ▼ Show 20 Lines
; ;
%B = icmp sgt <2 x i64> %x, <i64 1, i64 1> %B = icmp sgt <2 x i64> %x, <i64 1, i64 1>
%C = lshr <2 x i64> %x, <i64 63, i64 63> %C = lshr <2 x i64> %x, <i64 63, i64 63>
%D = zext <2 x i1> %B to <2 x i64> %D = zext <2 x i1> %B to <2 x i64>
%E = or <2 x i64> %C, %D %E = or <2 x i64> %C, %D
ret <2 x i64> %E ret <2 x i64> %E
} }
define i32 @icmp_slt_0_and_icmp_sge_neg1_i32(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg1_i32(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sgt i32 %x, -1
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = and i32 %C, %B
ret i32 %D
}
define i32 @icmp_slt_0_or_icmp_sge_neg1_i32(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_or_icmp_sge_neg1_i32(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -2
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = or i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sge i32 %x, -1
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = or i32 %C, %B
ret i32 %D
}
define i32 @icmp_slt_0_or_icmp_sge_100_i32(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_or_icmp_sge_100_i32(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], 99
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = or i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sge i32 %x, 100
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = or i32 %C, %B
ret i32 %D
}
define i64 @icmp_slt_0_and_icmp_sge_neg1_i64(i64 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg1_i64(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i64
; CHECK-NEXT: [[C:%.*]] = lshr i64 [[X]], 63
; CHECK-NEXT: [[D:%.*]] = and i64 [[C]], [[B]]
; CHECK-NEXT: ret i64 [[D]]
;
%A = icmp sge i64 %x, -1
%B = zext i1 %A to i64
%C = lshr i64 %x, 63
%D = and i64 %C, %B
ret i64 %D
}
define i64 @icmp_slt_0_and_icmp_sge_neg2_i64(i64 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg2_i64(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i64 [[X:%.*]], -3
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i64
; CHECK-NEXT: [[C:%.*]] = lshr i64 [[X]], 63
; CHECK-NEXT: [[D:%.*]] = and i64 [[C]], [[B]]
; CHECK-NEXT: ret i64 [[D]]
;
%A = icmp sge i64 %x, -2
%B = zext i1 %A to i64
%C = lshr i64 %x, 63
%D = and i64 %C, %B
ret i64 %D
}
define i64 @ashr_and_icmp_sge_neg1_i64(i64 %x) {
; CHECK-LABEL: @ashr_and_icmp_sge_neg1_i64(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i64
; CHECK-NEXT: [[C1:%.*]] = lshr i64 [[X]], 63
; CHECK-NEXT: [[D:%.*]] = and i64 [[C1]], [[B]]
; CHECK-NEXT: ret i64 [[D]]
;
%A = icmp sge i64 %x, -1
%B = zext i1 %A to i64
%C = ashr i64 %x, 63
%D = and i64 %C, %B
ret i64 %D
}
define i64 @icmp_slt_0_and_icmp_sgt_neg1_i64(i64 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sgt_neg1_i64(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i64 [[X:%.*]], -1
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i64
; CHECK-NEXT: [[C:%.*]] = lshr i64 [[X]], 63
; CHECK-NEXT: [[D:%.*]] = and i64 [[C]], [[B]]
; CHECK-NEXT: ret i64 [[D]]
;
%A = icmp sgt i64 %x, -1
%B = zext i1 %A to i64
%C = lshr i64 %x, 63
%D = and i64 %C, %B
ret i64 %D
}
define i64 @icmp_slt_0_and_icmp_sge_neg1_i64_fail(i64 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg1_i64_fail(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i64 [[X:%.*]], -2
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i64
; CHECK-NEXT: [[C:%.*]] = lshr i64 [[X]], 62
; CHECK-NEXT: [[D:%.*]] = and i64 [[C]], [[B]]
; CHECK-NEXT: ret i64 [[D]]
;
%A = icmp sge i64 %x, -1
%B = zext i1 %A to i64
%C = lshr i64 %x, 62
%D = and i64 %C, %B
ret i64 %D
}
define <2 x i32> @icmp_slt_0_and_icmp_sge_neg1_i32x2(<2 x i32> %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg1_i32x2(
; CHECK-NEXT: [[A:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -2, i32 -2>
; CHECK-NEXT: [[B:%.*]] = zext <2 x i1> [[A]] to <2 x i32>
; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> [[X]], <i32 31, i32 31>
; CHECK-NEXT: [[D:%.*]] = and <2 x i32> [[C]], [[B]]
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%A = icmp sge <2 x i32> %x, <i32 -1, i32 -1>
%B = zext <2 x i1> %A to <2 x i32>
%C = lshr <2 x i32> %x, <i32 31, i32 31>
%D = and <2 x i32> %C, %B
ret <2 x i32> %D
}
define <2 x i32> @icmp_slt_0_and_icmp_sge_neg2_i32x2(<2 x i32> %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg2_i32x2(
; CHECK-NEXT: [[A:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -3, i32 -3>
; CHECK-NEXT: [[B:%.*]] = zext <2 x i1> [[A]] to <2 x i32>
; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> [[X]], <i32 31, i32 31>
; CHECK-NEXT: [[D:%.*]] = and <2 x i32> [[C]], [[B]]
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%A = icmp sge <2 x i32> %x, <i32 -2, i32 -2>
%B = zext <2 x i1> %A to <2 x i32>
%C = lshr <2 x i32> %x, <i32 31, i32 31>
%D = and <2 x i32> %C, %B
ret <2 x i32> %D
}
define i32 @icmp_slt_0_and_icmp_sge_neg1_i32_multiuse0(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg1_i32_multiuse0(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -3
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: call void @use(i1 [[A]])
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sge i32 %x, -2
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = and i32 %C, %B
call void @use(i1 %A)
ret i32 %D
}
define i32 @icmp_slt_0_and_icmp_sge_neg2_i32_multiuse1(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg2_i32_multiuse1(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -3
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: call void @use32(i32 [[B]])
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sge i32 %x, -2
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = and i32 %C, %B
call void @use32(i32 %B)
ret i32 %D
}
define i32 @icmp_slt_0_and_icmp_sge_neg2_i32_multiuse2(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_sge_neg2_i32_multiuse2(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -3
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: call void @use32(i32 [[C]])
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sge i32 %x, -2
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = and i32 %C, %B
call void @use32(i32 %C)
ret i32 %D
}
define i32 @icmp_slt_0_or_icmp_eq_100_i32_fail(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_or_icmp_eq_100_i32_fail(
; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 100
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = or i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp eq i32 %x, 100
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = or i32 %C, %B
ret i32 %D
}
define i32 @icmp_slt_0_and_icmp_ne_neg2_i32_fail(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_and_icmp_ne_neg2_i32_fail(
; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], -2
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp ne i32 %x, -2
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = and i32 %C, %B
ret i32 %D
}
define i32 @icmp_x_slt_0_and_icmp_y_ne_neg2_i32_fail(i32 %x, i32 %y) {
; CHECK-LABEL: @icmp_x_slt_0_and_icmp_y_ne_neg2_i32_fail(
; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], -2
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[Y:%.*]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp ne i32 %x, -2
%B = zext i1 %A to i32
%C = lshr i32 %y, 31
%D = and i32 %C, %B
ret i32 %D
}
define i32 @icmp_x_slt_0_and_icmp_y_sgt_neg1_i32_fail(i32 %x, i32 %y) {
; CHECK-LABEL: @icmp_x_slt_0_and_icmp_y_sgt_neg1_i32_fail(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[Y:%.*]], 31
; CHECK-NEXT: [[D:%.*]] = and i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sgt i32 %x, -1
%B = zext i1 %A to i32
%C = lshr i32 %y, 31
%D = and i32 %C, %B
ret i32 %D
}
define i32 @icmp_slt_0_xor_icmp_sge_neg2_i32_fail(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_xor_icmp_sge_neg2_i32_fail(
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -3
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = xor i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%A = icmp sge i32 %x, -2
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = xor i32 %C, %B
ret i32 %D
}
define i32 @icmp_slt_0_or_icmp_add_1_sge_100_i32_fail(i32 %x) {
; CHECK-LABEL: @icmp_slt_0_or_icmp_add_1_sge_100_i32_fail(
; CHECK-NEXT: [[X1:%.*]] = add i32 [[X:%.*]], 1
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X1]], 99
; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[X]], 31
; CHECK-NEXT: [[D:%.*]] = or i32 [[C]], [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
%X1 = add i32 %x, 1
%A = icmp sge i32 %X1, 100
%B = zext i1 %A to i32
%C = lshr i32 %x, 31
%D = or i32 %C, %B
ret i32 %D
}