[LoongArch] Implement isLegalAddImmediate

[hev]

Summary

This brings a trivial improvement in the and-add-lsr.ll test case.

Signed-off-by: WANG Rui <[e-mail]>

Depends on D154760

[hev]

Rebase and update test case.

[hev]

Rebase.

[hev]

Rebase.

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
                               SDValue C) const override;
 
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
+  bool isLegalAddImmediate(int64_t Imm) const override;
+
   bool hasAndNotCompare(SDValue Y) const override;
 
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
   bool allowsMisalignedMemoryAccesses(
       EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
       unsigned *Fast = nullptr) const override;

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

case 2:
     break;
   default:
     return false;
   }
 
   return true;
 }
 
+bool LoongArchTargetLowering::isLegalAddImmediate(int64_t Imm) const {
+  return isInt<12>(Imm);
+}
+
 bool LoongArchTargetLowering::hasAndNotCompare(SDValue Y) const {
   // TODO: Support vectors.
   if (Y.getValueType().isVector())
     return false;
 
   return !isa<ConstantSDNode>(Y);
 }

llvm/test/CodeGen/LoongArch/lsr-legaladdimm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+define i32 @lsr_addimm(i32 %x, i32 %y) {
+; CHECK-LABEL: lsr_addimm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi.d $a0, $a0, -1
+; CHECK-NEXT:    bstrpick.d $a1, $a1, 31, 20
+; CHECK-NEXT:    and $a0, $a1, $a0
+; CHECK-NEXT:    ret
+  %1 = add i32 %x, 4095
+  %2 = lshr i32 %y, 20
+  %r = and i32 %2, %1
+  ret i32 %r
+}