[CSKY] Optimize IR pattern icmp-select with INCT32/INCF32

[zixuan-wu]

No more further comments. I just go through inct-incf.ll without too much detail. I hope all added Pats are all covered in inct-incf.ll

[benshi001]

In D153436#4462763, @zixuan-wu wrote:

No more further comments. I just go through inct-incf.ll without too much detail. I hope all added Pats are all covered in inct-incf.ll

Sure. I will have a double check about your concern.

[benshi001]

In D153436#4462890, @benshi001 wrote:

In D153436#4462763, @zixuan-wu wrote:

No more further comments. I just go through inct-incf.ll without too much detail. I hope all added Pats are all covered in inct-incf.ll

Sure. I will have a double check about your concern.

I have checked and I think each newly added Pat is covered.

(select (var0 == var1))
(select (var0 != var1))
(select (unsigned var0 >= var1))
(select (signed var0 >= var1))
(select (unsigned var0 > var1))
(select (signed var0 > var1))
(select (unsigned var0 < var1))
(select (signed var0 < var1))
(select (unsigned var0 <= var1))
(select (signed var0 <= var1))
(select (var == immediate))
(select (var != immediate))
(select (unsigned var >= immediate))
(select (signed var >= immediate))
(select (unsigned var > immediate))
(select (signed var > immediate))
(select (unsigned var < immediate))
(select (signed var < immediate))
(select (unsigned var <= immediate))
(select (signed var <= immediate))
(select (non comparison bool condition)) // a function call return bool

[zixuan-wu]

In D153436#4463080, @benshi001 wrote:

In D153436#4462890, @benshi001 wrote:

In D153436#4462763, @zixuan-wu wrote:

No more further comments. I just go through inct-incf.ll without too much detail. I hope all added Pats are all covered in inct-incf.ll

Sure. I will have a double check about your concern.

I have checked and I think each newly added Pat is covered.

(select (var0 == var1))
(select (var0 != var1))
(select (unsigned var0 >= var1))
(select (signed var0 >= var1))
(select (unsigned var0 > var1))
(select (signed var0 > var1))
(select (unsigned var0 < var1))
(select (signed var0 < var1))
(select (unsigned var0 <= var1))
(select (signed var0 <= var1))
(select (var == immediate))
(select (var != immediate))
(select (unsigned var >= immediate))
(select (signed var >= immediate))
(select (unsigned var > immediate))
(select (signed var > immediate))
(select (unsigned var < immediate))
(select (signed var < immediate))
(select (unsigned var <= immediate))
(select (signed var <= immediate))
(select (non comparison bool condition)) // a function call return bool

LGTM

llvm/lib/Target/CSKY/CSKYInstrInfo.td

let Predicates = [iHasE2] in {
   let Predicates = [iHas2E3] in
   def : Pat<(i32 (setge GPR:$rs1, oimm16:$rs2)),
             (MVCV32 (CMPLTI32 GPR:$rs1, oimm16:$rs2))>;
 }
 
 // Select Patterns.
 let Predicates = [iHasE2] in {
 
+def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
+          (INCT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
+          (INCF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
+
+multiclass INCTF32Pat0<PatFrag cond0, PatFrag cond1, Instruction cmp> {
+  def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
+            (INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+  def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
+            (INCF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+  def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
+            (INCF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+  def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
+            (INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+}
+
+defm : INCTF32Pat0<setuge, setult, CMPHSI32>;
+defm : INCTF32Pat0<setlt, setge, CMPLTI32>;
+
+def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5:$imm), GPR:$false),
+          (INCT32 CARRY:$ca, GPR:$false, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select CARRY:$ca, GPR:$true, (add GPR:$rx, uimm5:$imm)),
+          (INCF32 CARRY:$ca, GPR:$true, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5:$imm), GPR:$false),
+          (INCT32 CARRY:$ca, GPR:$false, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select (and CARRY:$ca, 1), GPR:$true, (add GPR:$rx, uimm5:$imm)),
+          (INCF32 CARRY:$ca, GPR:$true, GPR:$rx, uimm5:$imm)>;
+
 def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
           (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
           (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 
 multiclass MOVTF32Pat0<PatFrag cond0, PatFrag cond1, ImmLeaf imm_ty, Instruction inst> {
   def : Pat<(select (i32 (cond0 GPR:$rs1, imm_ty:$rs2)), GPR:$rx, GPR:$false),
             (MOVT32 (inst GPR:$rs1, imm_ty:$rs2), GPR:$rx, GPR:$false)>;
   def : Pat<(select (i32 (cond1 GPR:$rs1, imm_ty:$rs2)), GPR:$rx, GPR:$false),
             (MOVF32 (inst GPR:$rs1, imm_ty:$rs2), GPR:$rx, GPR:$false)>;
 }
 
 defm : MOVTF32Pat0<setne, seteq, uimm16, CMPNEI32>;
 defm : MOVTF32Pat0<setuge, setult, oimm16, CMPHSI32>;
 defm : MOVTF32Pat0<setlt, setge, oimm16, CMPLTI32>;
 
 def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
           (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
           (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 }
 
 
 let Predicates = [iHas2E3] in {
+def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
+          (INCT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
+          (INCF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
+
+multiclass INCTF32Pat1<PatFrag cond0, PatFrag cond1, Instruction cmp, Instruction incdec0,
+                       Instruction incdec1> {
+  def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
+            (incdec0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+  def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
+            (incdec1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+  def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
+            (incdec0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;
+  def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
+            (incdec1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;
+}
+
+defm : INCTF32Pat1<setuge, setule, CMPHS32, INCT32, INCF32>;
+defm : INCTF32Pat1<setult, setugt, CMPHS32, INCF32, INCT32>;
+defm : INCTF32Pat1<setlt, setgt, CMPLT32, INCT32, INCF32>;
+defm : INCTF32Pat1<setge, setle, CMPLT32, INCF32, INCT32>;
 
 def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
           (MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
 def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
           (MOVF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
 
 multiclass MOVTF32Pat1<PatFrag cond0, PatFrag cond1, Instruction cmp_inst,
                        Instruction mov_inst> {

llvm/test/CodeGen/CSKY/inct-incf.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s -mtriple=csky | FileCheck %s
 
 define i32 @select_by_icmp_ugt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ugt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmphs16 a1, a0
-; CHECK-NEXT:    movf32 a3, a2
+; CHECK-NEXT:    incf32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp ugt i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_sgt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_sgt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmplt16 a1, a0
-; CHECK-NEXT:    movt32 a3, a2
+; CHECK-NEXT:    inct32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp sgt i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_uge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_uge:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmphs16 a0, a1
-; CHECK-NEXT:    movt32 a3, a2
+; CHECK-NEXT:    inct32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp uge i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_sge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_sge:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmplt16 a0, a1
-; CHECK-NEXT:    movf32 a3, a2
+; CHECK-NEXT:    incf32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp sge i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ult(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ult:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmphs16 a0, a1
-; CHECK-NEXT:    movf32 a3, a2
+; CHECK-NEXT:    incf32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp ult i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_slt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_slt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmplt16 a0, a1
-; CHECK-NEXT:    movt32 a3, a2
+; CHECK-NEXT:    inct32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp slt i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ule(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ule:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmphs16 a1, a0
-; CHECK-NEXT:    movt32 a3, a2
+; CHECK-NEXT:    inct32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp ule i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_sle(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_sle:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmplt16 a1, a0
-; CHECK-NEXT:    movf32 a3, a2
+; CHECK-NEXT:    incf32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp sle i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ne(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ne:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmpne16 a0, a1
-; CHECK-NEXT:    movt32 a3, a2
+; CHECK-NEXT:    inct32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp ne i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_eq(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_eq:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a2, 10
 ; CHECK-NEXT:    cmpne16 a0, a1
-; CHECK-NEXT:    movf32 a3, a2
+; CHECK-NEXT:    incf32 a3, a2, 10
 ; CHECK-NEXT:    mov16 a0, a3
 ; CHECK-NEXT:    rts16
   %t4 = icmp eq i32 %t0, %t1
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ugt_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ugt_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    movi16 a3, 128
 ; CHECK-NEXT:    cmphs16 a3, a0
-; CHECK-NEXT:    movf32 a2, a1
+; CHECK-NEXT:    incf32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp ugt i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_sgt_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_sgt_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    movi16 a3, 128
 ; CHECK-NEXT:    cmplt16 a3, a0
-; CHECK-NEXT:    movt32 a2, a1
+; CHECK-NEXT:    inct32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp sgt i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_uge_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_uge_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    movi16 a3, 127
 ; CHECK-NEXT:    cmphs16 a3, a0
-; CHECK-NEXT:    movf32 a2, a1
+; CHECK-NEXT:    incf32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp uge i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_sge_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_sge_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    movi16 a3, 127
 ; CHECK-NEXT:    cmplt16 a3, a0
-; CHECK-NEXT:    movt32 a2, a1
+; CHECK-NEXT:    inct32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp sge i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ult_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ult_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    cmphsi32 a0, 128
-; CHECK-NEXT:    movf32 a2, a1
+; CHECK-NEXT:    incf32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp ult i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_slt_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_slt_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    cmplti32 a0, 128
-; CHECK-NEXT:    movt32 a2, a1
+; CHECK-NEXT:    inct32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp slt i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ule_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ule_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    cmphsi32 a0, 129
-; CHECK-NEXT:    movf32 a2, a1
+; CHECK-NEXT:    incf32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp ule i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_sle_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_sle_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    cmplti32 a0, 129
-; CHECK-NEXT:    movt32 a2, a1
+; CHECK-NEXT:    inct32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp sle i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_ne_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_ne_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    cmpnei32 a0, 128
-; CHECK-NEXT:    movt32 a2, a1
+; CHECK-NEXT:    inct32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp ne i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_icmp_eq_imm(i32 %t0, i32 %t2, i32 %t3) {
 ; CHECK-LABEL: select_by_icmp_eq_imm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi16 a1, 10
 ; CHECK-NEXT:    cmpnei32 a0, 128
-; CHECK-NEXT:    movf32 a2, a1
+; CHECK-NEXT:    incf32 a2, a1, 10
 ; CHECK-NEXT:    mov16 a0, a2
 ; CHECK-NEXT:    rts16
   %t4 = icmp eq i32 %t0, 128
   %t5 = add i32 %t2, 10
   %t6 = select i1 %t4, i32 %t5, i32 %t3
   ret i32 %t6
 }
 
 define i32 @select_by_call_t(i32 %t0, i32 %t1, i32 %t2) {
 ; CHECK-LABEL: select_by_call_t:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subi16 sp, sp, 12
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    st16.w l1, (sp, 8) # 4-byte Folded Spill
 ; CHECK-NEXT:    st16.w l0, (sp, 4) # 4-byte Folded Spill
 ; CHECK-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset l1, -4
 ; CHECK-NEXT:    .cfi_offset l0, -8
 ; CHECK-NEXT:    .cfi_offset lr, -12
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    mov16 l0, a2
 ; CHECK-NEXT:    mov16 l1, a1
 ; CHECK-NEXT:    jsri32 [.LCPI20_0]
-; CHECK-NEXT:    addi32 a1, l1, 10
 ; CHECK-NEXT:    btsti16 a0, 0
-; CHECK-NEXT:    movt32 l0, a1
+; CHECK-NEXT:    inct32 l0, l1, 10
 ; CHECK-NEXT:    mov16 a0, l0
 ; CHECK-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; CHECK-NEXT:    ld16.w l0, (sp, 4) # 4-byte Folded Reload
 ; CHECK-NEXT:    ld16.w l1, (sp, 8) # 4-byte Folded Reload
 ; CHECK-NEXT:    addi16 sp, sp, 12
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  # %bb.1:

 ; CHECK-NEXT:    st32.w lr, (sp, 0) # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset l1, -4
 ; CHECK-NEXT:    .cfi_offset l0, -8
 ; CHECK-NEXT:    .cfi_offset lr, -12
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    mov16 l0, a2
 ; CHECK-NEXT:    mov16 l1, a1
 ; CHECK-NEXT:    jsri32 [.LCPI21_0]
-; CHECK-NEXT:    addi32 a1, l1, 10
 ; CHECK-NEXT:    btsti16 a0, 0
-; CHECK-NEXT:    movt32 a1, l0
-; CHECK-NEXT:    mov16 a0, a1
+; CHECK-NEXT:    incf32 l0, l1, 10
+; CHECK-NEXT:    mov16 a0, l0
 ; CHECK-NEXT:    ld32.w lr, (sp, 0) # 4-byte Folded Reload
 ; CHECK-NEXT:    ld16.w l0, (sp, 4) # 4-byte Folded Reload
 ; CHECK-NEXT:    ld16.w l1, (sp, 8) # 4-byte Folded Reload
 ; CHECK-NEXT:    addi16 sp, sp, 12
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    .p2align 2, 0x0