[GlobalIsel][X86] Update legalization of G_PTR_ADD

[tschuett]

Summary

Replace the legacy legalizer versions

Add test coverage for 32-bit targets and non-constant ptr offsets

llvm/lib/Target/X86/X86LegalizerInfo.cpp

X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
 
   getActionDefinitionsBuilder(G_PTRTOINT)
       .legalForCartesianProduct(Is64Bit ? PtrTypes64 : PtrTypes32, {p0})
       .maxScalar(0, sMaxScalar)
       .widenScalarToNextPow2(0, /*Min*/ 8);
 
   getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, sMaxScalar}});
 
+  getActionDefinitionsBuilder(G_PTR_ADD)
+      .legalIf([=](const LegalityQuery &Query) -> bool {
+        return typePairInSet(0, 1, {{p0, s32}})(Query) ||
+               (Is64Bit && typePairInSet(0, 1, {{p0, s64}})(Query));
+      })
+      .widenScalarToNextPow2(1, /*Min*/ 32)
+      .clampScalar(1, s32, sMaxScalar);
+
   // sext, zext, and anyext
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
       .legalIf([=](const LegalityQuery &Query) {
         return typeInSet(0, {s8, s16, s32})(Query) ||
           (Query.Opcode == G_ANYEXT && Query.Types[0] == s128) ||
           (Is64Bit && Query.Types[0] == s64);
       })
     .widenScalarToNextPow2(0, /*Min=*/8)
X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
   getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall();
 
   // fp intrinsics
   getActionDefinitionsBuilder(G_INTRINSIC_ROUNDEVEN)
       .scalarize(0)
       .minScalar(0, LLT::scalar(32))
       .libcall();
 
+  getActionDefinitionsBuilder(G_FREEZE)
+    .legalFor({s8, s16, s32, s64, p0})
+    .widenScalarToNextPow2(0, /*Min=*/8)
+    .clampScalar(0, s8, sMaxScalar);
+
   setLegalizerInfo32bit();
   setLegalizerInfo64bit();
   setLegalizerInfoSSE1();
   setLegalizerInfoSSE2();
   setLegalizerInfoAVX();
   setLegalizerInfoAVX2();
   setLegalizerInfoAVX512();
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
   LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0, widen_1);
   for (unsigned MemOp : {G_LOAD, G_STORE})
     LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
         MemOp, 0, LegacyLegalizerInfo::narrowToSmallerAndWidenToSmallest);
-  LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
-      G_PTR_ADD, 1,
-      LegacyLegalizerInfo::widenToLargerTypesUnsupportedOtherwise);
 
   LegacyInfo.computeTables();
   verify(*STI.getInstrInfo());
 }
 
 bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
                                          MachineInstr &MI) const {
   return true;
for (unsigned MemOp : {G_LOAD, G_STORE}) {
     // And everything's fine in addrspace 0.
     LegacyInfo.setAction({MemOp, 1, p0}, LegacyLegalizeActions::Legal);
   }
 
   // Pointer-handling
   LegacyInfo.setAction({G_FRAME_INDEX, p0}, LegacyLegalizeActions::Legal);
   LegacyInfo.setAction({G_GLOBAL_VALUE, p0}, LegacyLegalizeActions::Legal);
 
-  LegacyInfo.setAction({G_PTR_ADD, p0}, LegacyLegalizeActions::Legal);
-  LegacyInfo.setAction({G_PTR_ADD, 1, s32}, LegacyLegalizeActions::Legal);
-
   // Control-flow
   LegacyInfo.setAction({G_BRCOND, s1}, LegacyLegalizeActions::Legal);
 
   // Merge/Unmerge
   for (const auto &Ty : {s16, s32, s64}) {
     LegacyInfo.setAction({G_MERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
     LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
                          LegacyLegalizeActions::Legal);
void X86LegalizerInfo::setLegalizerInfo64bit() {
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   LegacyInfo.setAction({G_PHI, s64}, LegacyLegalizeActions::Legal);
 
   for (unsigned MemOp : {G_LOAD, G_STORE})
     LegacyInfo.setAction({MemOp, s64}, LegacyLegalizeActions::Legal);
 
-  // Pointer-handling
-  LegacyInfo.setAction({G_PTR_ADD, 1, s64}, LegacyLegalizeActions::Legal);
-
   getActionDefinitionsBuilder(G_SITOFP)
     .legalForCartesianProduct({s32, s64})
       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(1)
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder(G_FPTOSI)

llvm/test/CodeGen/X86/GlobalISel/legalize-freeze.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+
+# test freeze
+
+...
+---
+name:            test_freezep0
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_freezep0
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(p0) = G_FREEZE [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[FREEZE]](p0)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](p0)
+    %0:_(p0) = IMPLICIT_DEF
+    %1:_(p0) = G_FREEZE %0
+    %2:_(p0) = COPY %1(p0)
+    RET 0, implicit %2
+
+...
+---
+name:            test_freeze64
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_freeze64
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[FREEZE]](s64)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](s64)
+    %0:_(s64) = IMPLICIT_DEF
+    %1:_(s64) = G_FREEZE %0
+    %2:_(s64) = COPY %1(s64)
+    RET 0, implicit %2
+
+...
+---
+name:            test_freeze48
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_freeze48
+    ; CHECK: [[DEF:%[0-9]+]]:_(s48) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[DEF]](s48)
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[ANYEXT]]
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[FREEZE]](s64)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s48) = COPY [[TRUNC]](s48)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](s48)
+    %0:_(s48) = IMPLICIT_DEF
+    %1:_(s48) = G_FREEZE %0
+    %2:_(s48) = COPY %1(s48)
+    RET 0, implicit %2
+
+...
+---
+name:            test_freeze32
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_freeze32
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[FREEZE]](s32)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](s32)
+    %0:_(s32) = IMPLICIT_DEF
+    %1:_(s32) = G_FREEZE %0
+    %2:_(s32) = COPY %1(s32)
+    RET 0, implicit %2
+
+...
+---
+name:            test_freeze16
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_freeze16
+    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[FREEZE]](s16)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](s16)
+    %0:_(s16) = IMPLICIT_DEF
+    %1:_(s16) = G_FREEZE %0
+    %2:_(s16) = COPY %1(s16)
+    RET 0, implicit %2
+
+...
+---
+name:            test_freeze8
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: test_freeze8
+    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[FREEZE]](s8)
+    ; CHECK-NEXT: RET 0, implicit [[COPY]](s8)
+    %0:_(s8) = IMPLICIT_DEF
+    %1:_(s8) = G_FREEZE %0
+    %2:_(s8) = COPY %1(s8)
+    RET 0, implicit %2
+
+...

llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
 
 --- |
-  define void @test_gep_i8(ptr %addr) {
+  define void @test_gep_i8c(ptr %addr) {
     %arrayidx = getelementptr i32, ptr undef, i8 5
     ret void
   }
+  define void @test_gep_i8(ptr %addr, i8 %ofs) {
+    %arrayidx = getelementptr i32, ptr undef, i8 %ofs
+    ret void
+  }
 
-  define void @test_gep_i16(ptr %addr) {
+  define void @test_gep_i16c(ptr %addr) {
     %arrayidx = getelementptr i32, ptr undef, i16 5
     ret void
   }
+  define void @test_gep_i16(ptr %addr, i16 %ofs) {
+    %arrayidx = getelementptr i32, ptr undef, i16 %ofs
+    ret void
+  }
 
-  define void @test_gep_i32(ptr %addr) {
+  define void @test_gep_i32c(ptr %addr) {
     %arrayidx = getelementptr i32, ptr undef, i32 5
     ret void
   }
+  define void @test_gep_i32(ptr %addr, i32 %ofs) {
+    %arrayidx = getelementptr i32, ptr undef, i32 %ofs
+    ret void
+  }
 
-  define void @test_gep_i64(ptr %addr) {
+  define void @test_gep_i64c(ptr %addr) {
     %arrayidx = getelementptr i32, ptr undef, i64 5
     ret void
   }
+  define void @test_gep_i64(ptr %addr, i64 %ofs) {
+    %arrayidx = getelementptr i32, ptr undef, i64 %ofs
+    ret void
+  }
+...
+---
+name:            test_gep_i8c
+legalized:       false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.1 (%ir-block.0):
+    ; CHECK-LABEL: name: test_gep_i8c
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; CHECK-NEXT: RET 0
+    %0(p0) = IMPLICIT_DEF
+    %1(s8) = G_CONSTANT i8 20
+    %2(p0) = G_PTR_ADD %0, %1(s8)
+    G_STORE %2, %0 :: (store (p0) into %ir.addr)
+    RET 0
 ...
 ---
 name:            test_gep_i8
 legalized:       false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_gep_i8
     ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
-    ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
-    ; CHECK: RET 0
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s8)
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
+    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; CHECK-NEXT: RET 0
     %0(p0) = IMPLICIT_DEF
-    %1(s8) = G_CONSTANT i8 20
+    %1(s8) = IMPLICIT_DEF
     %2(p0) = G_PTR_ADD %0, %1(s8)
     G_STORE %2, %0 :: (store (p0) into %ir.addr)
     RET 0
 ...
 ---
+name:            test_gep_i16c
+legalized:       false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.1 (%ir-block.0):
+    ; CHECK-LABEL: name: test_gep_i16c
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; CHECK-NEXT: RET 0
+    %0(p0) = IMPLICIT_DEF
+    %1(s16) = G_CONSTANT i16 20
+    %2(p0) = G_PTR_ADD %0, %1(s16)
+    G_STORE %2, %0 :: (store (p0) into %ir.addr)
+    RET 0
+...
+---
 name:            test_gep_i16
 legalized:       false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_gep_i16
     ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
-    ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
-    ; CHECK: RET 0
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s16)
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
+    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; CHECK-NEXT: RET 0
     %0(p0) = IMPLICIT_DEF
-    %1(s16) = G_CONSTANT i16 20
+    %1(s16) = IMPLICIT_DEF
     %2(p0) = G_PTR_ADD %0, %1(s16)
     G_STORE %2, %0 :: (store (p0) into %ir.addr)
     RET 0
 ...
 ---
-name:            test_gep_i32
+name:            test_gep_i32c
 legalized:       false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
-    ; CHECK-LABEL: name: test_gep_i32
+    ; CHECK-LABEL: name: test_gep_i32c
     ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
-    ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
-    ; CHECK: RET 0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; CHECK-NEXT: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s32) = G_CONSTANT i32 20
     %2(p0) = G_PTR_ADD %0, %1(s32)
     G_STORE %2, %0 :: (store (p0) into %ir.addr)
     RET 0
 ...
 ---
-name:            test_gep_i64
+name:            test_gep_i32
 legalized:       false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
-    ; CHECK-LABEL: name: test_gep_i64
+    ; CHECK-LABEL: name: test_gep_i32
     ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
-    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
-    ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
-    ; CHECK: RET 0
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s32)
+    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; CHECK-NEXT: RET 0
+    %0(p0) = IMPLICIT_DEF
+    %1(s32) = IMPLICIT_DEF
+    %2(p0) = G_PTR_ADD %0, %1(s32)
+    G_STORE %2, %0 :: (store (p0) into %ir.addr)
+    RET 0
+...
+---
+name:            test_gep_i64c
+legalized:       false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.1 (%ir-block.0):
+    ; X64-LABEL: name: test_gep_i64c
+    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
+    ; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
+    ; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; X64-NEXT: RET 0
+    ; X86-LABEL: name: test_gep_i64c
+    ; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+    ; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; X86-NEXT: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s64) = G_CONSTANT i64 20
     %2(p0) = G_PTR_ADD %0, %1(s64)
     G_STORE %2, %0 :: (store (p0) into %ir.addr)
     RET 0
 ...
+---
+name:            test_gep_i64
+legalized:       false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.1 (%ir-block.0):
+    ; X64-LABEL: name: test_gep_i64
+    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+    ; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s64)
+    ; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; X64-NEXT: RET 0
+    ; X86-LABEL: name: test_gep_i64
+    ; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+    ; X86-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
+    ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[TRUNC]](s32)
+    ; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+    ; X86-NEXT: RET 0
+    %0(p0) = IMPLICIT_DEF
+    %1(s64) = IMPLICIT_DEF
+    %2(p0) = G_PTR_ADD %0, %1(s64)
+    G_STORE %2, %0 :: (store (p0) into %ir.addr)
+    RET 0
+...