ARM: default to arm_aapcscc (or VFP) for embedded MachO targets.

[t.p.northover]

Summary

These were always intended to be AAPCS targets and LLVM does treat the usual C calling convention that way, but some refactoring over time seems to have lost that so now they get lots of extra arm_aapcscc decoration that's not needed.

[t.p.northover]

Ping.

clang/lib/CodeGen/TargetInfo.cpp

void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
   llvm::CallingConv::ID cc = getRuntimeCC();
   if (cc != llvm::CallingConv::C)
     FI.setEffectiveCallingConvention(cc);
 }
 
 /// Return the default calling convention that LLVM will use.
 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
   // The default calling convention that LLVM will infer.
-  if (isEABIHF() || getTarget().getTriple().isWatchABI())
+  const llvm::Triple &TT = getTarget().getTriple();
+  if (isEABIHF() || TT.isWatchABI() ||
+      (TT.isOSBinFormatMachO() &&
+       TT.getSubArch() == llvm::Triple::ARMSubArch_v7em))
     return llvm::CallingConv::ARM_AAPCS_VFP;
-  else if (isEABI())
+  else if (isEABI() || (TT.isOSBinFormatMachO() && !TT.isOSDarwin()))
     return llvm::CallingConv::ARM_AAPCS;
   else
     return llvm::CallingConv::ARM_APCS;
 }
 
 /// Return the calling convention that our ABI would like us to use
 /// as the C calling convention.
 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {

clang/test/CodeGen/arm-macho-embedded.c

+// RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho %s -emit-llvm -o - | FileCheck %s
+
+// N.b. the default (C) calling convention for embedded MachO is AAPCS so we
+// don't want Clang generating arm_aapcscc or arm_aapcs_vfpcc for basic
+// functions.
+
+// CHECK: define void @func()
+void func() {
+}

clang/test/CodeGen/atomic-arm.c

 // CHECK-HOSTED: @always8 = global i32 1
 
 int always1 = __atomic_always_lock_free(1, 0);
 int always4 = __atomic_always_lock_free(4, 0);
 int always8 = __atomic_always_lock_free(8, 0);
 
 int lock_free_1() {
   // CHECK-LABEL: @lock_free_1
-  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 1, ptr noundef null)
+  // CHECK-V6M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 1, ptr noundef null)
   // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V6M:   ret i32 [[RES32]]
 
   // CHECK-V7M: ret i32 1
   // CHECK-HOSTED: ret i32 1
   return __c11_atomic_is_lock_free(1);
 }
 
 int lock_free_4() {
   // CHECK-LABEL: @lock_free_4
-  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 4, ptr noundef null)
+  // CHECK-V6M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 4, ptr noundef null)
   // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V6M:   ret i32 [[RES32]]
 
   // CHECK-V7M: ret i32 1
   // CHECK-HOSTED: ret i32 1
   return __c11_atomic_is_lock_free(4);
 }
 
 int lock_free_8() {
   // CHECK-LABEL: @lock_free_8
-  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
+  // CHECK-V6M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
   // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V6M:   ret i32 [[RES32]]
 
-  // CHECK-V7M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
+  // CHECK-V7M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
   // CHECK-V7M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V7M:   ret i32 [[RES32]]
 
   // CHECK-HOSTED: ret i32 1
   return __c11_atomic_is_lock_free(8);
 }