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Differential D15132

[X86][SSE] Update the cost table for integer-integer conversions on SSE2.
ClosedPublic

Authored by congh on Dec 1 2015, 4:02 PM.

Details

Reviewers
RKSimon
davidxl
hfinkel
Commits
rG59898d8c6806: [X86][SSE] Update the cost table for integer-integer conversions on SSE2/SSE4.1.
rL255315: [X86][SSE] Update the cost table for integer-integer conversions on SSE2/SSE4.1.
Summary

Previously in the conversion cost table there are no entries for integer-integer conversions on SSE2. This will result in imprecise costs for certain vectorized operations. This patch adds those entries for SSE2. The cost numbers are counted from the result of running llc on the new test case in this patch.

Diff Detail

Event Timeline

congh updated this revision to Diff 41572.Dec 1 2015, 4:02 PM
congh retitled this revision from to [X86][SSE] Update the cost table for integer-integer conversions on SSE2..
congh updated this object.
congh added reviewers: hfinkel, RKSimon, davidxl.
congh added a subscriber: llvm-commits.
RKSimon added inline comments.Dec 8 2015, 7:04 AM
lib/Target/X86/X86TargetTransformInfo.cpp
734

These values don't appear to be correct for SSE41 which has PMOVSX/PMOVZX ops - maybe split off the 128-bit extension ops from AVXConversionTbl into SSE41ConversionTbl ?

congh added inline comments.Dec 8 2015, 10:30 AM
lib/Target/X86/X86TargetTransformInfo.cpp
734

SSSE3 also provides pshufb from which several operations here can benefit. So you suggestion adding more tables for SSSE3/SSE4.1?

RKSimon added inline comments.Dec 9 2015, 6:48 AM
lib/Target/X86/X86TargetTransformInfo.cpp
734

You may not need SSSE3 (often PSHUFB is as costly as fixed shuffles on older hardware - it just reduces register use) but splitting the extensions from AVX into SSE41 needs to be done.

755

I haven't checked this very thoroughly but you might need to improve non-simple type handling here, especially for extensions?

congh added inline comments.Dec 9 2015, 5:19 PM
lib/Target/X86/X86TargetTransformInfo.cpp
734

I agree. SSE41 really provides several instructions that can greatly reduce those costs. I have added a table for SSE41 and also updated the test case. PTAL.

755

This patch is actually adding cost entries for non-simple types. I added another query on the table below for non-simple types except this one. Those entries of float/int conversions also need to be updated for non-simple types and I will do it later. To prevent vector-size/types combination explosion, I think we probably need to redesign the cost table.

congh updated this revision to Diff 42362.Dec 9 2015, 5:19 PM

Update the patch by adding a cost table for SSE4.1. The test case is also updated accordingly.

RKSimon accepted this revision.Dec 10 2015, 6:50 AM
RKSimon edited edge metadata.

LGTM - if possible please add a FIXME comment describing the future work necessary to improve the handling of simple + non-simple types.

This revision is now accepted and ready to land.Dec 10 2015, 6:50 AM
Closed by commit rL255315: [X86][SSE] Update the cost table for integer-integer conversions on SSE2/SSE4.1. (authored by conghou). · Explain WhyDec 10 2015, 4:34 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
78 lines
test/
Analysis/
CostModel/
X86/
6 lines
353 lines

Diff 42362

lib/Target/X86/X86TargetTransformInfo.cpp

Show First 20 Lines • Show All 655 Lines • ▼ Show 20 Lines static const TypeConversionCostTblEntry AVXConversionTbl[] = {
// optimistic estimating its cost. It computes 3 per element (one // optimistic estimating its cost. It computes 3 per element (one
// vector-extract, one scalar conversion and one vector-insert). The // vector-extract, one scalar conversion and one vector-insert). The
// problem is that the inserts form a read-modify-write chain so latency // problem is that the inserts form a read-modify-write chain so latency
// should be factored in too. Inflating the cost per element by 1. // should be factored in too. Inflating the cost per element by 1.
{ ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
}; };
static const TypeConversionCostTblEntry SSE2ConvTbl[] = { static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
{ ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
{ ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
{ ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
{ ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
{ ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
{ ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
{ ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
{ ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
{ ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 },
{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 30 },
{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 },
{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 },
};
static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
// These are somewhat magic numbers justified by looking at the output of // These are somewhat magic numbers justified by looking at the output of
// Intel's IACA, running some kernels and making sure when we take // Intel's IACA, running some kernels and making sure when we take
// legalization into account the throughput will be overestimated. // legalization into account the throughput will be overestimated.
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
// There are faster sequences for float conversions. // There are faster sequences for float conversions.
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
{ ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
{ ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
{ ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 },
{ ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 },
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
{ ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
{ ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 },
{ ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
{ ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
RKSimonUnsubmitted
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These values don't appear to be correct for SSE41 which has PMOVSX/PMOVZX ops - maybe split off the 128-bit extension ops from AVXConversionTbl into SSE41ConversionTbl ?

RKSimon: These values don't appear to be correct for SSE41 which has PMOVSX/PMOVZX ops - maybe split off…
conghAuthorUnsubmitted
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SSSE3 also provides pshufb from which several operations here can benefit. So you suggestion adding more tables for SSSE3/SSE4.1?

congh: SSSE3 also provides pshufb from which several operations here can benefit. So you suggestion…
RKSimonUnsubmitted
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You may not need SSSE3 (often PSHUFB is as costly as fixed shuffles on older hardware - it just reduces register use) but splitting the extensions from AVX into SSE41 needs to be done.

RKSimon: You may not need SSSE3 (often PSHUFB is as costly as fixed shuffles on older hardware - it just…
conghAuthorUnsubmitted
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I agree. SSE41 really provides several instructions that can greatly reduce those costs. I have added a table for SSE41 and also updated the test case. PTAL.

congh: I agree. SSE41 really provides several instructions that can greatly reduce those costs. I have…
{ ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 14 },
{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 7 },
{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 },
{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 31 },
{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 },
{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 },
}; };
std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst);
if (ST->hasSSE2() && !ST->hasAVX()) { if (ST->hasSSE2() && !ST->hasAVX()) {
if (const auto *Entry = ConvertCostTableLookup(SSE2ConvTbl, ISD, if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
LTDest.second, LTSrc.second)) LTDest.second, LTSrc.second))
return LTSrc.first * Entry->Cost; return LTSrc.first * Entry->Cost;
} }
RKSimonUnsubmitted
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I haven't checked this very thoroughly but you might need to improve non-simple type handling here, especially for extensions?

RKSimon: I haven't checked this very thoroughly but you might need to improve non-simple type handling…
conghAuthorUnsubmitted
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This patch is actually adding cost entries for non-simple types. I added another query on the table below for non-simple types except this one. Those entries of float/int conversions also need to be updated for non-simple types and I will do it later. To prevent vector-size/types combination explosion, I think we probably need to redesign the cost table.

congh: This patch is actually adding cost entries for non-simple types. I added another query on the…
if (ST->hasAVX512()) { if (ST->hasAVX512()) {
if (const auto *Entry = ConvertCostTableLookup(AVX512ConversionTbl, ISD, if (const auto *Entry = ConvertCostTableLookup(AVX512ConversionTbl, ISD,
LTDest.second, LTSrc.second)) LTDest.second, LTSrc.second))
return Entry->Cost; return Entry->Cost;
} }
EVT SrcTy = TLI->getValueType(DL, Src); EVT SrcTy = TLI->getValueType(DL, Src);
EVT DstTy = TLI->getValueType(DL, Dst); EVT DstTy = TLI->getValueType(DL, Dst);
Show All 11 Linesint X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
if (ST->hasAVX()) { if (ST->hasAVX()) {
if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
DstTy.getSimpleVT(), DstTy.getSimpleVT(),
SrcTy.getSimpleVT())) SrcTy.getSimpleVT()))
return Entry->Cost; return Entry->Cost;
} }
if (ST->hasSSE41()) {
if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
DstTy.getSimpleVT(),
SrcTy.getSimpleVT()))
return Entry->Cost;
}
if (ST->hasSSE2()) {
if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
DstTy.getSimpleVT(),
SrcTy.getSimpleVT()))
return Entry->Cost;
}
return BaseT::getCastInstrCost(Opcode, Dst, Src); return BaseT::getCastInstrCost(Opcode, Dst, Src);
} }
int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
// Legalize the type. // Legalize the type.
std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
MVT MTy = LT.second; MVT MTy = LT.second;
▲ Show 20 Lines • Show All 482 Lines • Show Last 20 Lines

test/Analysis/CostModel/X86/sitofp.ll

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Linesdefine <32 x double> @sitofpv32i32v32double(<32 x i32> %a) {
ret <32 x double> %1 ret <32 x double> %1
} }
define <2 x double> @sitofpv2i64v2double(<2 x i64> %a) { define <2 x double> @sitofpv2i64v2double(<2 x i64> %a) {
; SSE2: sitofpv2i64v2double ; SSE2: sitofpv2i64v2double
; SSE2: cost of 20 {{.*}} sitofp ; SSE2: cost of 20 {{.*}} sitofp
; ;
; AVX1: sitofpv2i64v2double ; AVX1: sitofpv2i64v2double
; AVX1: cost of 4 {{.*}} sitofp ; AVX1: cost of 20 {{.*}} sitofp
; ;
; AVX2: sitofpv2i64v2double ; AVX2: sitofpv2i64v2double
; AVX2: cost of 4 {{.*}} sitofp ; AVX2: cost of 20 {{.*}} sitofp
; ;
; AVX512F: sitofpv2i64v2double ; AVX512F: sitofpv2i64v2double
; AVX512F: cost of 4 {{.*}} sitofp ; AVX512F: cost of 20 {{.*}} sitofp
%1 = sitofp <2 x i64> %a to <2 x double> %1 = sitofp <2 x i64> %a to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
define <4 x double> @sitofpv4i64v4double(<4 x i64> %a) { define <4 x double> @sitofpv4i64v4double(<4 x i64> %a) {
; SSE2: sitofpv4i64v4double ; SSE2: sitofpv4i64v4double
; SSE2: cost of 40 {{.*}} sitofp ; SSE2: cost of 40 {{.*}} sitofp
; ;
▲ Show 20 Lines • Show All 413 Lines • Show Last 20 Lines

test/Analysis/CostModel/X86/sse-itoi.ll

  • This file was added.
; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s
; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse4.1 -cost-model -analyze < %s | FileCheck --check-prefix=SSE41 %s
define void @zext_v16i16_to_v16i32(<16 x i16>* %a) {
; SSE2: zext_v16i16_to_v16i32
; SSE2: cost of 6 {{.*}} zext
;
; SSE41: zext_v16i16_to_v16i32
; SSE41: cost of 4 {{.*}} zext
;
%1 = load <16 x i16>, <16 x i16>* %a
%2 = zext <16 x i16> %1 to <16 x i32>
store <16 x i32> %2, <16 x i32>* undef, align 4
ret void
}
define void @sext_v16i16_to_v16i32(<16 x i16>* %a) {
; SSE2: sext_v16i16_to_v16i32
; SSE2: cost of 8 {{.*}} sext
;
; SSE41: sext_v16i16_to_v16i32
; SSE41: cost of 4 {{.*}} sext
;
%1 = load <16 x i16>, <16 x i16>* %a
%2 = sext <16 x i16> %1 to <16 x i32>
store <16 x i32> %2, <16 x i32>* undef, align 4
ret void
}
define void @zext_v8i16_to_v8i32(<8 x i16>* %a) {
; SSE2: zext_v8i16_to_v8i32
; SSE2: cost of 3 {{.*}} zext
;
; SSE41: zext_v8i16_to_v8i32
; SSE41: cost of 2 {{.*}} zext
;
%1 = load <8 x i16>, <8 x i16>* %a
%2 = zext <8 x i16> %1 to <8 x i32>
store <8 x i32> %2, <8 x i32>* undef, align 4
ret void
}
define void @sext_v8i16_to_v8i32(<8 x i16>* %a) {
; SSE2: sext_v8i16_to_v8i32
; SSE2: cost of 4 {{.*}} sext
;
; SSE41: sext_v8i16_to_v8i32
; SSE41: cost of 2 {{.*}} sext
;
%1 = load <8 x i16>, <8 x i16>* %a
%2 = sext <8 x i16> %1 to <8 x i32>
store <8 x i32> %2, <8 x i32>* undef, align 4
ret void
}
define void @zext_v4i16_to_v4i32(<4 x i16>* %a) {
; SSE2: zext_v4i16_to_v4i32
; SSE2: cost of 1 {{.*}} zext
;
; SSE41: zext_v4i16_to_v4i32
; SSE41: cost of 1 {{.*}} zext
;
%1 = load <4 x i16>, <4 x i16>* %a
%2 = zext <4 x i16> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32>* undef, align 4
ret void
}
define void @sext_v4i16_to_v4i32(<4 x i16>* %a) {
; SSE2: sext_v4i16_to_v4i32
; SSE2: cost of 2 {{.*}} sext
;
; SSE41: sext_v4i16_to_v4i32
; SSE41: cost of 1 {{.*}} sext
;
%1 = load <4 x i16>, <4 x i16>* %a
%2 = sext <4 x i16> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32>* undef, align 4
ret void
}
define void @zext_v16i8_to_v16i32(<16 x i8>* %a) {
; SSE2: zext_v16i8_to_v16i32
; SSE2: cost of 9 {{.*}} zext
;
; SSE41: zext_v16i8_to_v16i32
; SSE41: cost of 4 {{.*}} zext
;
%1 = load <16 x i8>, <16 x i8>* %a
%2 = zext <16 x i8> %1 to <16 x i32>
store <16 x i32> %2, <16 x i32>* undef, align 4
ret void
}
define void @sext_v16i8_to_v16i32(<16 x i8>* %a) {
; SSE2: sext_v16i8_to_v16i32
; SSE2: cost of 12 {{.*}} sext
;
; SSE41: sext_v16i8_to_v16i32
; SSE41: cost of 4 {{.*}} sext
;
%1 = load <16 x i8>, <16 x i8>* %a
%2 = sext <16 x i8> %1 to <16 x i32>
store <16 x i32> %2, <16 x i32>* undef, align 4
ret void
}
define void @zext_v8i8_to_v8i32(<8 x i8>* %a) {
; SSE2: zext_v8i8_to_v8i32
; SSE2: cost of 6 {{.*}} zext
;
; SSE41: zext_v8i8_to_v8i32
; SSE41: cost of 2 {{.*}} zext
;
%1 = load <8 x i8>, <8 x i8>* %a
%2 = zext <8 x i8> %1 to <8 x i32>
store <8 x i32> %2, <8 x i32>* undef, align 4
ret void
}
define void @sext_v8i8_to_v8i32(<8 x i8>* %a) {
; SSE2: sext_v8i8_to_v8i32
; SSE2: cost of 6 {{.*}} sext
;
; SSE41: sext_v8i8_to_v8i32
; SSE41: cost of 2 {{.*}} sext
;
%1 = load <8 x i8>, <8 x i8>* %a
%2 = sext <8 x i8> %1 to <8 x i32>
store <8 x i32> %2, <8 x i32>* undef, align 4
ret void
}
define void @zext_v4i8_to_v4i32(<4 x i8>* %a) {
; SSE2: zext_v4i8_to_v4i32
; SSE2: cost of 2 {{.*}} zext
;
; SSE41: zext_v4i8_to_v4i32
; SSE41: cost of 1 {{.*}} zext
;
%1 = load <4 x i8>, <4 x i8>* %a
%2 = zext <4 x i8> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32>* undef, align 4
ret void
}
define void @sext_v4i8_to_v4i32(<4 x i8>* %a) {
; SSE2: sext_v4i8_to_v4i32
; SSE2: cost of 3 {{.*}} sext
;
; SSE41: sext_v4i8_to_v4i32
; SSE41: cost of 1 {{.*}} sext
;
%1 = load <4 x i8>, <4 x i8>* %a
%2 = sext <4 x i8> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32>* undef, align 4
ret void
}
define void @zext_v16i8_to_v16i16(<16 x i8>* %a) {
; SSE2: zext_v16i8_to_v16i16
; SSE2: cost of 3 {{.*}} zext
;
; SSE41: zext_v16i8_to_v16i16
; SSE41: cost of 2 {{.*}} zext
;
%1 = load <16 x i8>, <16 x i8>* %a
%2 = zext <16 x i8> %1 to <16 x i16>
store <16 x i16> %2, <16 x i16>* undef, align 4
ret void
}
define void @sext_v16i8_to_v16i16(<16 x i8>* %a) {
; SSE2: sext_v16i8_to_v16i16
; SSE2: cost of 4 {{.*}} sext
;
; SSE41: sext_v16i8_to_v16i16
; SSE41: cost of 2 {{.*}} sext
;
%1 = load <16 x i8>, <16 x i8>* %a
%2 = sext <16 x i8> %1 to <16 x i16>
store <16 x i16> %2, <16 x i16>* undef, align 4
ret void
}
define void @zext_v8i8_to_v8i16(<8 x i8>* %a) {
; SSE2: zext_v8i8_to_v8i16
; SSE2: cost of 1 {{.*}} zext
;
; SSE41: zext_v8i8_to_v8i16
; SSE41: cost of 1 {{.*}} zext
;
%1 = load <8 x i8>, <8 x i8>* %a
%2 = zext <8 x i8> %1 to <8 x i16>
store <8 x i16> %2, <8 x i16>* undef, align 4
ret void
}
define void @sext_v8i8_to_v8i16(<8 x i8>* %a) {
; SSE2: sext_v8i8_to_v8i16
; SSE2: cost of 2 {{.*}} sext
;
; SSE41: sext_v8i8_to_v8i16
; SSE41: cost of 1 {{.*}} sext
;
%1 = load <8 x i8>, <8 x i8>* %a
%2 = sext <8 x i8> %1 to <8 x i16>
store <8 x i16> %2, <8 x i16>* undef, align 4
ret void
}
define void @zext_v4i8_to_v4i16(<4 x i8>* %a) {
; SSE2: zext_v4i8_to_v4i16
; SSE2: cost of 1 {{.*}} zext
;
; SSE41: zext_v4i8_to_v4i16
; SSE41: cost of 1 {{.*}} zext
;
%1 = load <4 x i8>, <4 x i8>* %a
%2 = zext <4 x i8> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* undef, align 4
ret void
}
define void @sext_v4i8_to_v4i16(<4 x i8>* %a) {
; SSE2: sext_v4i8_to_v4i16
; SSE2: cost of 6 {{.*}} sext
;
; SSE41: sext_v4i8_to_v4i16
; SSE41: cost of 2 {{.*}} sext
;
%1 = load <4 x i8>, <4 x i8>* %a
%2 = sext <4 x i8> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* undef, align 4
ret void
}
define void @truncate_v16i32_to_v16i16(<16 x i32>* %a) {
; SSE2: truncate_v16i32_to_v16i16
; SSE2: cost of 14 {{.*}} trunc
;
; SSE41: truncate_v16i32_to_v16i16
; SSE41: cost of 6 {{.*}} trunc
;
%1 = load <16 x i32>, <16 x i32>* %a
%2 = trunc <16 x i32> %1 to <16 x i16>
store <16 x i16> %2, <16 x i16>* undef, align 4
ret void
}
define void @truncate_v8i32_to_v8i16(<8 x i32>* %a) {
; SSE2: truncate_v8i32_to_v8i16
; SSE2: cost of 7 {{.*}} trunc
;
; SSE41: truncate_v8i32_to_v8i16
; SSE41: cost of 3 {{.*}} trunc
;
%1 = load <8 x i32>, <8 x i32>* %a
%2 = trunc <8 x i32> %1 to <8 x i16>
store <8 x i16> %2, <8 x i16>* undef, align 4
ret void
}
define void @truncate_v4i32_to_v4i16(<4 x i32>* %a) {
; SSE2: truncate_v4i32_to_v4i16
; SSE2: cost of 3 {{.*}} trunc
;
; SSE41: truncate_v4i32_to_v4i16
; SSE41: cost of 1 {{.*}} trunc
;
%1 = load <4 x i32>, <4 x i32>* %a
%2 = trunc <4 x i32> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* undef, align 4
ret void
}
define void @truncate_v16i32_to_v16i8(<16 x i32>* %a) {
; SSE2: truncate_v16i32_to_v16i8
; SSE2: cost of 31 {{.*}} trunc
;
; SSE41: truncate_v16i32_to_v16i8
; SSE41: cost of 30 {{.*}} trunc
;
%1 = load <16 x i32>, <16 x i32>* %a
%2 = trunc <16 x i32> %1 to <16 x i8>
store <16 x i8> %2, <16 x i8>* undef, align 4
ret void
}
define void @truncate_v8i32_to_v8i8(<8 x i32>* %a) {
; SSE2: truncate_v8i32_to_v8i8
; SSE2: cost of 4 {{.*}} trunc
;
; SSE41: truncate_v8i32_to_v8i8
; SSE41: cost of 3 {{.*}} trunc
;
%1 = load <8 x i32>, <8 x i32>* %a
%2 = trunc <8 x i32> %1 to <8 x i8>
store <8 x i8> %2, <8 x i8>* undef, align 4
ret void
}
define void @truncate_v4i32_to_v4i8(<4 x i32>* %a) {
; SSE2: truncate_v4i32_to_v4i8
; SSE2: cost of 3 {{.*}} trunc
;
; SSE41: truncate_v4i32_to_v4i8
; SSE41: cost of 1 {{.*}} trunc
;
%1 = load <4 x i32>, <4 x i32>* %a
%2 = trunc <4 x i32> %1 to <4 x i8>
store <4 x i8> %2, <4 x i8>* undef, align 4
ret void
}
define void @truncate_v16i16_to_v16i8(<16 x i16>* %a) {
; SSE2: truncate_v16i16_to_v16i8
; SSE2: cost of 3 {{.*}} trunc
;
; SSE41: truncate_v16i16_to_v16i8
; SSE41: cost of 3 {{.*}} trunc
;
%1 = load <16 x i16>, <16 x i16>* %a
%2 = trunc <16 x i16> %1 to <16 x i8>
store <16 x i8> %2, <16 x i8>* undef, align 4
ret void
}
define void @truncate_v8i16_to_v8i8(<8 x i16>* %a) {
; SSE2: truncate_v8i16_to_v8i8
; SSE2: cost of 2 {{.*}} trunc
;
; SSE41: truncate_v8i16_to_v8i8
; SSE41: cost of 1 {{.*}} trunc
;
%1 = load <8 x i16>, <8 x i16>* %a
%2 = trunc <8 x i16> %1 to <8 x i8>
store <8 x i8> %2, <8 x i8>* undef, align 4
ret void
}
define void @truncate_v4i16_to_v4i8(<4 x i16>* %a) {
; SSE2: truncate_v4i16_to_v4i8
; SSE2: cost of 4 {{.*}} trunc
;
; SSE41: truncate_v4i16_to_v4i8
; SSE41: cost of 2 {{.*}} trunc
;
%1 = load <4 x i16>, <4 x i16>* %a
%2 = trunc <4 x i16> %1 to <4 x i8>
store <4 x i8> %2, <4 x i8>* undef, align 4
ret void
}