[mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocation

[dsanders]

This patch LGTM but there's a quirk that we may need to worry about in some LLVM components (e.g. CodeGen, MCJIT, etc.) that I should mention.

This relocation and some of of the other new R_MICROMIPS_PC*_S* relocations have a slightly different concept of 'PC' compared to the relocations that came before. The difference is that the PC is rounded down to the specified alignment first whereas other relocations will happily use an unaligned PC. So the PC for R_MICROMIPS_PC18_S3 is 'PC & ~0x7'. I doubt there's much practical difference for the *_PC*_S2's and *_PC*_S1's because code needs to be correctly aligned anyway, but R_MICROMIPS_PC18_S3 requires a greater alignment than code does and may expose the difference more easily.

Another slight difference is that both the symbol and addend must be correctly aligned rather than merely that the sum of the two is correctly aligned. I'm told this is so that REL and RELA have the same constraints.

[dsanders]

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

137 ↗

(On Diff #41259)

Thinking about it a bit more, we should check the alignment here for the micromips case.

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

case Mips::fixup_MIPS_PC18_S3:
     // Forcing a signed division because Value can be negative.
     Value = (int64_t)Value / 8;
     // We now check if Value can be encoded as a 18-bit signed immediate.
     if (!isInt<18>(Value) && Ctx) {
       Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
       return 0;
     }
     break;
+  case Mips::fixup_MICROMIPS_PC18_S3:
+    // Check alignment.
+    if ((Value & 7) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
+    }
+    // Forcing a signed division because Value can be negative.
+    Value = (int64_t)Value / 8;
+    // We now check if Value can be encoded as a 18-bit signed immediate.
+    if (!isInt<18>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
+      return 0;
+    }
+    break;
   case Mips::fixup_MIPS_PC21_S2:
     // Forcing a signed division because Value can be negative.
     Value = (int64_t) Value / 4;
     // We now check if Value can be encoded as a 21-bit signed immediate.
     if (!isInt<21>(Value) && Ctx) {
       Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
       return 0;
     }
const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_MICROMIPS_HI16",    0,     16,   0 },
     { "fixup_MICROMIPS_LO16",    0,     16,   0 },
     { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
     { "fixup_MICROMIPS_PC7_S1",  0,      7,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC10_S1", 0,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1", 0,     16,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC26_S1", 0,     26,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC19_S2", 0,     19,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC18_S3", 0,     18,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
     { "fixup_MICROMIPS_GOT_OFST",        0,     16,   0 },
     { "fixup_MICROMIPS_TLS_GD",          0,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0,     16,   0 },
const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
     { "fixup_MICROMIPS_HI16",   16,     16,   0 },
     { "fixup_MICROMIPS_LO16",   16,     16,   0 },
     { "fixup_MICROMIPS_GOT16",  16,     16,   0 },
     { "fixup_MICROMIPS_PC7_S1",  9,      7,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC10_S1", 6,     10,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC16_S1",16,     16,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC26_S1", 6,     26,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_PC19_S2",13,     19,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_MICROMIPS_PC18_S3",14,     18,   MCFixupKindInfo::FKF_IsPCRel },
     { "fixup_MICROMIPS_CALL16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOT_DISP",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_PAGE",        16,     16,   0 },
     { "fixup_MICROMIPS_GOT_OFST",        16,     16,   0 },
     { "fixup_MICROMIPS_TLS_GD",          16,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16,     16,   0 },

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

if (IsPCRel) {
     case Mips::fixup_MICROMIPS_PC10_S1:
       return ELF::R_MICROMIPS_PC10_S1;
     case Mips::fixup_MICROMIPS_PC16_S1:
       return ELF::R_MICROMIPS_PC16_S1;
     case Mips::fixup_MICROMIPS_PC26_S1:
       return ELF::R_MICROMIPS_PC26_S1;
     case Mips::fixup_MICROMIPS_PC19_S2:
       return ELF::R_MICROMIPS_PC19_S2;
+    case Mips::fixup_MICROMIPS_PC18_S3:
+      return ELF::R_MICROMIPS_PC18_S3;
     case Mips::fixup_MIPS_PC19_S2:
       return ELF::R_MIPS_PC19_S2;
     case Mips::fixup_MIPS_PC18_S3:
       return ELF::R_MIPS_PC18_S3;
     case Mips::fixup_MIPS_PC21_S2:
       return ELF::R_MIPS_PC21_S2;
     case Mips::fixup_MIPS_PC26_S2:
       return ELF::R_MIPS_PC26_S2;

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

enum Fixups {
     fixup_MICROMIPS_PC16_S1,
 
     // resulting in - R_MICROMIPS_PC26_S1
     fixup_MICROMIPS_PC26_S1,
 
     // resulting in - R_MICROMIPS_PC19_S2
     fixup_MICROMIPS_PC19_S2,
 
+    // resulting in - R_MICROMIPS_PC18_S3
+    fixup_MICROMIPS_PC18_S3,
+
     // resulting in - R_MICROMIPS_CALL16
     fixup_MICROMIPS_CALL16,
 
     // resulting in - R_MICROMIPS_GOT_DISP
     fixup_MICROMIPS_GOT_DISP,
 
     // resulting in - R_MICROMIPS_GOT_PAGE
     fixup_MICROMIPS_GOT_PAGE,

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

if (MO.isImm()) {
     assert((Res & 7) == 0);
     return Res >> 3;
   }
 
   assert(MO.isExpr() &&
          "getSimm18Lsl2Encoding expects only expressions or an immediate");
 
   const MCExpr *Expr = MO.getExpr();
-  Fixups.push_back(MCFixup::create(0, Expr,
-                                   MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
+  Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
+                                            : Mips::fixup_MIPS_PC18_S3;
+  Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
   return 0;
 }
 
 unsigned
 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
   assert(MI.getOperand(OpNo).isImm());

llvm/trunk/test/MC/Mips/micromips32r6/relocations.s

 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
+# CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
   bc    bar
   addiupc $2,bar
   lwpc    $2,bar

llvm/trunk/test/MC/Mips/micromips64r6/relocations.s

 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC26_S1
 # CHECK-FIXUP: addiupc $2, bar  # encoding: [0x78,0b01000AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
 # CHECK-FIXUP: lwpc    $2,  bar # encoding: [0x78,0b01001AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
+# CHECK-FIXUP: ldpc  $2, bar    # encoding: [0x78,0b010110AA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC18_S3
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
+# CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x10 R_MICROMIPS_PC18_S3 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
   bc    bar
   addiupc $2,bar
   lwpc    $2,bar
+  ldpc  $2, bar