[LoongArch] Support fcc* (condition flag) registers in inlineasm clobbers

[hev]

Thanks!

[xen0n]

It's confirmed offline that LA32 also has 8 $fcc's, so the existing assumption holds, and the code changes are correct. (Apparently the "LA32 Reduced" subset is not supported right now, which only has one $fcc0.)

clang/lib/Basic/Targets/LoongArch.cpp

static const char *const GCCRegNames[] = {
       "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", "$r8", "$r9",
       "$r10", "$r11", "$r12", "$r13", "$r14", "$r15", "$r16", "$r17", "$r18",
       "$r19", "$r20", "$r21", "$r22", "$r23", "$r24", "$r25", "$r26", "$r27",
       "$r28", "$r29", "$r30", "$r31",
       // Floating point registers.
       "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
       "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
       "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
-      "$f28", "$f29", "$f30", "$f31"};
+      "$f28", "$f29", "$f30", "$f31",
+      // Condition flag registers.
+      "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7"};
   return llvm::ArrayRef(GCCRegNames);
 }
 
 ArrayRef<TargetInfo::GCCRegAlias>
 LoongArchTargetInfo::getGCCRegAliases() const {
   static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
       {{"$zero"}, "$r0"},       {{"$ra"}, "$r1"},    {{"$tp"}, "$r2"},
       {{"$sp"}, "$r3"},         {{"$a0"}, "$r4"},    {{"$a1"}, "$r5"},

clang/test/CodeGen/LoongArch/inline-asm-gcc-regs-error.c

 // CHECK: :[[#@LINE+1]]:24: error: unknown register name 'r4' in asm
   register int a3 asm ("r4");
 // CHECK: :[[#@LINE+1]]:24: error: unknown register name 'a0' in asm
   register int a4 asm ("a0");
 // CHECK: :[[#@LINE+1]]:26: error: unknown register name 'f0' in asm
   register float a5 asm ("f0");
 // CHECK: :[[#@LINE+1]]:26: error: unknown register name 'fa0' in asm
   register float a6 asm ("fa0");
+// CHECK: :[[#@LINE+1]]:15: error: unknown register name 'fcc0' in asm
+  asm ("" ::: "fcc0");
 }

clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c

 }
 
 // CHECK-LABEL: @test_fs2
 // CHECK: call void asm sideeffect "", "{$f26}"(float undef)
 void test_fs2() {
     register float a asm ("$fs2");
     asm ("" :: "f" (a));
 }
+
+// CHECK-LABEL: @test_fcc
+// CHECK: call void asm sideeffect "", "~{$fcc0}"()
+// CHECK: call void asm sideeffect "", "~{$fcc7}"()
+void test_fcc() {
+    asm ("" ::: "$fcc0");
+    asm ("" ::: "$fcc7");
+}

llvm/test/CodeGen/LoongArch/inline-asm-clobbers-fcc.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc --mtriple=loongarch64 --mattr=+d --run-pass=greedy %s -o - | FileCheck %s
+
+## Check that fcc register clobbered by inlineasm is correctly saved by examing
+## a pair of pseudos (PseudoST_CFR and PseudoLD_CFR) are generated before and
+## after the INLINEASM.
+...
+---
+name: test
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $f0_64, $f1_64
+
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $f0_64, $f1_64
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f1_64
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f0_64
+    ; CHECK-NEXT: [[FCMP_CLT_D:%[0-9]+]]:cfr = FCMP_CLT_D [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: PseudoST_CFR [[FCMP_CLT_D]], %stack.0, 0 :: (store (s64) into %stack.0)
+    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $fcc0
+    ; CHECK-NEXT: [[PseudoLD_CFR:%[0-9]+]]:cfr = PseudoLD_CFR %stack.0, 0 :: (load (s64) from %stack.0)
+    ; CHECK-NEXT: $r4 = COPY [[PseudoLD_CFR]]
+    ; CHECK-NEXT: PseudoRET implicit killed $r4
+    %1:fpr64 = COPY $f1_64
+    %0:fpr64 = COPY $f0_64
+    %2:cfr = FCMP_CLT_D %1, %0
+    INLINEASM &"nop", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $fcc0
+    $r4 = COPY %2
+    PseudoRET implicit killed $r4
+
+...