[NFC]adjust identaion and update comments in X86InstrArithmeic.td

[XinWang10]

Summary

After https://reviews.llvm.org/D144154, I introduce some identation issues,
and some comments are not that precise.

[skan]

LGTM

llvm/lib/Target/X86/X86InstrArithmetic.td

: BinOpMR<opcode, mnemonic, typeinfo,
              (implicit EFLAGS)]>,
     Sched<[WriteALURMW,
            // base, scale, index, offset, segment
            ReadDefault, ReadDefault, ReadDefault,
            ReadDefault, ReadDefault,
            WriteALU.ReadAfterFold]>;  // reg
 
 // BinOpMR_RMW_FF - Binary instructions with inputs "[mem], reg", where the
-// pattern use EFLAGS as operand and implicitly use EFLAGS.
+// pattern sets EFLAGS and implicitly uses EFLAGS.
 class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
                      SDNode opnode>
   : BinOpMR<opcode, mnemonic, typeinfo,
             [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
                     addr:$dst),
              (implicit EFLAGS)]>,
     Sched<[WriteADCRMW,
           // base, scale, index, offset, segment
           ReadDefault, ReadDefault, ReadDefault,
           ReadDefault, ReadDefault,
class BinOpMI_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
                   SDNode opnode, Format f>
   : BinOpMI<opcode, mnemonic, typeinfo, f,
             [(store (opnode (typeinfo.VT (load addr:$dst)),
                             typeinfo.ImmOperator:$src), addr:$dst),
              (implicit EFLAGS)]>,
     Sched<[WriteALURMW]>;
 
 // BinOpMI_RMW_FF - Binary instructions with inputs "[mem], imm", where the
-// pattern use EFLAGS as operand and implicitly use EFLAGS.
+// pattern sets EFLAGS and implicitly uses EFLAGS.
 class BinOpMI_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
                      SDNode opnode, Format f>
   : BinOpMI<opcode, mnemonic, typeinfo, f,
             [(store (opnode (typeinfo.VT (load addr:$dst)),
                              typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
                              (implicit EFLAGS)]>,
     Sched<[WriteADCRMW]>;
 
class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
                    SDPatternOperator opnode, Format f>
   : BinOpMI8<mnemonic, typeinfo, f,
              [(store (opnode (load addr:$dst),
                              typeinfo.Imm8Operator:$src), addr:$dst),
               (implicit EFLAGS)]>,
     Sched<[WriteALURMW]>;
 
 // BinOpMI8_RMW_FF - Binary instructions with inputs "[mem], imm8", where the
-// pattern use EFLAGS as operand and implicitly use EFLAGS.
+// pattern sets EFLAGS and implicitly uses EFLAGS.
 class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
                       SDPatternOperator opnode, Format f>
   : BinOpMI8<mnemonic, typeinfo, f,
              [(store (opnode (load addr:$dst),
                              typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
               (implicit EFLAGS)]>,
     Sched<[WriteADCRMW]>;
 
class UnaryOpR<bits<8> opcode, Format f, string mnemonic, X86TypeInfo info,
                list<dag> pattern>
   : ITy<opcode, f, info, (outs info.RegClass:$dst),
         (ins info.RegClass:$src1), mnemonic, "$dst", pattern>;
 
 //  INCDECR - Instructions like "inc reg".
 class INCDECR<Format f, string mnemonic, X86TypeInfo info,
               SDPatternOperator node>
   : UnaryOpR<0xFE, f, mnemonic, info,
-               [(set info.RegClass:$dst, EFLAGS,
-               (node info.RegClass:$src1, 1))]>;
 
 //  INCDECM - Instructions like "inc [mem]".
 class INCDECM<Format f, string mnemonic, X86TypeInfo info, int num>
   : UnaryOpM<0xFE, f, mnemonic, info,
              [(store (add (info.LoadNode addr:$dst), num), addr:$dst),
               (implicit EFLAGS)]>;
 
 //  INCDECR_ALT - Instructions like "inc reg" short forms.

 class MulOpM<bits<8> opcode, Format f, string mnemonic, X86TypeInfo info,
              X86FoldableSchedWrite sched, list<dag> pattern>
   : ITy<opcode, f, info, (outs), (ins info.MemOperand:$src), mnemonic,
         "$src", pattern>, SchedLoadReg<sched>;
 
 //  NegOpR - Instructions like "neg reg", with implicit EFLAGS.
 class NegOpR<bits<8> opcode, string mnemonic, X86TypeInfo info>
   : UnaryOpR<opcode, MRM3r, mnemonic, info,
-               [(set info.RegClass:$dst, (ineg info.RegClass:$src1)),
-                (implicit EFLAGS)]>;
 
 //  NotOpR - Instructions like "not reg".
 class NotOpR<bits<8> opcode, string mnemonic, X86TypeInfo info>
   : UnaryOpR<opcode, MRM2r, mnemonic, info,
                [(set info.RegClass:$dst,
                 (not info.RegClass:$src1))]>;
 
 //  NegOpM - Instructions like "neg [mem]", with implicit EFLAGS.
: BinOpRM_C<opcode, MRMSrcMem, mnemonic, info,
               [(set info.RegClass:$dst, EFLAGS,
                 (X86smul_flag info.RegClass:$src1, (info.LoadNode addr:$src2)))]>,
     Sched<[sched.Folded, sched.ReadAfterFold]>, TB;
 
 // IMulOpRRI8 - Instructions like "imul reg, reg, i8".
 class IMulOpRRI8<bits<8> opcode, string mnemonic, X86TypeInfo info,
                  X86FoldableSchedWrite sched>
   : ITy<opcode, MRMSrcReg, info, (outs info.RegClass:$dst),
-               (ins info.RegClass:$src1,
-               info.Imm8Operand:$src2), mnemonic,
-               "{$src2, $src1, $dst|$dst, $src1, $src2}",
-               [(set info.RegClass:$dst, EFLAGS,
-                (X86smul_flag info.RegClass:$src1,
+        (ins info.RegClass:$src1, info.Imm8Operand:$src2), mnemonic,
                        info.Imm8NoSuOperator:$src2))]>,
     Sched<[sched]>{
   let ImmT = Imm8;
 }
 
 // IMulOpRRI - Instructions like "imul reg, reg, i16/i32/i64".
 class IMulOpRRI<bits<8> opcode, string mnemonic, X86TypeInfo info,
                 X86FoldableSchedWrite sched>
   : ITy<opcode, MRMSrcReg, info, (outs info.RegClass:$dst),
-               (ins info.RegClass:$src1,
-               info.ImmOperand:$src2), mnemonic,
-               "{$src2, $src1, $dst|$dst, $src1, $src2}",
-               [(set info.RegClass:$dst, EFLAGS,
-                (X86smul_flag info.RegClass:$src1,
+        (ins info.RegClass:$src1, info.ImmOperand:$src2), mnemonic,
                        info.ImmNoSuOperator:$src2))]>,
     Sched<[sched]>{
   let ImmT = info.ImmEncoding;
 }
 
 // IMulOpRMI8 - Instructions like "imul reg, [mem], i8".
 class IMulOpRMI8<bits<8> opcode, string mnemonic, X86TypeInfo info,
                  X86FoldableSchedWrite sched>
   : ITy<opcode, MRMSrcMem, info, (outs info.RegClass:$dst),
-               (ins info.MemOperand:$src1,
-               info.Imm8Operand:$src2), mnemonic,
-                "{$src2, $src1, $dst|$dst, $src1, $src2}",
-               [(set info.RegClass:$dst, EFLAGS,
-                (X86smul_flag (info.LoadNode addr:$src1),
+        (ins info.MemOperand:$src1, info.Imm8Operand:$src2), mnemonic,
                         info.Imm8NoSuOperator:$src2))]>,
     Sched<[sched.Folded]>{
   let ImmT = Imm8;
 }
 
 // IMulOpRMI - Instructions like "imul reg, [mem], i16/i32/i64".
 class IMulOpRMI<bits<8> opcode, string mnemonic, X86TypeInfo info,
                 X86FoldableSchedWrite sched>
   : ITy<opcode, MRMSrcMem, info, (outs info.RegClass:$dst),
-               (ins info.MemOperand:$src1,
-               info.ImmOperand:$src2), mnemonic,
-               "{$src2, $src1, $dst|$dst, $src1, $src2}",
-               [(set info.RegClass:$dst, EFLAGS,
-                  (X86smul_flag (info.LoadNode addr:$src1),
+        (ins info.MemOperand:$src1, info.ImmOperand:$src2), mnemonic,
                         info.ImmNoSuOperator:$src2))]>,
     Sched<[sched.Folded]>{
   let ImmT = info.ImmEncoding;
 }
 
 def X86add_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
                                (X86add_flag node:$lhs, node:$rhs), [{
   return hasNoCarryFlagUses(SDValue(N, 1));
 }]>;