[Power PC] fix calculating address of arguments on stack for variadic functions

[spetrovic]

Summary

This patch fixes calculating address of arguments larger than 32 bit on stack for variadic functions (rounding up address to alignment) on ppc32 architecture.

[hfinkel]

lib/CodeGen/TargetInfo.cpp

3547

You need to use variable names consistent with our coding convention (OverflowArgArea, etc.).

[rjmccall]

lib/CodeGen/TargetInfo.cpp

3548

This patch applies to more types than just double. You should probably add tests for some of the other cases, but if not, please at least make your commit message convey the intended generality.

3549

if (Align > OverflowAreaAlign)

3559

Would you mind extracting a function to do this realignment? There are 3-4 other places in this file that do exactly this. Using the existing code pattern from emitVoidPtrDirectVAArg — i.e. using an add instead of a non-inbounds GEP — seems reasonable.

I think this is a sensible prototype:

static Address emitRoundPointerUpToAlignment(CodeGenFunction &CGF, llvm::Value *Ptr, CharUnits Align, const llvm::Twine &Name);

3562

This code will be more readable if you keep Align as a CharUnits.

[rjmccall]

lib/CodeGen/TargetInfo.cpp

241

Thank you for extracting this.

First, this function deserves a doc comment now; I would suggest:

/// Dynamically round a pointer up to a multiple of the given alignment.

Also, this is now generically useful, so (1) please rename OverflowArgArea to something more generic, like Ptr, and (2) please use LLVM value names based on the name already in Ptr. That is, instead of "overflow_arg_area.align", please use

Ptr->getName () + ".aligned"

Finally, please look for the other places in this file that you could change to use this new function. There's one in emitVoidPtrDirectVAArg, and there are several other in other targets.

3551

Please sink OverflowArgArea into the if block, since you don't need it outside.

[spetrovic]

Comments addressed.

[rjmccall]

Thank you. A few more style complaints; with those fixed, LGTM.

lib/CodeGen/TargetInfo.cpp

166

Minor code-style nitpick: please put the * next to the function name, not the type.

211

LLVM code style is to always leave the braces there.

3091

Braces.

[spetrovic]

Comments addressed.

[rjmccall]

Please feel free to commit after you make this last change.

lib/CodeGen/TargetInfo.cpp

209

LLVM code style is to put the else on the same line as the closing brace.

lib/CodeGen/TargetInfo.cpp

void ABIArgInfo::dump() const {
   case Expand:
     OS << "Expand";
     break;
   }
   OS << ")\n";
 }
 
 /// Emit va_arg for a platform using the common void* representation,
 /// where arguments are simply emitted in an array of slots on the stack.
 ///
 /// This version implements the core direct-value passing rules.
 ///
 /// \param SlotSize - The size and alignment of a stack slot.
 ///   Each argument will be allocated to a multiple of this number of
 ///   slots, and all the slots will be aligned to this value.
 /// \param AllowHigherAlign - The slot alignment is not a cap;
 ///   an argument type with an alignment greater than the slot size
PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
              llvm::ConstantInt::get(CGF.IntPtrTy, -DirectAlign.getQuantity()));
     Addr = Address(CGF.Builder.CreateIntToPtr(PtrAsInt, Ptr->getType(),
                                               "argp.cur.aligned"),
                    DirectAlign);
   } else {
     Addr = Address(Ptr, SlotSize);
   }
 
   // Advance the pointer past the argument, then store that back.
   CharUnits FullDirectSize = DirectSize.RoundUpToAlignment(SlotSize);
   llvm::Value *NextPtr =
     CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
                                            "argp.next");
   CGF.Builder.CreateStore(NextPtr, VAListAddr);
 
   // If the argument is smaller than a slot, and this is a big-endian
   // target, the argument will be right-adjusted in its slot.
   if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian()) {
     Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);

 ///   Each argument will be allocated to a multiple of this number of
 ///   slots, and all the slots will be aligned to this value.
 /// \param AllowHigherAlign - The slot alignment is not a cap;
 ///   an argument type with an alignment greater than the slot size
 ///   will be emitted on a higher-alignment address, potentially
 ///   leaving one or more empty slots behind as padding.
 static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
                                 QualType ValueTy, bool IsIndirect,
                                 std::pair<CharUnits, CharUnits> ValueInfo,
                                 CharUnits SlotSizeAndAlign,
                                 bool AllowHigherAlign) {
   // The size and alignment of the value that was passed directly.
   CharUnits DirectSize, DirectAlign;
   if (IsIndirect) {
     DirectSize = CGF.getPointerSize();
     DirectAlign = CGF.getPointerAlign();
   } else {
if (Align > 8) {
     llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align);
     overflow_arg_area =
       CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
                                  overflow_arg_area->getType(),
                                  "overflow_arg_area.align");
   }
 
   // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
   llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
   llvm::Value *Res =
     CGF.Builder.CreateBitCast(overflow_arg_area,
                               llvm::PointerType::getUnqual(LTy));
 
   // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
   // l->overflow_arg_area + sizeof(type).
   // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
   // an 8 byte boundary.
Address MemAddr = Address::invalid();
     } else {
       Size = CGF.getPointerSize();
     }
 
     Address OverflowAreaAddr =
       Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
     Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr),
                          OverflowAreaAlign);
+    // Round up address of argument to alignment
+    llvm::Value *overflow_arg_area = OverflowArea.getPointer();
+    uint32_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity();
+    if (Align > 4) {
+      // overflow_arg_area = (overflow_arg_area + align - 1) & -align;
+      llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, Align - 1);
+      overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset);
+      llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area,
+                                                      CGF.Int32Ty);
+      llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -(uint32_t)Align);
+      overflow_arg_area =
+        CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
+                                   overflow_arg_area->getType(),
+                                   "overflow_arg_area.align");
+    }
  
-    // The current address is the address of the varargs element.
-    // FIXME: do we not need to round up to alignment?
+    OverflowArea = Address(overflow_arg_area, CharUnits::fromQuantity(Align));
     MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
 
     // Increase the overflow area.
     OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
     Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
     CGF.EmitBranch(Cont);
   }
 

test/CodeGen/ppc-varargs-struct.c

 // CHECK-PPC-NEXT:  [[REGADDR:%.+]] = bitcast i8* [[RAW_REGADDR]] to %struct.x**
 // CHECK-PPC-NEXT:  [[USED_GPR:%[0-9]+]] = add i8 [[GPR]], 1
 // CHECK-PPC-NEXT:  store i8 [[USED_GPR]], i8* [[GPRPTR]], align 4
 // CHECK-PPC-NEXT:  br label %[[CONT:[a-z0-9]+]]
 //
 // CHECK-PPC:[[USING_OVERFLOW]]
 // CHECK-PPC-NEXT:  [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3
 // CHECK-PPC-NEXT:  [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4
-// CHECK-PPC-NEXT:  [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x**
-// CHECK-PPC-NEXT:  [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4
-// CHECK-PPC-NEXT:  store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]]
+// CHECK-PPC-NEXT:  %{{[0-9]+}} = getelementptr i8, i8* %{{[0-9]+}}, i32 7
+// CHECK-PPC-NEXT:  %{{[0-9]+}} = ptrtoint i8* %{{[0-9]+}} to i32
+// CHECK-PPC-NEXT:  %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8
+// CHECK-PPC-NEXT:  %overflow_arg_area.align = inttoptr i32 %{{[0-9]+}} to i8*
+// CHECK-PPC-NEXT:  [[MEMADDR:%.+]] = bitcast i8* %overflow_arg_area.align to %struct.x**
+// CHECK-PPC-NEXT:  [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %overflow_arg_area.align, i32 4
+// CHECK-PPC-NEXT:  store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4
 // CHECK-PPC-NEXT:  br label %[[CONT]]
 //
 // CHECK-PPC:[[CONT]]
 // CHECK-PPC-NEXT:  [[VAARG_ADDR:%[a-z.0-9]+]] = phi %struct.x** [ [[REGADDR]], %[[USING_REGS]] ], [ [[MEMADDR]], %[[USING_OVERFLOW]] ]
 // CHECK-PPC-NEXT:  [[AGGR:%[a-z0-9]+]] = load %struct.x*, %struct.x** [[VAARG_ADDR]]
 // CHECK-PPC-NEXT:  [[DEST:%[0-9]+]] = bitcast %struct.x* %t to i8*
 // CHECK-PPC-NEXT:  [[SRC:%.+]] = bitcast %struct.x* [[AGGR]] to i8*
 // CHECK-PPC-NEXT:  call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[DEST]], i8* [[SRC]], i32 16, i32 8, i1 false)