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[mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocation
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Authored by zoran.jovanovic on Nov 19 2015, 8:06 AM.

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zoran.jovanovic retitled this revision from to [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocation.
zoran.jovanovic updated this object.
zoran.jovanovic added a subscriber: llvm-commits.
dsanders accepted this revision.Dec 7 2015, 6:51 AM
dsanders edited edge metadata.

LGTM with a nit.

include/llvm/Support/ELFRelocs/Mips.def
111 ↗(On Diff #40650)

This one ought to be ..._S1 and adjustFixupValue(), etc. should be corrected to match. Could you fix this in a separate patch?

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
168 ↗(On Diff #40650)

We should also 'return 0' as per the other cases.

This revision is now accepted and ready to land.Dec 7 2015, 6:51 AM
dsanders added inline comments.Dec 7 2015, 7:10 AM
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
370 ↗(On Diff #40650)

Is it still -4 when we're shifting by 1 instead of 2?

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
370 ↗(On Diff #40650)

If my understanding is correct -4 is defined only by the size of current instruction (balc and bc in this case) and it is 4 bytes:
"... is added to the address of the instruction following the
branch (not the branch itself), to form a PC-relative effective target address"
" Operation:
target_offset <- sign_extend( offset || 01 )
GPR[31] <- PC+4
PC <- PC+4 + sign_extend(target_offset)"

dsanders added inline comments.Dec 17 2015, 6:40 AM
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
370 ↗(On Diff #40650)

That makes sense. Thanks.

This revision was automatically updated to reflect the committed changes.