Handle ARMv7K as an alias, instead of fake architecture (NFC)

[tyomitch]

Summary

This follows D14577 to treat ARMv7K as an alias for ARMv7-A,
instead of an architecture in its own right.

[rengolin]

lib/Target/ARM/ARMSubtarget.cpp

156

I strongly oppose to going back to string parsing all over the place.

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

1053

Idem.

[tyomitch]

Thanks Renato, I see your point.

How about this?

[t.p.northover]

I'm not really sure about this. To the extent that the arch part of the triple means anything on MachO targets, it's a CPU choice (possibly with accompanying ABI upgrades, like x86_64h).

Defaulting watchOS to Cortex-A7 achieves the right thing on existing triples, but for what seem like dodgy reasons to me.

lib/Support/Triple.cpp

1376

tvOS probably ought to default to "cyclone" if anything.

[tyomitch]

Thanks Tim! One more attempt...

[t.p.northover]

That's probably OK for now, as far as I'm concerned. If and when we ever care about v7k outside watchOS we can decide what to do about it.

[tyomitch]

In D14757#293002, @t.p.northover wrote:

That's probably OK for now, as far as I'm concerned. If and when we ever care about v7k outside watchOS we can decide what to do about it.

Thanks Tim!
Do you have any comments on D14755 (the ARMv6J patch)? @rengolin suggested you took a look...

include/llvm/ADT/Triple.h

enum SubArchType {
     NoSubArch,
 
     ARMSubArch_v8_1a,
     ARMSubArch_v8,
     ARMSubArch_v7,
     ARMSubArch_v7em,
     ARMSubArch_v7m,
     ARMSubArch_v7s,
-    ARMSubArch_v7k,
     ARMSubArch_v6,
     ARMSubArch_v6m,
     ARMSubArch_v6k,
     ARMSubArch_v6t2,
     ARMSubArch_v5,
     ARMSubArch_v5te,
     ARMSubArch_v4t,
 

include/llvm/Support/ARMTargetParser.def

 ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, AEK_NONE)
 ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, AEK_NONE)
 ARM_ARCH("xscale", AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, AEK_NONE)
 ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7,
           FK_NEON_VFPV4, AEK_DSP)
-ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7,
-          FK_NONE, AEK_DSP)
 #undef ARM_ARCH
 
 #ifndef ARM_ARCH_EXT_NAME
 #define ARM_ARCH_EXT_NAME(NAME, ID)
 #endif
 ARM_ARCH_EXT_NAME("invalid", AEK_INVALID)
 ARM_ARCH_EXT_NAME("none", AEK_NONE)
 ARM_ARCH_EXT_NAME("crc", AEK_CRC)

 ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
 ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
 ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
 // Non-standard Arch names.
 ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, AEK_NONE)
 ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, AEK_NONE)
 ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true,
              (AEK_HWDIVARM | AEK_HWDIV))
-ARM_CPU_NAME("cortex-a7", AK_ARMV7K, FK_NONE, true, AEK_HWDIVARM | AEK_HWDIV)
 // Invalid CPU
 ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, AEK_INVALID)
 #undef ARM_CPU_NAME

lib/Support/TargetParser.cpp

 static StringRef getArchSynonym(StringRef Arch) {
   return StringSwitch<StringRef>(Arch)
       .Case("v5", "v5t")
       .Case("v5e", "v5te")
       .Case("v6j", "v6")
       .Case("v6hl", "v6k")
       .Cases("v6m", "v6sm", "v6s-m", "v6-m")
       .Cases("v6z", "v6zk", "v6kz")
-      .Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
+      .Cases("v7", "v7a", "v7hl", "v7k", "v7l", "v7-a")
       .Case("v7r", "v7-r")
       .Case("v7m", "v7-m")
       .Case("v7em", "v7e-m")
       .Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
       .Case("v8.1a", "v8.1-a")
       .Default(Arch);
 }
 
unsigned llvm::ARM::parseArchProfile(StringRef Arch) {
   switch (parseArch(Arch)) {
   case ARM::AK_ARMV6M:
   case ARM::AK_ARMV7M:
   case ARM::AK_ARMV7EM:
     return ARM::PK_M;
   case ARM::AK_ARMV7R:
     return ARM::PK_R;
   case ARM::AK_ARMV7A:
-  case ARM::AK_ARMV7K:
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:
     return ARM::PK_A;
   }
   return ARM::PK_INVALID;
 }
 
 // Version number (ex. v7 = 7).
unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
   case ARM::AK_ARMV6KZ:
   case ARM::AK_ARMV6M:
     return 6;
   case ARM::AK_ARMV7A:
   case ARM::AK_ARMV7R:
   case ARM::AK_ARMV7M:
   case ARM::AK_ARMV7S:
   case ARM::AK_ARMV7EM:
-  case ARM::AK_ARMV7K:
     return 7;
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:
     return 8;
   }
   return 0;
 }

lib/Support/Triple.cpp

case ARM::AK_ARMV6KZ:
     return Triple::ARMSubArch_v6k;
   case ARM::AK_ARMV6T2:
     return Triple::ARMSubArch_v6t2;
   case ARM::AK_ARMV6M:
     return Triple::ARMSubArch_v6m;
   case ARM::AK_ARMV7A:
   case ARM::AK_ARMV7R:
     return Triple::ARMSubArch_v7;
-  case ARM::AK_ARMV7K:
-    return Triple::ARMSubArch_v7k;
   case ARM::AK_ARMV7M:
     return Triple::ARMSubArch_v7m;
   case ARM::AK_ARMV7S:
     return Triple::ARMSubArch_v7s;
   case ARM::AK_ARMV7EM:
     return Triple::ARMSubArch_v7em;
   case ARM::AK_ARMV8A:
     return Triple::ARMSubArch_v8;
StringRef Triple::getARMCPUForArch(StringRef MArch) const {
   case llvm::Triple::FreeBSD:
   case llvm::Triple::NetBSD:
     if (!MArch.empty() && MArch == "v6")
       return "arm1176jzf-s";
     break;
   case llvm::Triple::Win32:
     // FIXME: this is invalid for WindowsCE
     return "cortex-a9";
+  case llvm::Triple::TvOS:
+  case llvm::Triple::WatchOS:
+    return "cortex-a7";
   default:
     break;
   }
 
   if (MArch.empty())
     return StringRef();
 
   StringRef CPU = ARM::getDefaultCPU(MArch);
   if (!CPU.empty())
     return CPU;
 

lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initializeEnvironment() {
   HasCrypto = false;
   HasCRC = false;
   HasZeroCycleZeroing = false;
   StrictAlign = false;
   HasDSP = false;
   UseNaClTrap = false;
   GenLongCalls = false;
   UnsafeFPMath = false;
+  // ARMv7k does not use SjLj exception handling.
   UseSjLjEH = (isTargetDarwin() &&
-               TargetTriple.getSubArch() != Triple::ARMSubArch_v7k);
+               !TargetTriple.getArchName().endswith("v7k"));
 }
 
 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   if (CPUString.empty()) {
     CPUString = "generic";
 
     if (isTargetDarwin()) {
       StringRef ArchName = TargetTriple.getArchName();
       if (ArchName.endswith("v7s"))
         // Default to the Swift CPU when targeting armv7s/thumbv7s.
         CPUString = "swift";
       else if (ArchName.endswith("v7k"))
         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
-        // ARMv7k does not use SjLj exception handling.
         CPUString = "cortex-a7";
     }
   }
 
   // Insert the architecture feature derived from the target triple into the
   // feature string. This is important for setting features that are implied
   // based on the architecture version.
   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

case ARM::AK_ARMV5TEJ:
     return MachO::CPU_SUBTYPE_ARM_V5;
   case ARM::AK_ARMV6:
   case ARM::AK_ARMV6K:
     return MachO::CPU_SUBTYPE_ARM_V6;
   case ARM::AK_ARMV7A:
     return MachO::CPU_SUBTYPE_ARM_V7;
   case ARM::AK_ARMV7S:
     return MachO::CPU_SUBTYPE_ARM_V7S;
-  case ARM::AK_ARMV7K:
-    return MachO::CPU_SUBTYPE_ARM_V7K;
   case ARM::AK_ARMV6M:
     return MachO::CPU_SUBTYPE_ARM_V6M;
   case ARM::AK_ARMV7M:
     return MachO::CPU_SUBTYPE_ARM_V7M;
   case ARM::AK_ARMV7EM:
     return MachO::CPU_SUBTYPE_ARM_V7EM;
   }
 }
 
 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
                                         const Triple &TheTriple, StringRef CPU,
                                         bool isLittle) {
   switch (TheTriple.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
   case Triple::MachO: {
-    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
+    StringRef Arch = TheTriple.getArchName();
+    MachO::CPUSubTypeARM CS = (Arch == "armv7k" || Arch == "thumbv7k")
+                              ? MachO::CPU_SUBTYPE_ARM_V7K
+                              : getMachOSubTypeFromArch(Arch);
     return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS);
   }
   case Triple::COFF:
     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
     return new ARMAsmBackendWinCOFF(T, TheTriple);
   case Triple::ELF:
     assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
     uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());