For IR like:
%alloca = alloca ... dbg.value(%alloca, !myvar, OP_deref(<other_ops>))
GlobalISel lowers it to MIR:
%some_reg = G_FRAME_INDEX <stack_slot> DBG_VALUE %some_reg, !myvar, OP_deref(<other_ops>)
In other words, if the value of !myvar can be obtained by
dereferencing an alloca, in MIR we say that the _location_ of a variable
is obtained by dereferencing register %some_reg (plus some
<other_ops>).
We can instead remove the use of %some_reg: the location of !myvar
_is_ <stack_slot> (plus some <other_ops>). This patch implements
this transformation, which improves debug information handling in O0, as
these registers hardly ever survive register allocation.
A note about testing: similar to what was done in D76934
(f24e2e9eebde4b7a1d), this patch exposed a bug in the Builder class when
using -debug, where we tried to print an incomplete instruction. The
changes in MachineIRBuilder.cpp address that.
Can you update the test to not hardcode !17, !18?