[NFC]Pre-commit test case

[mingmingl]

Summary

Pre-commit test cases to show missed icmp-opt with flag-setting ALUs

[mingmingl]

Run auto-updater on one of existing tests

[mingmingl]

remove empty lines

[mingmingl]

add RUN line for new test

[mingmingl]

arc land <feature-branch> detects this pre-commit test case is not reviewed so decided to send this out as well. Thanks!

[dmgreen]

LGTM. You can land tests like this without review.

[mingmingl]

In D146754#4224991, @dmgreen wrote:

LGTM. You can land tests like this without review.

Got it, will do it if the test case is simple enough next time!

llvm/test/CodeGen/AArch64/aarch64-icmp-opt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -O3 -mtriple=aarch64 %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define i32 @sub_icmp_i32(i32 %0, i32 %1) {
+; CHECK-LABEL: sub_icmp_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub w0, w0, w1
+; CHECK-NEXT:    cmp w0, #0
+; CHECK-NEXT:    b.le .LBB0_2
+; CHECK-NEXT:  // %bb.1:
+; CHECK-NEXT:    b _Z2f2i
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    b _Z2f1i
+  %3 = sub nsw i32 %0, %1
+  %4 = icmp slt i32 %3, 1
+  br i1 %4, label %5, label %7
+
+5:
+  %6 = tail call i32 @_Z2f1i(i32 %3)
+  br label %9
+
+7:
+  %8 = tail call i32 @_Z2f2i(i32 %3)
+  br label %9
+
+9:
+  %10 = phi i32 [ %6, %5 ], [ %8, %7 ]
+  ret i32 %10
+}
+
+
+
+define i64 @sub_icmp_i64(i64 %0, i64 %1) {
+; CHECK-LABEL: sub_icmp_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub x0, x0, x1
+; CHECK-NEXT:    cmp x0, #0
+; CHECK-NEXT:    b.le .LBB1_2
+; CHECK-NEXT:  // %bb.1:
+; CHECK-NEXT:    b _Z2f4l
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    b _Z2f3l
+  %3 = sub nsw i64 %0, %1
+  %4 = icmp slt i64 %3, 1
+  br i1 %4, label %5, label %7
+
+5:
+  %6 = tail call i64 @_Z2f3l(i64 %3)
+  br label %9
+
+7:
+  %8 = tail call i64 @_Z2f4l(i64 %3)
+  br label %9
+
+9:
+  %10 = phi i64 [ %6, %5 ], [ %8, %7 ]
+  ret i64 %10
+}
+
+define i64 @add_i64(i64 %0, i64 %1) {
+; CHECK-LABEL: add_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add x0, x1, x0
+; CHECK-NEXT:    cmp x0, #0
+; CHECK-NEXT:    b.le .LBB2_2
+; CHECK-NEXT:  // %bb.1:
+; CHECK-NEXT:    b _Z2f4l
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    b _Z2f3l
+  %3 = add nsw i64 %1, %0
+  %4 = icmp slt i64 %3, 1
+  br i1 %4, label %5, label %7
+
+5:
+  %6 = tail call i64 @_Z2f3l(i64 %3)
+  br label %9
+
+7:
+  %8 = tail call i64 @_Z2f4l(i64 %3)
+  br label %9
+
+9:
+  %10 = phi i64 [ %6, %5 ], [ %8, %7 ]
+  ret i64 %10
+}
+
+define i32 @add_i32(i32 %0, i32 %1) {
+; CHECK-LABEL: add_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add w0, w1, w0
+; CHECK-NEXT:    cmp w0, #0
+; CHECK-NEXT:    b.le .LBB3_2
+; CHECK-NEXT:  // %bb.1:
+; CHECK-NEXT:    b _Z2f4l
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    b _Z2f3l
+  %3 = add nsw i32 %1, %0
+  %4 = icmp slt i32 %3, 1
+  br i1 %4, label %5, label %7
+
+5:
+  %6 = tail call i32 @_Z2f3l(i32 %3)
+  br label %9
+
+7:
+  %8 = tail call i32 @_Z2f4l(i32 %3)
+  br label %9
+
+9:
+  %10 = phi i32 [ %6, %5 ], [ %8, %7 ]
+  ret i32 %10
+}
+
+
+
+declare i32 @_Z2f1i(i32)
+declare i32 @_Z2f2i(i32)
+declare i64 @_Z2f3l(i64)
+declare i64 @_Z2f4l(i64)

llvm/test/CodeGen/AArch64/arm64-csel.ll

entry:
   %neg = xor i32 -1, %b
   %cond = select i1 %tobool, i32 %neg, i32 %a
   ret i32 %cond
 }
 
 define i32 @foo9(i32 %v) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo9:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #4
+; CHECK-NEXT:    mov w8, #4 // =0x4
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    cinv w0, w8, eq
 ; CHECK-NEXT:    ret
 entry:
   %tobool = icmp ne i32 %v, 0
   %cond = select i1 %tobool, i32 4, i32 -5
   ret i32 %cond
 }
 
 define i64 @foo10(i64 %v) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo10:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #4
+; CHECK-NEXT:    mov w8, #4 // =0x4
 ; CHECK-NEXT:    cmp x0, #0
 ; CHECK-NEXT:    cinv x0, x8, eq
 ; CHECK-NEXT:    ret
 entry:
   %tobool = icmp ne i64 %v, 0
   %cond = select i1 %tobool, i64 4, i64 -5
   ret i64 %cond
 }
 
 define i32 @foo11(i32 %v) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo11:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #4
+; CHECK-NEXT:    mov w8, #4 // =0x4
 ; CHECK-NEXT:    cmp w0, #0
 ; CHECK-NEXT:    cneg w0, w8, eq
 ; CHECK-NEXT:    ret
 entry:
   %tobool = icmp ne i32 %v, 0
   %cond = select i1 %tobool, i32 4, i32 -4
   ret i32 %cond
 }
 
 define i64 @foo12(i64 %v) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo12:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #4
+; CHECK-NEXT:    mov w8, #4 // =0x4
 ; CHECK-NEXT:    cmp x0, #0
 ; CHECK-NEXT:    cneg x0, x8, eq
 ; CHECK-NEXT:    ret
 entry:
   %tobool = icmp ne i64 %v, 0
   %cond = select i1 %tobool, i64 4, i64 -4
   ret i64 %cond
 }
entry:
   %cond = select i1 %tobool, i64 %sub, i64 %a
   ret i64 %cond
 }
 
 define i32 @foo15(i32 %a, i32 %b) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo15:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    cinc w0, w8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i32 %a, %b
   %. = select i1 %cmp, i32 2, i32 1
   ret i32 %.
 }
 
 define i32 @foo16(i32 %a, i32 %b) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    cinc w0, w8, le
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i32 %a, %b
   %. = select i1 %cmp, i32 1, i32 2
   ret i32 %.
 }
 
 define i64 @foo17(i64 %a, i64 %b) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo17:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, x1
-; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    cinc x0, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, %b
   %. = select i1 %cmp, i64 2, i64 1
   ret i64 %.
 }
 
 define i64 @foo18(i64 %a, i64 %b) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo18:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, x1
-; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    cinc x0, x8, le
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, %b
   %. = select i1 %cmp, i64 1, i64 2
   ret i64 %.
 }
 
 ; Regression test for TrueVal + 1 overflow
 define i64 @foo18_overflow1(i64 %a, i64 %b) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo18_overflow1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, x1
-; CHECK-NEXT:    mov x8, #9223372036854775807
+; CHECK-NEXT:    mov x8, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    csel x0, x8, xzr, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, %b
   %. = select i1 %cmp, i64 9223372036854775807, i64 0
   ret i64 %.
 }
 
 ; Regression test for FalseVal + 1 overflow
 define i64 @foo18_overflow2(i64 %a, i64 %b) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo18_overflow2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, x1
-; CHECK-NEXT:    mov x8, #9223372036854775807
+; CHECK-NEXT:    mov x8, #9223372036854775807 // =0x7fffffffffffffff
 ; CHECK-NEXT:    csel x0, xzr, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, %b
   %. = select i1 %cmp, i64 0, i64 9223372036854775807
   ret i64 %.
 }
 
 ; Regression test for FalseVal - TrueVal overflow
 define i64 @foo18_overflow3(i1 %cmp) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo18_overflow3:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov x8, #-9223372036854775808 
-; CHECK-NEXT:    tst w0, #0x1 
-; CHECK-NEXT:    csel x0, x8, xzr, ne 
+; CHECK-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    csel x0, x8, xzr, ne
 ; CHECK-NEXT:    ret
 entry:
   %. = select i1 %cmp, i64 -9223372036854775808, i64 0
   ret i64 %.
 }
 
 ; Regression test for TrueVal - FalseVal overflow
 define i64 @foo18_overflow4(i1 %cmp) nounwind readnone optsize ssp {
 ; CHECK-LABEL: foo18_overflow4:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov x8, #-9223372036854775808 
-; CHECK-NEXT:    tst w0, #0x1 
-; CHECK-NEXT:    csel x0, xzr, x8, ne 
+; CHECK-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    csel x0, xzr, x8, ne
 ; CHECK-NEXT:    ret
 entry:
   %. = select i1 %cmp, i64 0, i64 -9223372036854775808
   ret i64 %.
 }
 
 define i64 @foo19(i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: foo19:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, x1
 ; CHECK-NEXT:    cinc x0, x2, lo
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp ult i64 %a, %b
   %inc = zext i1 %cmp to i64
   %inc.c = add i64 %inc, %c
   ret i64 %inc.c
 }
 
 define i32 @foo20(i32 %x) {
 ; CHECK-LABEL: foo20:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #6
+; CHECK-NEXT:    mov w8, #6 // =0x6
 ; CHECK-NEXT:    cmp w0, #5
 ; CHECK-NEXT:    csinc w0, w8, wzr, eq
 ; CHECK-NEXT:    ret
   %cmp = icmp eq i32 %x, 5
   %res = select i1 %cmp, i32 6, i32 1
   ret i32 %res
 }
 
 define i64 @foo21(i64 %x) {
 ; CHECK-LABEL: foo21:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #6
+; CHECK-NEXT:    mov w8, #6 // =0x6
 ; CHECK-NEXT:    cmp x0, #5
 ; CHECK-NEXT:    csinc x0, x8, xzr, eq
 ; CHECK-NEXT:    ret
   %cmp = icmp eq i64 %x, 5
   %res = select i1 %cmp, i64 6, i64 1
   ret i64 %res
 }
 
 define i32 @foo22(i32 %x) {
 ; CHECK-LABEL: foo22:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #6
+; CHECK-NEXT:    mov w8, #6 // =0x6
 ; CHECK-NEXT:    cmp w0, #5
 ; CHECK-NEXT:    csinc w0, w8, wzr, ne
 ; CHECK-NEXT:    ret
   %cmp = icmp eq i32 %x, 5
   %res = select i1 %cmp, i32 1, i32 6
   ret i32 %res
 }
 
 define i64 @foo23(i64 %x) {
 ; CHECK-LABEL: foo23:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #6
+; CHECK-NEXT:    mov w8, #6 // =0x6
 ; CHECK-NEXT:    cmp x0, #5
 ; CHECK-NEXT:    csinc x0, x8, xzr, ne
 ; CHECK-NEXT:    ret
   %cmp = icmp eq i64 %x, 5
   %res = select i1 %cmp, i64 1, i64 6
   ret i64 %res
 }