[ARM] Match VABDL from log2 shuffles.

[• chatur01]

Summary

The patterns are pretty gross, but I couldn't see a more concise way of doing it.

The bitcasts are needed for the v2i64 and v8i16 cases because they're type-legalized to v4i32.

[• chatur01]

Made the patterns a bit nicer with the help of a PatFrag

[rengolin]

Hi Charlie,

It seems that this pattern is only valid if the original types were unsigned to begin with, which is a fair assumption, but Is there any guarantee that the zero-extend is exclusively used in unsigned values, or are there some legalization patterns that could zero extend for other reasons?

For instance, this arithmetic shift-right is used instead of logical, in assumed unsigned values, because negative numbers will set the most significant bits of the double-size result registers, and you want to clear them out with the XOR.

Funny, though, it also works when both values are negative, but not when they're of different signs, because you end up with a FF00 or 00FF pattern in the intermediate results.

cheers,
--renato

lib/Target/ARM/ARMInstrNEON.td

                         "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
 
 //   VABDL    : Vector Absolute Difference Long (Q = | D - D |)
 defm VABDLs   : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
                                "vabdl", "s", sabsdiff, zext, 1>;
 defm VABDLu   : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
                                "vabdl", "u", uabsdiff, zext, 1>;
 
+def abd_shr :
+    PatFrag<(ops node:$in1, node:$in2, node:$shift),
+            (NEONvshrs (sub (zext node:$in1),
+                            (zext node:$in2)), (i32 $shift))>;
+
+def : Pat<(xor (v4i32 (bitconvert (v8i16 (abd_shr (v8i8 DPR:$opA), (v8i8 DPR:$opB), 15)))),
+               (v4i32 (bitconvert (v8i16 (add (sub (zext (v8i8 DPR:$opA)),
+                                                   (zext (v8i8 DPR:$opB))),
+                                              (v8i16 (abd_shr (v8i8 DPR:$opA), (v8i8 DPR:$opB), 15))))))),
+          (VABDLuv8i16 DPR:$opA, DPR:$opB)>;
+
+def : Pat<(xor (v4i32 (abd_shr (v4i16 DPR:$opA), (v4i16 DPR:$opB), 31)),
+               (v4i32 (add (sub (zext (v4i16 DPR:$opA)),
+                                (zext (v4i16 DPR:$opB))),
+                           (abd_shr (v4i16 DPR:$opA), (v4i16 DPR:$opB), 31)))),
+          (VABDLuv4i32 DPR:$opA, DPR:$opB)>;
+
+def : Pat<(xor (v4i32 (bitconvert (v2i64 (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))),
+               (v4i32 (bitconvert (v2i64 (add (sub (zext (v2i32 DPR:$opA)),
+                                                   (zext (v2i32 DPR:$opB))),
+                                         (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))))),
+          (VABDLuv2i64 DPR:$opA, DPR:$opB)>;
+
 //   VABA     : Vector Absolute Difference and Accumulate
 defm VABAs    : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
                              "vaba", "s", sabsdiff, add>;
 defm VABAu    : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
                              "vaba", "u", uabsdiff, add>;
 
 //   VABAL    : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
 defm VABALs   : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,

test/CodeGen/ARM/neon_vabs.ll

 define <2 x i32> @test10(<2 x i32> %a) nounwind {
 ; CHECK-LABEL: test10:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sle <2 x i32> %a, zeroinitializer
         %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a
         ret <2 x i32> %abs
 }
+
+;; Check that absdiff patterns as emitted by log2 shuffles are
+;; matched by VABD.
+
+define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind {
+; CHECK-LABEL: test11:
+; CHECK: vabdl.u16 q
+        %zext1 = zext <4 x i16> %a to <4 x i32>
+        %zext2 = zext <4 x i16> %b to <4 x i32>
+        %diff = sub <4 x i32> %zext1, %zext2
+        %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31>
+        %add1 = add <4 x i32> %shift1, %diff
+        %res = xor <4 x i32> %shift1, %add1
+        ret <4 x i32> %res
+}
+define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind {
+; CHECK-LABEL: test12:
+; CHECK: vabdl.u8 q
+        %zext1 = zext <8 x i8> %a to <8 x i16>
+        %zext2 = zext <8 x i8> %b to <8 x i16>
+        %diff = sub <8 x i16> %zext1, %zext2
+        %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+        %add1 = add <8 x i16> %shift1, %diff
+        %res = xor <8 x i16> %shift1, %add1
+        ret <8 x i16> %res
+}
+
+define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind {
+; CHECK-LABEL: test13:
+; CHECK: vabdl.u32 q
+        %zext1 = zext <2 x i32> %a to <2 x i64>
+        %zext2 = zext <2 x i32> %b to <2 x i64>
+        %diff = sub <2 x i64> %zext1, %zext2
+        %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63>
+        %add1 = add <2 x i64> %shift1, %diff
+        %res = xor <2 x i64> %shift1, %add1
+        ret <2 x i64> %res
+}