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Differential D146636

Precommit tests for #60690
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Authored by junaire on Mar 22 2023, 8:59 AM.

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RKSimon
junaire
Commits
rG3ca6e69b6efe: Precommit tests for #60690
Summary

Signed-off-by: Jun Zhang <jun@junz.org>

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Event Timeline

junaire created this revision.Mar 22 2023, 8:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2023, 8:59 AM
junaire requested review of this revision.Mar 22 2023, 8:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2023, 8:59 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
junaire added a child revision: D146637: [InstCombine] Try to recognize bswap pattern when calling funnel shifts.Mar 22 2023, 9:00 AM
Harbormaster completed remote builds in B221038: Diff 507379.Mar 22 2023, 10:11 AM
RKSimon added inline comments.Mar 22 2023, 11:20 AM
llvm/test/Transforms/InstCombine/bswap.ll
933

(style) Its always useful to tag the test case with the relevant bug (avoids having to git blame the file) - either call the test PR60690 or add a comment above mentioning it

junaire updated this revision to Diff 507605.Mar 22 2023, 10:11 PM
  1. Use more meaningful name for the tests
  2. Add fshr case
Harbormaster completed remote builds in B221218: Diff 507605.Mar 22 2023, 11:00 PM
junaire accepted this revision.Mar 23 2023, 7:51 PM

Since D146637 is approved, let's just land this as well. :)

This revision is now accepted and ready to land.Mar 23 2023, 7:51 PM
This revision was landed with ongoing or failed builds.Mar 23 2023, 7:51 PM
Closed by commit rG3ca6e69b6efe: Precommit tests for #60690 (authored by junaire). · Explain Why
This revision was automatically updated to reflect the committed changes.
junaire added a commit: rG3ca6e69b6efe: Precommit tests for #60690.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
60 lines

Diff 507950

llvm/test/Transforms/InstCombine/bswap.ll

Show First 20 Lines • Show All 923 Lines • ▼ Show 20 Lines
; ;
%t2 = and i64 %t0, 72057594037927935 %t2 = and i64 %t0, 72057594037927935
%t3 = call i64 @llvm.bswap.i64(i64 %t2) %t3 = call i64 @llvm.bswap.i64(i64 %t2)
%t4 = lshr i64 %t0, 56 %t4 = lshr i64 %t0, 56
%t5 = or i64 %t3, %t4 %t5 = or i64 %t3, %t4
%t6 = trunc i64 %t5 to i32 %t6 = trunc i64 %t5 to i32
ret i32 %t6 ret i32 %t6
} }
define i64 @PR60690_call_fshl(i64 %result) {
RKSimonUnsubmitted
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(style) Its always useful to tag the test case with the relevant bug (avoids having to git blame the file) - either call the test PR60690 or add a comment above mentioning it

RKSimon: (style) Its always useful to tag the test case with the relevant bug (avoids having to git…
; CHECK-LABEL: @PR60690_call_fshl(
; CHECK-NEXT: [[AND_I:%.*]] = lshr i64 [[RESULT:%.*]], 8
; CHECK-NEXT: [[SHR_I:%.*]] = and i64 [[AND_I]], 71777214294589695
; CHECK-NEXT: [[AND1_I:%.*]] = shl i64 [[RESULT]], 8
; CHECK-NEXT: [[SHL_I:%.*]] = and i64 [[AND1_I]], -71777214294589696
; CHECK-NEXT: [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]
; CHECK-NEXT: [[AND_I7:%.*]] = shl i64 [[OR_I]], 16
; CHECK-NEXT: [[SHL_I8:%.*]] = and i64 [[AND_I7]], -281470681808896
; CHECK-NEXT: [[AND1_I9:%.*]] = lshr i64 [[OR_I]], 16
; CHECK-NEXT: [[SHR_I10:%.*]] = and i64 [[AND1_I9]], 281470681808895
; CHECK-NEXT: [[OR_I11:%.*]] = or i64 [[SHL_I8]], [[SHR_I10]]
; CHECK-NEXT: [[OR_I12:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[OR_I11]], i64 [[OR_I11]], i64 32)
; CHECK-NEXT: ret i64 [[OR_I12]]
;
%and.i = lshr i64 %result, 8
%shr.i = and i64 %and.i, 71777214294589695
%and1.i = shl i64 %result, 8
%shl.i = and i64 %and1.i, -71777214294589696
%or.i = or i64 %shr.i, %shl.i
%and.i7 = shl i64 %or.i, 16
%shl.i8 = and i64 %and.i7, -281470681808896
%and1.i9 = lshr i64 %or.i, 16
%shr.i10 = and i64 %and1.i9, 281470681808895
%or.i11 = or i64 %shl.i8, %shr.i10
%or.i12 = tail call i64 @llvm.fshl.i64(i64 %or.i11, i64 %or.i11, i64 32)
ret i64 %or.i12
}
declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @PR60690_call_fshr(i64 %result) {
; CHECK-LABEL: @PR60690_call_fshr(
; CHECK-NEXT: [[AND_I:%.*]] = lshr i64 [[RESULT:%.*]], 8
; CHECK-NEXT: [[SHR_I:%.*]] = and i64 [[AND_I]], 71777214294589695
; CHECK-NEXT: [[AND1_I:%.*]] = shl i64 [[RESULT]], 8
; CHECK-NEXT: [[SHL_I:%.*]] = and i64 [[AND1_I]], -71777214294589696
; CHECK-NEXT: [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]
; CHECK-NEXT: [[AND_I7:%.*]] = shl i64 [[OR_I]], 16
; CHECK-NEXT: [[SHL_I8:%.*]] = and i64 [[AND_I7]], -281470681808896
; CHECK-NEXT: [[AND1_I9:%.*]] = lshr i64 [[OR_I]], 16
; CHECK-NEXT: [[SHR_I10:%.*]] = and i64 [[AND1_I9]], 281470681808895
; CHECK-NEXT: [[OR_I11:%.*]] = or i64 [[SHL_I8]], [[SHR_I10]]
; CHECK-NEXT: [[OR_I12:%.*]] = call i64 @llvm.fshl.i64(i64 [[OR_I11]], i64 [[OR_I11]], i64 32)
; CHECK-NEXT: ret i64 [[OR_I12]]
;
%and.i = lshr i64 %result, 8
%shr.i = and i64 %and.i, 71777214294589695
%and1.i = shl i64 %result, 8
%shl.i = and i64 %and1.i, -71777214294589696
%or.i = or i64 %shr.i, %shl.i
%and.i7 = shl i64 %or.i, 16
%shl.i8 = and i64 %and.i7, -281470681808896
%and1.i9 = lshr i64 %or.i, 16
%shr.i10 = and i64 %and1.i9, 281470681808895
%or.i11 = or i64 %shl.i8, %shr.i10
%or.i12 = tail call i64 @llvm.fshr.i64(i64 %or.i11, i64 %or.i11, i64 32)
ret i64 %or.i12
}
declare i64 @llvm.fshr.i64(i64, i64, i64)