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Differential D145627

[test] Remove occurences of br undef in CodeGen/ARM and CodeGen/AVR tests
Needs RevisionPublic

Authored by kritgpt on Mar 8 2023, 4:17 PM.

Details

Reviewers
nlopes
Summary

This patch removes br undef as suggested by https://discourse.llvm.org/t/please-dont-use-br-undef-in-tests-aka-please-avoid-test-cases-with-ub/63115. Script used: https://gist.github.com/kritgpt/69bfc7ef78e1784716c693d531a58adf.

Diff Detail

Unit TestsFailed

TimeTest
60 msx64 debian > LLVM.CodeGen/ARM::2009-08-15-RegScavenger-EarlyClobber.ll
80 msx64 debian > LLVM.CodeGen/ARM::2011-12-14-machine-sink.ll
70 msx64 debian > LLVM.CodeGen/ARM::2013-07-29-vector-or-combine.ll
120 msx64 debian > LLVM.CodeGen/ARM::arm-shrink-wrapping.ll
80 msx64 debian > LLVM.CodeGen/ARM::i1.ll
View Full Test Results (12 Failed)

Event Timeline

kritgpt created this revision.Mar 8 2023, 4:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2023, 4:17 PM
Herald added subscribers: Jim, asbirlea, javed.absar and 4 others. · View Herald Transcript
kritgpt requested review of this revision.Mar 8 2023, 4:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2023, 4:17 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
kritgpt added a reviewer: nlopes.Mar 8 2023, 4:18 PM
Harbormaster completed remote builds in B218237: Diff 503553.Mar 8 2023, 5:30 PM
nlopes requested changes to this revision.Mar 9 2023, 12:05 AM

tests failing

This revision now requires changes to proceed.Mar 9 2023, 12:05 AM

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Diff 503553

llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll

; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2
@"\01LC" = external constant [15 x i8] ; <ptr> [#uses=1] @"\01LC" = external constant [15 x i8] ; <ptr> [#uses=1]
declare i32 @printf(ptr nocapture, ...) nounwind declare i32 @printf(ptr nocapture, ...) nounwind
define i32 @main() nounwind { define i32 @main(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10) nounwind {
entry: entry:
br label %bb.i1.i br label %bb.i1.i
bb.i1.i: ; preds = %Cos.exit.i.i, %entry bb.i1.i: ; preds = %Cos.exit.i.i, %entry
br label %bb.i.i.i br label %bb.i.i.i
bb.i.i.i: ; preds = %bb.i.i.i, %bb.i1.i bb.i.i.i: ; preds = %bb.i.i.i, %bb.i1.i
br i1 undef, label %Cos.exit.i.i, label %bb.i.i.i br i1 %c0, label %Cos.exit.i.i, label %bb.i.i.i
Cos.exit.i.i: ; preds = %bb.i.i.i Cos.exit.i.i: ; preds = %bb.i.i.i
br i1 undef, label %bb2.i.i, label %bb.i1.i br i1 %c1, label %bb2.i.i, label %bb.i1.i
bb2.i.i: ; preds = %Cos.exit.i.i bb2.i.i: ; preds = %Cos.exit.i.i
br label %bb3.i.i br label %bb3.i.i
bb3.i.i: ; preds = %bb5.i.i, %bb2.i.i bb3.i.i: ; preds = %bb5.i.i, %bb2.i.i
br label %bb4.i.i br label %bb4.i.i
bb4.i.i: ; preds = %bb4.i.i, %bb3.i.i bb4.i.i: ; preds = %bb4.i.i, %bb3.i.i
br i1 undef, label %bb5.i.i, label %bb4.i.i br i1 %c2, label %bb5.i.i, label %bb4.i.i
bb5.i.i: ; preds = %bb4.i.i bb5.i.i: ; preds = %bb4.i.i
br i1 undef, label %bb.i, label %bb3.i.i br i1 %c3, label %bb.i, label %bb3.i.i
bb.i: ; preds = %bb.i, %bb5.i.i bb.i: ; preds = %bb.i, %bb5.i.i
br i1 undef, label %bb1.outer2.i.i.outer, label %bb.i br i1 %c4, label %bb1.outer2.i.i.outer, label %bb.i
bb1.outer2.i.i.outer: ; preds = %Fft.exit.i, %bb5.i12.i, %bb.i bb1.outer2.i.i.outer: ; preds = %Fft.exit.i, %bb5.i12.i, %bb.i
br label %bb1.outer2.i.i br label %bb1.outer2.i.i
bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer
br label %bb1.i.i br label %bb1.i.i
bb1.i.i: ; preds = %bb1.i.i, %bb1.outer2.i.i bb1.i.i: ; preds = %bb1.i.i, %bb1.outer2.i.i
br i1 undef, label %bb2.i9.i, label %bb1.i.i br i1 %c5, label %bb2.i9.i, label %bb1.i.i
bb2.i9.i: ; preds = %bb1.i.i bb2.i9.i: ; preds = %bb1.i.i
br i1 undef, label %bb4.i11.i, label %bb1.outer2.i.i br i1 %c6, label %bb4.i11.i, label %bb1.outer2.i.i
bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
br i1 undef, label %bb5.i12.i, label %bb4.i11.i br i1 %c7, label %bb5.i12.i, label %bb4.i11.i
bb5.i12.i: ; preds = %bb4.i11.i bb5.i12.i: ; preds = %bb4.i11.i
br i1 undef, label %bb7.i.i, label %bb1.outer2.i.i.outer br i1 %c8, label %bb7.i.i, label %bb1.outer2.i.i.outer
bb7.i.i: ; preds = %bb7.i.i, %bb5.i12.i bb7.i.i: ; preds = %bb7.i.i, %bb5.i12.i
br i1 undef, label %Fft.exit.i, label %bb7.i.i br i1 %c9, label %Fft.exit.i, label %bb7.i.i
Fft.exit.i: ; preds = %bb7.i.i Fft.exit.i: ; preds = %bb7.i.i
br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer br i1 %c10, label %bb5.i, label %bb1.outer2.i.i.outer
bb5.i: ; preds = %Fft.exit.i bb5.i: ; preds = %Fft.exit.i
%0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", double undef, double undef) nounwind ; <i32> [#uses=0] %0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", double undef, double undef) nounwind ; <i32> [#uses=0]
unreachable unreachable
} }

llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll

; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6
%struct.anon = type { i16, i16 } %struct.anon = type { i16, i16 }
%struct.cab_archive = type { i32, i16, i16, i16, i16, i8, ptr, ptr } %struct.cab_archive = type { i32, i16, i16, i16, i16, i8, ptr, ptr }
%struct.cab_file = type { i32, i16, i64, ptr, i32, i32, i32, ptr, ptr, ptr, ptr } %struct.cab_file = type { i32, i16, i64, ptr, i32, i32, i32, ptr, ptr, ptr, ptr }
%struct.cab_folder = type { i16, i16, ptr, i64, ptr } %struct.cab_folder = type { i16, i16, ptr, i64, ptr }
%struct.cab_state = type { ptr, ptr, [38912 x i8], i16, i16, ptr, i16 } %struct.cab_state = type { ptr, ptr, [38912 x i8], i16, i16, ptr, i16 }
%struct.qtm_model = type { i32, i32, ptr } %struct.qtm_model = type { i32, i32, ptr }
%struct.qtm_stream = type { i32, i32, i8, ptr, i32, i32, i32, i16, i16, i16, i8, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], ptr, ptr } %struct.qtm_stream = type { i32, i32, i8, ptr, i32, i32, i32, i16, i16, i16, i8, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], ptr, ptr }
declare fastcc i32 @qtm_read_input(ptr nocapture) nounwind declare fastcc i32 @qtm_read_input(ptr nocapture) nounwind
define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes) nounwind { define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22, i1 %c23, i1 %c24, i1 %c25, i1 %c26, i1 %c27, i1 %c28, i1 %c29, i1 %c30, i1 %c31, i1 %c32, i1 %c33, i1 %c34, i1 %c35, i1 %c36, i1 %c37, i1 %c38, i1 %c39) nounwind {
entry: entry:
br i1 undef, label %bb245, label %bb3 br i1 %c0, label %bb245, label %bb3
bb3: ; preds = %entry bb3: ; preds = %entry
br i1 undef, label %bb5, label %bb4 br i1 %c1, label %bb5, label %bb4
bb4: ; preds = %bb3 bb4: ; preds = %bb3
ret i32 undef ret i32 undef
bb5: ; preds = %bb3 bb5: ; preds = %bb3
br i1 undef, label %bb245, label %bb14 br i1 %c2, label %bb245, label %bb14
bb14: ; preds = %bb5 bb14: ; preds = %bb5
br label %bb238 br label %bb238
bb28: ; preds = %bb215 bb28: ; preds = %bb215
br label %bb31 br label %bb31
bb29: ; preds = %bb31 bb29: ; preds = %bb31
br i1 undef, label %bb31, label %bb32 br i1 %c3, label %bb31, label %bb32
bb31: ; preds = %bb29, %bb28 bb31: ; preds = %bb29, %bb28
br i1 undef, label %bb29, label %bb32 br i1 %c4, label %bb29, label %bb32
bb32: ; preds = %bb31, %bb29 bb32: ; preds = %bb31, %bb29
br label %bb33 br label %bb33
bb33: ; preds = %bb33, %bb32 bb33: ; preds = %bb33, %bb32
br i1 undef, label %bb34, label %bb33 br i1 %c5, label %bb34, label %bb33
bb34: ; preds = %bb33 bb34: ; preds = %bb33
br i1 undef, label %bb35, label %bb36 br i1 %c6, label %bb35, label %bb36
bb35: ; preds = %bb34 bb35: ; preds = %bb34
br label %bb36 br label %bb36
bb36: ; preds = %bb46, %bb35, %bb34 bb36: ; preds = %bb46, %bb35, %bb34
br i1 undef, label %bb40, label %bb37 br i1 %c7, label %bb40, label %bb37
bb37: ; preds = %bb36 bb37: ; preds = %bb36
br i1 undef, label %bb77, label %bb60 br i1 %c8, label %bb77, label %bb60
bb40: ; preds = %bb36 bb40: ; preds = %bb36
br i1 undef, label %bb46, label %bb41 br i1 %c9, label %bb46, label %bb41
bb41: ; preds = %bb40 bb41: ; preds = %bb40
br i1 undef, label %bb45, label %bb42 br i1 %c10, label %bb45, label %bb42
bb42: ; preds = %bb41 bb42: ; preds = %bb41
ret i32 undef ret i32 undef
bb45: ; preds = %bb41 bb45: ; preds = %bb41
br label %bb46 br label %bb46
bb46: ; preds = %bb45, %bb40 bb46: ; preds = %bb45, %bb40
br label %bb36 br label %bb36
bb60: ; preds = %bb60, %bb37 bb60: ; preds = %bb60, %bb37
br label %bb60 br label %bb60
bb77: ; preds = %bb37 bb77: ; preds = %bb37
switch i32 undef, label %bb197 [ switch i32 undef, label %bb197 [
i32 5, label %bb108 i32 5, label %bb108
i32 6, label %bb138 i32 6, label %bb138
] ]
bb108: ; preds = %bb77 bb108: ; preds = %bb77
br label %bb111 br label %bb111
bb109: ; preds = %bb111 bb109: ; preds = %bb111
br i1 undef, label %bb111, label %bb112 br i1 %c11, label %bb111, label %bb112
bb111: ; preds = %bb109, %bb108 bb111: ; preds = %bb109, %bb108
br i1 undef, label %bb109, label %bb112 br i1 %c12, label %bb109, label %bb112
bb112: ; preds = %bb111, %bb109 bb112: ; preds = %bb111, %bb109
br label %bb113 br label %bb113
bb113: ; preds = %bb113, %bb112 bb113: ; preds = %bb113, %bb112
br i1 undef, label %bb114, label %bb113 br i1 %c13, label %bb114, label %bb113
bb114: ; preds = %bb113 bb114: ; preds = %bb113
br i1 undef, label %bb115, label %bb116 br i1 %c14, label %bb115, label %bb116
bb115: ; preds = %bb114 bb115: ; preds = %bb114
br label %bb116 br label %bb116
bb116: ; preds = %bb115, %bb114 bb116: ; preds = %bb115, %bb114
br i1 undef, label %bb120, label %bb117 br i1 %c15, label %bb120, label %bb117
bb117: ; preds = %bb116 bb117: ; preds = %bb116
br label %bb136 br label %bb136
bb120: ; preds = %bb116 bb120: ; preds = %bb116
ret i32 undef ret i32 undef
bb128: ; preds = %bb136 bb128: ; preds = %bb136
br i1 undef, label %bb134, label %bb129 br i1 %c16, label %bb134, label %bb129
bb129: ; preds = %bb128 bb129: ; preds = %bb128
br i1 undef, label %bb133, label %bb130 br i1 %c17, label %bb133, label %bb130
bb130: ; preds = %bb129 bb130: ; preds = %bb129
br i1 undef, label %bb132, label %bb131 br i1 %c18, label %bb132, label %bb131
bb131: ; preds = %bb130 bb131: ; preds = %bb130
ret i32 undef ret i32 undef
bb132: ; preds = %bb130 bb132: ; preds = %bb130
br label %bb133 br label %bb133
bb133: ; preds = %bb132, %bb129 bb133: ; preds = %bb132, %bb129
br label %bb134 br label %bb134
bb134: ; preds = %bb133, %bb128 bb134: ; preds = %bb133, %bb128
br label %bb136 br label %bb136
bb136: ; preds = %bb134, %bb117 bb136: ; preds = %bb134, %bb117
br i1 undef, label %bb198, label %bb128 br i1 %c19, label %bb198, label %bb128
bb138: ; preds = %bb77 bb138: ; preds = %bb77
%0 = trunc i32 undef to i16 ; <i16> [#uses=1] %0 = trunc i32 undef to i16 ; <i16> [#uses=1]
br label %bb141 br label %bb141
bb139: ; preds = %bb141 bb139: ; preds = %bb141
%scevgep441442881 = load i16, ptr undef ; <i16> [#uses=1] %scevgep441442881 = load i16, ptr undef ; <i16> [#uses=1]
%1 = icmp ugt i16 %scevgep441442881, %0 ; <i1> [#uses=1] %1 = icmp ugt i16 %scevgep441442881, %0 ; <i1> [#uses=1]
br i1 %1, label %bb141, label %bb142 br i1 %1, label %bb141, label %bb142
bb141: ; preds = %bb139, %bb138 bb141: ; preds = %bb139, %bb138
br i1 undef, label %bb139, label %bb142 br i1 %c20, label %bb139, label %bb142
bb142: ; preds = %bb141, %bb139 bb142: ; preds = %bb141, %bb139
br label %bb143 br label %bb143
bb143: ; preds = %bb143, %bb142 bb143: ; preds = %bb143, %bb142
br i1 undef, label %bb144, label %bb143 br i1 %c21, label %bb144, label %bb143
bb144: ; preds = %bb143 bb144: ; preds = %bb143
br i1 undef, label %bb145, label %bb146 br i1 %c22, label %bb145, label %bb146
bb145: ; preds = %bb144 bb145: ; preds = %bb144
unreachable unreachable
bb146: ; preds = %bb156, %bb144 bb146: ; preds = %bb156, %bb144
br i1 undef, label %bb150, label %bb147 br i1 %c23, label %bb150, label %bb147
bb147: ; preds = %bb146 bb147: ; preds = %bb146
br i1 undef, label %bb157, label %bb148 br i1 %c24, label %bb157, label %bb148
bb148: ; preds = %bb147 bb148: ; preds = %bb147
br i1 undef, label %bb149, label %bb157 br i1 %c25, label %bb149, label %bb157
bb149: ; preds = %bb148 bb149: ; preds = %bb148
br label %bb150 br label %bb150
bb150: ; preds = %bb149, %bb146 bb150: ; preds = %bb149, %bb146
br i1 undef, label %bb156, label %bb152 br i1 %c26, label %bb156, label %bb152
bb152: ; preds = %bb150 bb152: ; preds = %bb150
unreachable unreachable
bb156: ; preds = %bb150 bb156: ; preds = %bb150
br label %bb146 br label %bb146
bb157: ; preds = %bb148, %bb147 bb157: ; preds = %bb148, %bb147
br i1 undef, label %bb167, label %bb160 br i1 %c27, label %bb167, label %bb160
bb160: ; preds = %bb157 bb160: ; preds = %bb157
ret i32 undef ret i32 undef
bb167: ; preds = %bb157 bb167: ; preds = %bb157
br label %bb170 br label %bb170
bb168: ; preds = %bb170 bb168: ; preds = %bb170
br i1 undef, label %bb170, label %bb171 br i1 %c28, label %bb170, label %bb171
bb170: ; preds = %bb168, %bb167 bb170: ; preds = %bb168, %bb167
br i1 undef, label %bb168, label %bb171 br i1 %c29, label %bb168, label %bb171
bb171: ; preds = %bb170, %bb168 bb171: ; preds = %bb170, %bb168
br label %bb172 br label %bb172
bb172: ; preds = %bb172, %bb171 bb172: ; preds = %bb172, %bb171
br i1 undef, label %bb173, label %bb172 br i1 %c30, label %bb173, label %bb172
bb173: ; preds = %bb172 bb173: ; preds = %bb172
br i1 undef, label %bb174, label %bb175 br i1 %c31, label %bb174, label %bb175
bb174: ; preds = %bb173 bb174: ; preds = %bb173
unreachable unreachable
bb175: ; preds = %bb179, %bb173 bb175: ; preds = %bb179, %bb173
br i1 undef, label %bb179, label %bb176 br i1 %c32, label %bb179, label %bb176
bb176: ; preds = %bb175 bb176: ; preds = %bb175
br i1 undef, label %bb186, label %bb177 br i1 %c33, label %bb186, label %bb177
bb177: ; preds = %bb176 bb177: ; preds = %bb176
br i1 undef, label %bb178, label %bb186 br i1 %c34, label %bb178, label %bb186
bb178: ; preds = %bb177 bb178: ; preds = %bb177
br label %bb179 br label %bb179
bb179: ; preds = %bb178, %bb175 bb179: ; preds = %bb178, %bb175
br label %bb175 br label %bb175
bb186: ; preds = %bb177, %bb176 bb186: ; preds = %bb177, %bb176
br label %bb195 br label %bb195
bb187: ; preds = %bb195 bb187: ; preds = %bb195
br i1 undef, label %bb193, label %bb189 br i1 %c35, label %bb193, label %bb189
bb189: ; preds = %bb187 bb189: ; preds = %bb187
%2 = tail call fastcc i32 @qtm_read_input(ptr %qtm) nounwind ; <i32> [#uses=0] %2 = tail call fastcc i32 @qtm_read_input(ptr %qtm) nounwind ; <i32> [#uses=0]
ret i32 undef ret i32 undef
bb193: ; preds = %bb187 bb193: ; preds = %bb187
br label %bb195 br label %bb195
bb195: ; preds = %bb193, %bb186 bb195: ; preds = %bb193, %bb186
br i1 undef, label %bb198, label %bb187 br i1 %c36, label %bb198, label %bb187
bb197: ; preds = %bb77 bb197: ; preds = %bb77
ret i32 -124 ret i32 -124
bb198: ; preds = %bb195, %bb136 bb198: ; preds = %bb195, %bb136
br i1 undef, label %bb211.preheader, label %bb214 br i1 %c37, label %bb211.preheader, label %bb214
bb211.preheader: ; preds = %bb198 bb211.preheader: ; preds = %bb198
br label %bb211 br label %bb211
bb211: ; preds = %bb211, %bb211.preheader bb211: ; preds = %bb211, %bb211.preheader
br i1 undef, label %bb214, label %bb211 br i1 %c38, label %bb214, label %bb211
bb214: ; preds = %bb211, %bb198 bb214: ; preds = %bb211, %bb198
br label %bb215 br label %bb215
bb215: ; preds = %bb238, %bb214 bb215: ; preds = %bb238, %bb214
br i1 undef, label %bb28, label %bb216 br i1 %c39, label %bb28, label %bb216
bb216: ; preds = %bb215 bb216: ; preds = %bb215
br label %bb238 br label %bb238
bb238: ; preds = %bb216, %bb14 bb238: ; preds = %bb216, %bb14
br label %bb215 br label %bb215
bb245: ; preds = %bb5, %entry bb245: ; preds = %bb5, %entry
ret i32 undef ret i32 undef
} }

llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin ; RUN: llc < %s -mtriple=armv6-apple-darwin
%struct.term = type { i32, i32, i32 } %struct.term = type { i32, i32, i32 }
declare fastcc ptr @memory_Malloc(i32) nounwind declare fastcc ptr @memory_Malloc(i32) nounwind
define fastcc ptr @t1() nounwind { define fastcc ptr @t1(i1 %c0) nounwind {
entry: entry:
br i1 undef, label %bb, label %bb1 br i1 %c0, label %bb, label %bb1
bb: ; preds = %entry bb: ; preds = %entry
ret ptr undef ret ptr undef
bb1: ; preds = %entry bb1: ; preds = %entry
%0 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; <ptr> [#uses=0] %0 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; <ptr> [#uses=0]
%1 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; <ptr> [#uses=0] %1 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; <ptr> [#uses=0]
ret ptr undef ret ptr undef
} }
define i32 @t2(i32 %argc, ptr nocapture %argv) nounwind { define i32 @t2(i32 %argc, ptr nocapture %argv, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22, i1 %c23, i1 %c24, i1 %c25, i1 %c26, i1 %c27, i1 %c28, i1 %c29, i1 %c30, i1 %c31, i1 %c32, i1 %c33, i1 %c34, i1 %c35, i1 %c36, i1 %c37, i1 %c38, i1 %c39, i1 %c40, i1 %c41, i1 %c42, i1 %c43, i1 %c44, i1 %c45, i1 %c46, i1 %c47, i1 %c48, i1 %c49, i1 %c50, i1 %c51, i1 %c52, i1 %c53, i1 %c54, i1 %c55) nounwind {
entry: entry:
br label %bb6.i8 br label %bb6.i8
bb6.i8: ; preds = %memory_CalculateRealBlockSize1374.exit.i, %entry bb6.i8: ; preds = %memory_CalculateRealBlockSize1374.exit.i, %entry
br i1 undef, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9 br i1 %c0, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9
bb.i.i9: ; preds = %bb6.i8 bb.i.i9: ; preds = %bb6.i8
br label %memory_CalculateRealBlockSize1374.exit.i br label %memory_CalculateRealBlockSize1374.exit.i
memory_CalculateRealBlockSize1374.exit.i: ; preds = %bb.i.i9, %bb6.i8 memory_CalculateRealBlockSize1374.exit.i: ; preds = %bb.i.i9, %bb6.i8
%0 = phi i32 [ undef, %bb.i.i9 ], [ undef, %bb6.i8 ] ; <i32> [#uses=2] %0 = phi i32 [ undef, %bb.i.i9 ], [ undef, %bb6.i8 ] ; <i32> [#uses=2]
store i32 %0, ptr undef, align 4 store i32 %0, ptr undef, align 4
%1 = urem i32 8184, %0 ; <i32> [#uses=1] %1 = urem i32 8184, %0 ; <i32> [#uses=1]
%2 = sub i32 8188, %1 ; <i32> [#uses=1] %2 = sub i32 8188, %1 ; <i32> [#uses=1]
store i32 %2, ptr undef, align 4 store i32 %2, ptr undef, align 4
br i1 undef, label %memory_Init.exit, label %bb6.i8 br i1 %c1, label %memory_Init.exit, label %bb6.i8
memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i
br label %bb.i.i br label %bb.i.i
bb.i.i: ; preds = %bb.i.i, %memory_Init.exit bb.i.i: ; preds = %bb.i.i, %memory_Init.exit
br i1 undef, label %symbol_Init.exit, label %bb.i.i br i1 %c2, label %symbol_Init.exit, label %bb.i.i
symbol_Init.exit: ; preds = %bb.i.i symbol_Init.exit: ; preds = %bb.i.i
br label %bb.i.i67 br label %bb.i.i67
bb.i.i67: ; preds = %bb.i.i67, %symbol_Init.exit bb.i.i67: ; preds = %bb.i.i67, %symbol_Init.exit
br i1 undef, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67 br i1 %c3, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67
symbol_CreatePrecedence3522.exit: ; preds = %bb.i.i67 symbol_CreatePrecedence3522.exit: ; preds = %bb.i.i67
br label %bb.i.i8.i br label %bb.i.i8.i
bb.i.i8.i: ; preds = %bb.i.i8.i, %symbol_CreatePrecedence3522.exit bb.i.i8.i: ; preds = %bb.i.i8.i, %symbol_CreatePrecedence3522.exit
br i1 undef, label %cont_Create.exit9.i, label %bb.i.i8.i br i1 %c4, label %cont_Create.exit9.i, label %bb.i.i8.i
cont_Create.exit9.i: ; preds = %bb.i.i8.i cont_Create.exit9.i: ; preds = %bb.i.i8.i
br label %bb.i.i.i72 br label %bb.i.i.i72
bb.i.i.i72: ; preds = %bb.i.i.i72, %cont_Create.exit9.i bb.i.i.i72: ; preds = %bb.i.i.i72, %cont_Create.exit9.i
br i1 undef, label %cont_Init.exit, label %bb.i.i.i72 br i1 %c5, label %cont_Init.exit, label %bb.i.i.i72
cont_Init.exit: ; preds = %bb.i.i.i72 cont_Init.exit: ; preds = %bb.i.i.i72
br label %bb.i103 br label %bb.i103
bb.i103: ; preds = %bb.i103, %cont_Init.exit bb.i103: ; preds = %bb.i103, %cont_Init.exit
br i1 undef, label %subs_Init.exit, label %bb.i103 br i1 %c6, label %subs_Init.exit, label %bb.i103
subs_Init.exit: ; preds = %bb.i103 subs_Init.exit: ; preds = %bb.i103
br i1 undef, label %bb1.i.i.i80, label %cc_Init.exit br i1 %c7, label %bb1.i.i.i80, label %cc_Init.exit
bb1.i.i.i80: ; preds = %subs_Init.exit bb1.i.i.i80: ; preds = %subs_Init.exit
unreachable unreachable
cc_Init.exit: ; preds = %subs_Init.exit cc_Init.exit: ; preds = %subs_Init.exit
br label %bb.i.i375 br label %bb.i.i375
bb.i.i375: ; preds = %bb.i.i375, %cc_Init.exit bb.i.i375: ; preds = %bb.i.i375, %cc_Init.exit
br i1 undef, label %bb.i439, label %bb.i.i375 br i1 %c8, label %bb.i439, label %bb.i.i375
bb.i439: ; preds = %bb.i439, %bb.i.i375 bb.i439: ; preds = %bb.i439, %bb.i.i375
br i1 undef, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439 br i1 %c9, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439
opts_DeclareSPASSFlagsAsOptions.exit: ; preds = %bb.i439 opts_DeclareSPASSFlagsAsOptions.exit: ; preds = %bb.i439
br i1 undef, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82 br i1 %c10, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82
bb.i.i82: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit bb.i.i82: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit
unreachable unreachable
opts_TranslateShortOptDeclarations.exit.i: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit opts_TranslateShortOptDeclarations.exit.i: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit
br i1 undef, label %list_Length.exit.i.thread.i, label %bb.i.i4.i br i1 %c11, label %list_Length.exit.i.thread.i, label %bb.i.i4.i
list_Length.exit.i.thread.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i list_Length.exit.i.thread.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i
br i1 undef, label %bb18.i.i.i, label %bb26.i.i.i br i1 %c12, label %bb18.i.i.i, label %bb26.i.i.i
bb.i.i4.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i bb.i.i4.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i
unreachable unreachable
bb18.i.i.i: ; preds = %list_Length.exit.i.thread.i bb18.i.i.i: ; preds = %list_Length.exit.i.thread.i
unreachable unreachable
bb26.i.i.i: ; preds = %list_Length.exit.i.thread.i bb26.i.i.i: ; preds = %list_Length.exit.i.thread.i
br i1 undef, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i br i1 %c13, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i
opts_GetOptLongOnly.exit.thread97.i: ; preds = %bb26.i.i.i opts_GetOptLongOnly.exit.thread97.i: ; preds = %bb26.i.i.i
br label %bb27.i142 br label %bb27.i142
bb27.i142: ; preds = %opts_GetOptLongOnly.exit.thread97.i, %bb26.i.i.i bb27.i142: ; preds = %opts_GetOptLongOnly.exit.thread97.i, %bb26.i.i.i
br label %bb1.i3.i br label %bb1.i3.i
bb1.i3.i: ; preds = %bb1.i3.i, %bb27.i142 bb1.i3.i: ; preds = %bb1.i3.i, %bb27.i142
br i1 undef, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i br i1 %c14, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i
opts_FreeLongOptsArray.exit.i: ; preds = %bb1.i3.i opts_FreeLongOptsArray.exit.i: ; preds = %bb1.i3.i
br label %bb.i443 br label %bb.i443
bb.i443: ; preds = %bb.i443, %opts_FreeLongOptsArray.exit.i bb.i443: ; preds = %bb.i443, %opts_FreeLongOptsArray.exit.i
br i1 undef, label %flag_InitStoreByDefaults3542.exit, label %bb.i443 br i1 %c15, label %flag_InitStoreByDefaults3542.exit, label %bb.i443
flag_InitStoreByDefaults3542.exit: ; preds = %bb.i443 flag_InitStoreByDefaults3542.exit: ; preds = %bb.i443
br i1 undef, label %bb6.i449, label %bb.i503 br i1 %c16, label %bb6.i449, label %bb.i503
bb6.i449: ; preds = %flag_InitStoreByDefaults3542.exit bb6.i449: ; preds = %flag_InitStoreByDefaults3542.exit
unreachable unreachable
bb.i503: ; preds = %bb.i503, %flag_InitStoreByDefaults3542.exit bb.i503: ; preds = %bb.i503, %flag_InitStoreByDefaults3542.exit
br i1 undef, label %flag_CleanStore3464.exit, label %bb.i503 br i1 %c17, label %flag_CleanStore3464.exit, label %bb.i503
flag_CleanStore3464.exit: ; preds = %bb.i503 flag_CleanStore3464.exit: ; preds = %bb.i503
br i1 undef, label %bb1.i81.i.preheader, label %bb.i173 br i1 %c18, label %bb1.i81.i.preheader, label %bb.i173
bb.i173: ; preds = %flag_CleanStore3464.exit bb.i173: ; preds = %flag_CleanStore3464.exit
unreachable unreachable
bb1.i81.i.preheader: ; preds = %flag_CleanStore3464.exit bb1.i81.i.preheader: ; preds = %flag_CleanStore3464.exit
br i1 undef, label %bb1.i64.i.preheader, label %bb5.i179 br i1 %c19, label %bb1.i64.i.preheader, label %bb5.i179
bb5.i179: ; preds = %bb1.i81.i.preheader bb5.i179: ; preds = %bb1.i81.i.preheader
unreachable unreachable
bb1.i64.i.preheader: ; preds = %bb1.i81.i.preheader bb1.i64.i.preheader: ; preds = %bb1.i81.i.preheader
br i1 undef, label %dfg_DeleteProofList.exit.i, label %bb.i9.i br i1 %c20, label %dfg_DeleteProofList.exit.i, label %bb.i9.i
bb.i9.i: ; preds = %bb1.i64.i.preheader bb.i9.i: ; preds = %bb1.i64.i.preheader
unreachable unreachable
dfg_DeleteProofList.exit.i: ; preds = %bb1.i64.i.preheader dfg_DeleteProofList.exit.i: ; preds = %bb1.i64.i.preheader
br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i br i1 %c21, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i
bb.i.i62.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i bb.i.i62.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i
br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i br i1 %c22, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i
term_DeleteTermList621.exit.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i term_DeleteTermList621.exit.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i
br i1 undef, label %dfg_DFGParser.exit, label %bb.i.i211 br i1 %c23, label %dfg_DFGParser.exit, label %bb.i.i211
bb.i.i211: ; preds = %term_DeleteTermList621.exit.i bb.i.i211: ; preds = %term_DeleteTermList621.exit.i
unreachable unreachable
dfg_DFGParser.exit: ; preds = %term_DeleteTermList621.exit.i dfg_DFGParser.exit: ; preds = %term_DeleteTermList621.exit.i
br label %bb.i513 br label %bb.i513
bb.i513: ; preds = %bb2.i516, %dfg_DFGParser.exit bb.i513: ; preds = %bb2.i516, %dfg_DFGParser.exit
br i1 undef, label %bb2.i516, label %bb1.i514 br i1 %c24, label %bb2.i516, label %bb1.i514
bb1.i514: ; preds = %bb.i513 bb1.i514: ; preds = %bb.i513
unreachable unreachable
bb2.i516: ; preds = %bb.i513 bb2.i516: ; preds = %bb.i513
br i1 undef, label %bb.i509, label %bb.i513 br i1 %c25, label %bb.i509, label %bb.i513
bb.i509: ; preds = %bb.i509, %bb2.i516 bb.i509: ; preds = %bb.i509, %bb2.i516
br i1 undef, label %symbol_TransferPrecedence3468.exit511, label %bb.i509 br i1 %c26, label %symbol_TransferPrecedence3468.exit511, label %bb.i509
symbol_TransferPrecedence3468.exit511: ; preds = %bb.i509 symbol_TransferPrecedence3468.exit511: ; preds = %bb.i509
br i1 undef, label %bb20, label %bb21 br i1 %c27, label %bb20, label %bb21
bb20: ; preds = %symbol_TransferPrecedence3468.exit511 bb20: ; preds = %symbol_TransferPrecedence3468.exit511
unreachable unreachable
bb21: ; preds = %symbol_TransferPrecedence3468.exit511 bb21: ; preds = %symbol_TransferPrecedence3468.exit511
br i1 undef, label %cnf_Init.exit, label %bb.i498 br i1 %c28, label %cnf_Init.exit, label %bb.i498
bb.i498: ; preds = %bb21 bb.i498: ; preds = %bb21
unreachable unreachable
cnf_Init.exit: ; preds = %bb21 cnf_Init.exit: ; preds = %bb21
br i1 undef, label %bb23, label %bb22 br i1 %c29, label %bb23, label %bb22
bb22: ; preds = %cnf_Init.exit bb22: ; preds = %cnf_Init.exit
br i1 undef, label %bb2.i.i496, label %bb.i.i494 br i1 %c30, label %bb2.i.i496, label %bb.i.i494
bb.i.i494: ; preds = %bb22 bb.i.i494: ; preds = %bb22
unreachable unreachable
bb2.i.i496: ; preds = %bb22 bb2.i.i496: ; preds = %bb22
unreachable unreachable
bb23: ; preds = %cnf_Init.exit bb23: ; preds = %cnf_Init.exit
br i1 undef, label %bb28, label %bb24 br i1 %c31, label %bb28, label %bb24
bb24: ; preds = %bb23 bb24: ; preds = %bb23
unreachable unreachable
bb28: ; preds = %bb23 bb28: ; preds = %bb23
br i1 undef, label %bb31, label %bb29 br i1 %c32, label %bb31, label %bb29
bb29: ; preds = %bb28 bb29: ; preds = %bb28
unreachable unreachable
bb31: ; preds = %bb28 bb31: ; preds = %bb28
br i1 undef, label %bb34, label %bb32 br i1 %c33, label %bb34, label %bb32
bb32: ; preds = %bb31 bb32: ; preds = %bb31
unreachable unreachable
bb34: ; preds = %bb31 bb34: ; preds = %bb31
br i1 undef, label %bb83, label %bb66 br i1 %c34, label %bb83, label %bb66
bb66: ; preds = %bb34 bb66: ; preds = %bb34
unreachable unreachable
bb83: ; preds = %bb34 bb83: ; preds = %bb34
br i1 undef, label %bb2.i1668, label %bb.i1667 br i1 %c35, label %bb2.i1668, label %bb.i1667
bb.i1667: ; preds = %bb83 bb.i1667: ; preds = %bb83
unreachable unreachable
bb2.i1668: ; preds = %bb83 bb2.i1668: ; preds = %bb83
br i1 undef, label %bb5.i205, label %bb3.i204 br i1 %c36, label %bb5.i205, label %bb3.i204
bb3.i204: ; preds = %bb2.i1668 bb3.i204: ; preds = %bb2.i1668
unreachable unreachable
bb5.i205: ; preds = %bb2.i1668 bb5.i205: ; preds = %bb2.i1668
br i1 undef, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i br i1 %c37, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i
bb.i206.i: ; preds = %bb5.i205 bb.i206.i: ; preds = %bb5.i205
br i1 undef, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i br i1 %c38, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i
bb1.i207.i: ; preds = %bb.i206.i bb1.i207.i: ; preds = %bb.i206.i
br i1 undef, label %bb25.i1801.thread, label %bb.i1688 br i1 %c39, label %bb25.i1801.thread, label %bb.i1688
bb.i1688: ; preds = %bb1.i207.i bb.i1688: ; preds = %bb1.i207.i
unreachable unreachable
bb25.i1801.thread: ; preds = %bb1.i207.i bb25.i1801.thread: ; preds = %bb1.i207.i
unreachable unreachable
ana_AnalyzeSortStructure.exit.i: ; preds = %bb.i206.i, %bb5.i205 ana_AnalyzeSortStructure.exit.i: ; preds = %bb.i206.i, %bb5.i205
br i1 undef, label %bb7.i207, label %bb.i1806 br i1 %c40, label %bb7.i207, label %bb.i1806
bb.i1806: ; preds = %ana_AnalyzeSortStructure.exit.i bb.i1806: ; preds = %ana_AnalyzeSortStructure.exit.i
br i1 undef, label %bb2.i.i.i1811, label %bb.i.i.i1809 br i1 %c41, label %bb2.i.i.i1811, label %bb.i.i.i1809
bb.i.i.i1809: ; preds = %bb.i1806 bb.i.i.i1809: ; preds = %bb.i1806
unreachable unreachable
bb2.i.i.i1811: ; preds = %bb.i1806 bb2.i.i.i1811: ; preds = %bb.i1806
unreachable unreachable
bb7.i207: ; preds = %ana_AnalyzeSortStructure.exit.i bb7.i207: ; preds = %ana_AnalyzeSortStructure.exit.i
br i1 undef, label %bb9.i, label %bb8.i br i1 %c42, label %bb9.i, label %bb8.i
bb8.i: ; preds = %bb7.i207 bb8.i: ; preds = %bb7.i207
unreachable unreachable
bb9.i: ; preds = %bb7.i207 bb9.i: ; preds = %bb7.i207
br i1 undef, label %bb23.i, label %bb26.i br i1 %c43, label %bb23.i, label %bb26.i
bb23.i: ; preds = %bb9.i bb23.i: ; preds = %bb9.i
br i1 undef, label %bb25.i, label %bb24.i br i1 %c44, label %bb25.i, label %bb24.i
bb24.i: ; preds = %bb23.i bb24.i: ; preds = %bb23.i
br i1 undef, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093 br i1 %c45, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093
bb.i2093: ; preds = %bb.i2093, %bb24.i bb.i2093: ; preds = %bb.i2093, %bb24.i
br label %bb.i2093 br label %bb.i2093
sort_SortTheoryIsTrivial.exit.i: ; preds = %bb24.i sort_SortTheoryIsTrivial.exit.i: ; preds = %bb24.i
br i1 undef, label %bb3.i2141, label %bb4.i2143 br i1 %c46, label %bb3.i2141, label %bb4.i2143
bb3.i2141: ; preds = %sort_SortTheoryIsTrivial.exit.i bb3.i2141: ; preds = %sort_SortTheoryIsTrivial.exit.i
unreachable unreachable
bb4.i2143: ; preds = %sort_SortTheoryIsTrivial.exit.i bb4.i2143: ; preds = %sort_SortTheoryIsTrivial.exit.i
br i1 undef, label %bb8.i2178, label %bb5.i2144 br i1 %c47, label %bb8.i2178, label %bb5.i2144
bb5.i2144: ; preds = %bb4.i2143 bb5.i2144: ; preds = %bb4.i2143
br i1 undef, label %bb7.i2177, label %bb1.i28.i br i1 %c48, label %bb7.i2177, label %bb1.i28.i
bb1.i28.i: ; preds = %bb5.i2144 bb1.i28.i: ; preds = %bb5.i2144
br i1 undef, label %bb4.i43.i, label %bb2.i.i2153 br i1 %c49, label %bb4.i43.i, label %bb2.i.i2153
bb2.i.i2153: ; preds = %bb1.i28.i bb2.i.i2153: ; preds = %bb1.i28.i
br i1 undef, label %bb4.i.i33.i, label %bb.i.i30.i br i1 %c50, label %bb4.i.i33.i, label %bb.i.i30.i
bb.i.i30.i: ; preds = %bb2.i.i2153 bb.i.i30.i: ; preds = %bb2.i.i2153
unreachable unreachable
bb4.i.i33.i: ; preds = %bb2.i.i2153 bb4.i.i33.i: ; preds = %bb2.i.i2153
br i1 undef, label %bb9.i.i36.i, label %bb5.i.i34.i br i1 %c51, label %bb9.i.i36.i, label %bb5.i.i34.i
bb5.i.i34.i: ; preds = %bb4.i.i33.i bb5.i.i34.i: ; preds = %bb4.i.i33.i
unreachable unreachable
bb9.i.i36.i: ; preds = %bb4.i.i33.i bb9.i.i36.i: ; preds = %bb4.i.i33.i
br i1 undef, label %bb14.i.i.i2163, label %bb10.i.i37.i br i1 %c52, label %bb14.i.i.i2163, label %bb10.i.i37.i
bb10.i.i37.i: ; preds = %bb9.i.i36.i bb10.i.i37.i: ; preds = %bb9.i.i36.i
unreachable unreachable
bb14.i.i.i2163: ; preds = %bb9.i.i36.i bb14.i.i.i2163: ; preds = %bb9.i.i36.i
br i1 undef, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164 br i1 %c53, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164
bb15.i.i.i2164: ; preds = %bb14.i.i.i2163 bb15.i.i.i2164: ; preds = %bb14.i.i.i2163
unreachable unreachable
sort_LinkPrint.exit.i.i: ; preds = %bb14.i.i.i2163 sort_LinkPrint.exit.i.i: ; preds = %bb14.i.i.i2163
unreachable unreachable
bb4.i43.i: ; preds = %bb1.i28.i bb4.i43.i: ; preds = %bb1.i28.i
unreachable unreachable
bb7.i2177: ; preds = %bb5.i2144 bb7.i2177: ; preds = %bb5.i2144
unreachable unreachable
bb8.i2178: ; preds = %bb4.i2143 bb8.i2178: ; preds = %bb4.i2143
br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader br i1 %c54, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader
bb.i5.i2185.preheader: ; preds = %bb8.i2178 bb.i5.i2185.preheader: ; preds = %bb8.i2178
br label %bb.i5.i2185 br label %bb.i5.i2185
bb.i5.i2185: ; preds = %bb.i5.i2185, %bb.i5.i2185.preheader bb.i5.i2185: ; preds = %bb.i5.i2185, %bb.i5.i2185.preheader
br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185 br i1 %c55, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185
sort_ApproxStaticSortTheory.exit: ; preds = %bb.i5.i2185, %bb8.i2178 sort_ApproxStaticSortTheory.exit: ; preds = %bb.i5.i2185, %bb8.i2178
br label %bb25.i br label %bb25.i
bb25.i: ; preds = %sort_ApproxStaticSortTheory.exit, %bb23.i bb25.i: ; preds = %sort_ApproxStaticSortTheory.exit, %bb23.i
unreachable unreachable
bb26.i: ; preds = %bb9.i bb26.i: ; preds = %bb9.i
unreachable unreachable
} }

llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll

; RUN: llc < %s -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard ; RUN: llc < %s -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard
; PR4419 ; PR4419
define float @__ieee754_acosf(float %x) nounwind { define float @__ieee754_acosf(float %x, i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
br i1 undef, label %bb, label %bb4 br i1 %c0, label %bb, label %bb4
bb: ; preds = %entry bb: ; preds = %entry
ret float undef ret float undef
bb4: ; preds = %entry bb4: ; preds = %entry
br i1 undef, label %bb5, label %bb6 br i1 %c1, label %bb5, label %bb6
bb5: ; preds = %bb4 bb5: ; preds = %bb4
ret float undef ret float undef
bb6: ; preds = %bb4 bb6: ; preds = %bb4
br i1 undef, label %bb11, label %bb12 br i1 %c2, label %bb11, label %bb12
bb11: ; preds = %bb6 bb11: ; preds = %bb6
%0 = tail call float @__ieee754_sqrtf(float undef) nounwind ; <float> [#uses=1] %0 = tail call float @__ieee754_sqrtf(float undef) nounwind ; <float> [#uses=1]
%1 = fmul float %0, -2.000000e+00 ; <float> [#uses=1] %1 = fmul float %0, -2.000000e+00 ; <float> [#uses=1]
%2 = fadd float %1, 0x400921FB40000000 ; <float> [#uses=1] %2 = fadd float %1, 0x400921FB40000000 ; <float> [#uses=1]
ret float %2 ret float %2
bb12: ; preds = %bb6 bb12: ; preds = %bb6
ret float undef ret float undef
} }
declare float @__ieee754_sqrtf(float) declare float @__ieee754_sqrtf(float)

llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin ; RUN: llc < %s -mtriple=armv6-apple-darwin
%struct.rtunion = type { i64 } %struct.rtunion = type { i64 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
define void @simplify_unary_real(ptr nocapture %p) nounwind { define void @simplify_unary_real(ptr nocapture %p, i1 %c0) nounwind {
entry: entry:
%tmp121 = load i64, ptr null, align 4 ; <i64> [#uses=1] %tmp121 = load i64, ptr null, align 4 ; <i64> [#uses=1]
%0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; <ptr> [#uses=1] %0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; <ptr> [#uses=1]
%tmp122 = load i64, ptr %0, align 4 ; <i64> [#uses=1] %tmp122 = load i64, ptr %0, align 4 ; <i64> [#uses=1]
%1 = zext i64 undef to i192 ; <i192> [#uses=2] %1 = zext i64 undef to i192 ; <i192> [#uses=2]
%2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1] %2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1]
%3 = shl i192 %2, 64 ; <i192> [#uses=2] %3 = shl i192 %2, 64 ; <i192> [#uses=2]
%4 = zext i64 %tmp122 to i192 ; <i192> [#uses=1] %4 = zext i64 %tmp122 to i192 ; <i192> [#uses=1]
%5 = shl i192 %4, 128 ; <i192> [#uses=1] %5 = shl i192 %4, 128 ; <i192> [#uses=1]
%6 = or i192 %3, %1 ; <i192> [#uses=1] %6 = or i192 %3, %1 ; <i192> [#uses=1]
%7 = or i192 %6, %5 ; <i192> [#uses=2] %7 = or i192 %6, %5 ; <i192> [#uses=2]
switch i32 undef, label %bb82 [ switch i32 undef, label %bb82 [
i32 77, label %bb38 i32 77, label %bb38
i32 129, label %bb21 i32 129, label %bb21
i32 130, label %bb20 i32 130, label %bb20
] ]
bb20: ; preds = %entry bb20: ; preds = %entry
ret void ret void
bb21: ; preds = %entry bb21: ; preds = %entry
br i1 undef, label %bb82, label %bb29 br i1 %c0, label %bb82, label %bb29
bb29: ; preds = %bb21 bb29: ; preds = %bb21
%tmp18.i = and i192 %3, 1208907372870555465154560 ; <i192> [#uses=1] %tmp18.i = and i192 %3, 1208907372870555465154560 ; <i192> [#uses=1]
%mask.i = or i192 %tmp18.i, %1 ; <i192> [#uses=1] %mask.i = or i192 %tmp18.i, %1 ; <i192> [#uses=1]
%mask41.i = or i192 %mask.i, 0 ; <i192> [#uses=1] %mask41.i = or i192 %mask.i, 0 ; <i192> [#uses=1]
br label %bb82 br label %bb82
bb38: ; preds = %entry bb38: ; preds = %entry
br label %bb82 br label %bb82
bb82: ; preds = %bb38, %bb29, %bb21, %entry bb82: ; preds = %bb38, %bb29, %bb21, %entry
%d.0 = phi i192 [ %mask41.i, %bb29 ], [ undef, %bb38 ], [ %7, %entry ], [ %7, %bb21 ] ; <i192> [#uses=1] %d.0 = phi i192 [ %mask41.i, %bb29 ], [ undef, %bb38 ], [ %7, %entry ], [ %7, %bb21 ] ; <i192> [#uses=1]
%tmp51 = trunc i192 %d.0 to i64 ; <i64> [#uses=0] %tmp51 = trunc i192 %d.0 to i64 ; <i64> [#uses=0]
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin9 ; RUN: llc < %s -mtriple=armv6-apple-darwin9
@nn = external global i32 ; <ptr> [#uses=1] @nn = external global i32 ; <ptr> [#uses=1]
@al_len = external global i32 ; <ptr> [#uses=2] @al_len = external global i32 ; <ptr> [#uses=2]
@no_mat = external global i32 ; <ptr> [#uses=2] @no_mat = external global i32 ; <ptr> [#uses=2]
@no_mis = external global i32 ; <ptr> [#uses=2] @no_mis = external global i32 ; <ptr> [#uses=2]
@"\01LC12" = external constant [29 x i8], align 1 ; <ptr> [#uses=1] @"\01LC12" = external constant [29 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC16" = external constant [33 x i8], align 1 ; <ptr> [#uses=1] @"\01LC16" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1]
declare i32 @printf(ptr nocapture, ...) nounwind declare i32 @printf(ptr nocapture, ...) nounwind
declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) nounwind {
entry: entry:
br i1 undef, label %bb5, label %bb br i1 %c0, label %bb5, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br label %bb br label %bb
bb5: ; preds = %entry bb5: ; preds = %entry
br i1 undef, label %bb6, label %bb8 br i1 %c1, label %bb6, label %bb8
bb6: ; preds = %bb6, %bb5 bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6 br i1 %c2, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5 bb8: ; preds = %bb6, %bb5
br label %bb15 br label %bb15
bb9: ; preds = %bb15 bb9: ; preds = %bb15
br i1 undef, label %bb10, label %bb11 br i1 %c3, label %bb10, label %bb11
bb10: ; preds = %bb9 bb10: ; preds = %bb9
unreachable unreachable
bb11: ; preds = %bb9 bb11: ; preds = %bb9
%0 = load i32, ptr undef, align 4 ; <i32> [#uses=2] %0 = load i32, ptr undef, align 4 ; <i32> [#uses=2]
%1 = add i32 %0, 1 ; <i32> [#uses=2] %1 = add i32 %0, 1 ; <i32> [#uses=2]
store i32 %1, ptr undef, align 4 store i32 %1, ptr undef, align 4
Show All 9 Linesbb11: ; preds = %bb9
%6 = tail call i32 (ptr, ...) @printf(ptr @"\01LC12", double %5) nounwind ; <i32> [#uses=0] %6 = tail call i32 (ptr, ...) @printf(ptr @"\01LC12", double %5) nounwind ; <i32> [#uses=0]
%7 = load i32, ptr @al_len, align 4 ; <i32> [#uses=1] %7 = load i32, ptr @al_len, align 4 ; <i32> [#uses=1]
%8 = load i32, ptr @no_mat, align 4 ; <i32> [#uses=1] %8 = load i32, ptr @no_mat, align 4 ; <i32> [#uses=1]
%9 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1] %9 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1]
%10 = sub i32 %7, %8 ; <i32> [#uses=1] %10 = sub i32 %7, %8 ; <i32> [#uses=1]
%11 = sub i32 %10, %9 ; <i32> [#uses=1] %11 = sub i32 %10, %9 ; <i32> [#uses=1]
%12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; <i32> [#uses=0] %12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; <i32> [#uses=0]
%13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] %13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0]
br i1 undef, label %bb15, label %bb12 br i1 %c4, label %bb15, label %bb12
bb12: ; preds = %bb11 bb12: ; preds = %bb11
br label %bb228.i br label %bb228.i
bb74.i: ; preds = %bb228.i bb74.i: ; preds = %bb228.i
br i1 undef, label %bb138.i, label %bb145.i br i1 %c5, label %bb138.i, label %bb145.i
bb138.i: ; preds = %bb74.i bb138.i: ; preds = %bb74.i
br label %bb145.i br label %bb145.i
bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
br i1 undef, label %bb146.i, label %bb151.i br i1 %c6, label %bb146.i, label %bb151.i
bb146.i: ; preds = %bb145.i bb146.i: ; preds = %bb145.i
br i1 undef, label %bb228.i, label %bb151.i br i1 %c7, label %bb228.i, label %bb151.i
bb151.i: ; preds = %bb146.i, %bb145.i bb151.i: ; preds = %bb146.i, %bb145.i
br i1 undef, label %bb153.i, label %bb228.i br i1 %c8, label %bb153.i, label %bb228.i
bb153.i: ; preds = %bb151.i bb153.i: ; preds = %bb151.i
br i1 undef, label %bb220.i, label %bb.nph.i98 br i1 %c9, label %bb220.i, label %bb.nph.i98
bb.nph.i98: ; preds = %bb153.i bb.nph.i98: ; preds = %bb153.i
br label %bb158.i br label %bb158.i
bb158.i: ; preds = %bb218.i, %bb.nph.i98 bb158.i: ; preds = %bb218.i, %bb.nph.i98
br i1 undef, label %bb168.i, label %bb160.i br i1 %c10, label %bb168.i, label %bb160.i
bb160.i: ; preds = %bb158.i bb160.i: ; preds = %bb158.i
br i1 undef, label %bb161.i, label %bb168.i br i1 %c11, label %bb161.i, label %bb168.i
bb161.i: ; preds = %bb160.i bb161.i: ; preds = %bb160.i
br i1 undef, label %bb168.i, label %bb163.i br i1 %c12, label %bb168.i, label %bb163.i
bb163.i: ; preds = %bb161.i bb163.i: ; preds = %bb161.i
br i1 undef, label %bb167.i, label %bb168.i br i1 %c13, label %bb167.i, label %bb168.i
bb167.i: ; preds = %bb163.i bb167.i: ; preds = %bb163.i
br label %bb168.i br label %bb168.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
br i1 undef, label %bb211.i, label %bb218.i br i1 %c14, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i bb211.i: ; preds = %bb168.i
br label %bb218.i br label %bb218.i
bb218.i: ; preds = %bb211.i, %bb168.i bb218.i: ; preds = %bb211.i, %bb168.i
br i1 undef, label %bb220.i, label %bb158.i br i1 %c15, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i bb220.i: ; preds = %bb218.i, %bb153.i
br i1 undef, label %bb221.i, label %bb228.i br i1 %c16, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i bb221.i: ; preds = %bb220.i
br label %bb228.i br label %bb228.i
bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
br i1 undef, label %bb74.i, label %bb145.i br i1 %c17, label %bb74.i, label %bb145.i
bb15: ; preds = %bb11, %bb8 bb15: ; preds = %bb11, %bb8
br i1 undef, label %return, label %bb9 br i1 %c18, label %return, label %bb9
return: ; preds = %bb15 return: ; preds = %bb15
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin9 ; RUN: llc < %s -mtriple=armv6-apple-darwin9
@no_mat = external global i32 ; <ptr> [#uses=1] @no_mat = external global i32 ; <ptr> [#uses=1]
@no_mis = external global i32 ; <ptr> [#uses=2] @no_mis = external global i32 ; <ptr> [#uses=2]
@"\01LC11" = external constant [33 x i8], align 1 ; <ptr> [#uses=1] @"\01LC11" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC15" = external constant [33 x i8], align 1 ; <ptr> [#uses=1] @"\01LC15" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1]
declare i32 @printf(ptr nocapture, ...) nounwind declare i32 @printf(ptr nocapture, ...) nounwind
declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) nounwind {
entry: entry:
br i1 undef, label %bb5, label %bb br i1 %c0, label %bb5, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br label %bb br label %bb
bb5: ; preds = %entry bb5: ; preds = %entry
br i1 undef, label %bb6, label %bb8 br i1 %c1, label %bb6, label %bb8
bb6: ; preds = %bb6, %bb5 bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6 br i1 %c2, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5 bb8: ; preds = %bb6, %bb5
br label %bb15 br label %bb15
bb9: ; preds = %bb15 bb9: ; preds = %bb15
br i1 undef, label %bb10, label %bb11 br i1 %c3, label %bb10, label %bb11
bb10: ; preds = %bb9 bb10: ; preds = %bb9
unreachable unreachable
bb11: ; preds = %bb9 bb11: ; preds = %bb9
%0 = load i32, ptr undef, align 4 ; <i32> [#uses=3] %0 = load i32, ptr undef, align 4 ; <i32> [#uses=3]
%1 = add i32 %0, 1 ; <i32> [#uses=2] %1 = add i32 %0, 1 ; <i32> [#uses=2]
store i32 %1, ptr undef, align 4 store i32 %1, ptr undef, align 4
%2 = load i32, ptr undef, align 4 ; <i32> [#uses=2] %2 = load i32, ptr undef, align 4 ; <i32> [#uses=2]
%3 = sub i32 %2, %0 ; <i32> [#uses=1] %3 = sub i32 %2, %0 ; <i32> [#uses=1]
store i32 0, ptr @no_mat, align 4 store i32 0, ptr @no_mat, align 4
store i32 0, ptr @no_mis, align 4 store i32 0, ptr @no_mis, align 4
%4 = getelementptr i8, ptr %B, i32 %0 ; <ptr> [#uses=1] %4 = getelementptr i8, ptr %B, i32 %0 ; <ptr> [#uses=1]
tail call void @diff(ptr undef, ptr %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind tail call void @diff(ptr undef, ptr %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
%5 = tail call i32 (ptr, ...) @printf(ptr @"\01LC11", i32 %tmp13) nounwind ; <i32> [#uses=0] %5 = tail call i32 (ptr, ...) @printf(ptr @"\01LC11", i32 %tmp13) nounwind ; <i32> [#uses=0]
%6 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1] %6 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1]
%7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; <i32> [#uses=0] %7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; <i32> [#uses=0]
%8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] %8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
br i1 undef, label %bb15, label %bb12 br i1 %c4, label %bb15, label %bb12
bb12: ; preds = %bb11 bb12: ; preds = %bb11
br label %bb228.i br label %bb228.i
bb74.i: ; preds = %bb228.i bb74.i: ; preds = %bb228.i
br i1 undef, label %bb138.i, label %bb145.i br i1 %c5, label %bb138.i, label %bb145.i
bb138.i: ; preds = %bb74.i bb138.i: ; preds = %bb74.i
br label %bb145.i br label %bb145.i
bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
br i1 undef, label %bb146.i, label %bb151.i br i1 %c6, label %bb146.i, label %bb151.i
bb146.i: ; preds = %bb145.i bb146.i: ; preds = %bb145.i
br i1 undef, label %bb228.i, label %bb151.i br i1 %c7, label %bb228.i, label %bb151.i
bb151.i: ; preds = %bb146.i, %bb145.i bb151.i: ; preds = %bb146.i, %bb145.i
br i1 undef, label %bb153.i, label %bb228.i br i1 %c8, label %bb153.i, label %bb228.i
bb153.i: ; preds = %bb151.i bb153.i: ; preds = %bb151.i
br i1 undef, label %bb220.i, label %bb.nph.i98 br i1 %c9, label %bb220.i, label %bb.nph.i98
bb.nph.i98: ; preds = %bb153.i bb.nph.i98: ; preds = %bb153.i
br label %bb158.i br label %bb158.i
bb158.i: ; preds = %bb218.i, %bb.nph.i98 bb158.i: ; preds = %bb218.i, %bb.nph.i98
br i1 undef, label %bb168.i, label %bb160.i br i1 %c10, label %bb168.i, label %bb160.i
bb160.i: ; preds = %bb158.i bb160.i: ; preds = %bb158.i
br i1 undef, label %bb161.i, label %bb168.i br i1 %c11, label %bb161.i, label %bb168.i
bb161.i: ; preds = %bb160.i bb161.i: ; preds = %bb160.i
br i1 undef, label %bb168.i, label %bb163.i br i1 %c12, label %bb168.i, label %bb163.i
bb163.i: ; preds = %bb161.i bb163.i: ; preds = %bb161.i
br i1 undef, label %bb167.i, label %bb168.i br i1 %c13, label %bb167.i, label %bb168.i
bb167.i: ; preds = %bb163.i bb167.i: ; preds = %bb163.i
br label %bb168.i br label %bb168.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
br i1 undef, label %bb211.i, label %bb218.i br i1 %c14, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i bb211.i: ; preds = %bb168.i
br label %bb218.i br label %bb218.i
bb218.i: ; preds = %bb211.i, %bb168.i bb218.i: ; preds = %bb211.i, %bb168.i
br i1 undef, label %bb220.i, label %bb158.i br i1 %c15, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i bb220.i: ; preds = %bb218.i, %bb153.i
br i1 undef, label %bb221.i, label %bb228.i br i1 %c16, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i bb221.i: ; preds = %bb220.i
br label %bb228.i br label %bb228.i
bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
br i1 undef, label %bb74.i, label %bb145.i br i1 %c17, label %bb74.i, label %bb145.i
bb15: ; preds = %bb11, %bb8 bb15: ; preds = %bb11, %bb8
%indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; <i32> [#uses=2] %indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; <i32> [#uses=2]
%tmp13 = add i32 %indvar11, 1 ; <i32> [#uses=2] %tmp13 = add i32 %indvar11, 1 ; <i32> [#uses=2]
%count.0 = sub i32 undef, %indvar11 ; <i32> [#uses=0] %count.0 = sub i32 undef, %indvar11 ; <i32> [#uses=0]
br i1 undef, label %return, label %bb9 br i1 %c18, label %return, label %bb9
return: ; preds = %bb15 return: ; preds = %bb15
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin9 ; RUN: llc < %s -mtriple=armv6-apple-darwin9
@JJ = external global ptr ; <ptr> [#uses=1] @JJ = external global ptr ; <ptr> [#uses=1]
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15) nounwind {
entry: entry:
br i1 undef, label %bb5, label %bb br i1 %c0, label %bb5, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br label %bb br label %bb
bb5: ; preds = %entry bb5: ; preds = %entry
br i1 undef, label %bb6, label %bb8 br i1 %c1, label %bb6, label %bb8
bb6: ; preds = %bb6, %bb5 bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6 br i1 %c2, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5 bb8: ; preds = %bb6, %bb5
br label %bb15 br label %bb15
bb9: ; preds = %bb15 bb9: ; preds = %bb15
br i1 undef, label %bb10, label %bb11 br i1 %c3, label %bb10, label %bb11
bb10: ; preds = %bb9 bb10: ; preds = %bb9
unreachable unreachable
bb11: ; preds = %bb9 bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12 br i1 %c4, label %bb15, label %bb12
bb12: ; preds = %bb11 bb12: ; preds = %bb11
%0 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1] %0 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1]
br label %bb228.i br label %bb228.i
bb74.i: ; preds = %bb228.i bb74.i: ; preds = %bb228.i
br i1 undef, label %bb138.i, label %bb145.i br i1 %c5, label %bb138.i, label %bb145.i
bb138.i: ; preds = %bb74.i bb138.i: ; preds = %bb74.i
br label %bb145.i br label %bb145.i
bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
%cflag.0.i = phi i16 [ 0, %bb228.i ], [ 0, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=1] %cflag.0.i = phi i16 [ 0, %bb228.i ], [ 0, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=1]
br i1 undef, label %bb146.i, label %bb151.i br i1 %c6, label %bb146.i, label %bb151.i
bb146.i: ; preds = %bb145.i bb146.i: ; preds = %bb145.i
br i1 undef, label %bb228.i, label %bb151.i br i1 %c7, label %bb228.i, label %bb151.i
bb151.i: ; preds = %bb146.i, %bb145.i bb151.i: ; preds = %bb146.i, %bb145.i
%.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1] %.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1]
%or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1] %or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1]
br i1 %or.cond298, label %bb153.i, label %bb228.i br i1 %or.cond298, label %bb153.i, label %bb228.i
bb153.i: ; preds = %bb151.i bb153.i: ; preds = %bb151.i
br i1 undef, label %bb220.i, label %bb.nph.i98 br i1 %c8, label %bb220.i, label %bb.nph.i98
bb.nph.i98: ; preds = %bb153.i bb.nph.i98: ; preds = %bb153.i
br label %bb158.i br label %bb158.i
bb158.i: ; preds = %bb218.i, %bb.nph.i98 bb158.i: ; preds = %bb218.i, %bb.nph.i98
%c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1] %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1]
%cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1] %cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1]
%pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %8, %bb218.i ] ; <i32> [#uses=1] %pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %8, %bb218.i ] ; <i32> [#uses=1]
%pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1] %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1]
%fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=3] %fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=3]
%ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2] %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2]
%i.121.i = sub i32 undef, undef ; <i32> [#uses=3] %i.121.i = sub i32 undef, undef ; <i32> [#uses=3]
%tmp105.i = sub i32 undef, undef ; <i32> [#uses=1] %tmp105.i = sub i32 undef, undef ; <i32> [#uses=1]
%1 = sub i32 %c.1020.i, undef ; <i32> [#uses=0] %1 = sub i32 %c.1020.i, undef ; <i32> [#uses=0]
br i1 undef, label %bb168.i, label %bb160.i br i1 %c9, label %bb168.i, label %bb160.i
bb160.i: ; preds = %bb158.i bb160.i: ; preds = %bb158.i
br i1 undef, label %bb161.i, label %bb168.i br i1 %c10, label %bb161.i, label %bb168.i
bb161.i: ; preds = %bb160.i bb161.i: ; preds = %bb160.i
br i1 undef, label %bb168.i, label %bb163.i br i1 %c11, label %bb168.i, label %bb163.i
bb163.i: ; preds = %bb161.i bb163.i: ; preds = %bb161.i
%2 = icmp slt i32 %fj.515.i, undef ; <i1> [#uses=1] %2 = icmp slt i32 %fj.515.i, undef ; <i1> [#uses=1]
%3 = and i1 %2, undef ; <i1> [#uses=1] %3 = and i1 %2, undef ; <i1> [#uses=1]
br i1 %3, label %bb167.i, label %bb168.i br i1 %3, label %bb167.i, label %bb168.i
bb167.i: ; preds = %bb163.i bb167.i: ; preds = %bb163.i
br label %bb168.i br label %bb168.i
Show All 12 Linesbb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1] %cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1]
%c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2] %c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2]
store i32 %c.14.i, ptr undef, align 4 store i32 %c.14.i, ptr undef, align 4
%7 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1] %7 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
%8 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1] %8 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
store i32 %ci.12.i, ptr %scevgep88.i, align 4 store i32 %ci.12.i, ptr %scevgep88.i, align 4
store i32 %cj.11.i100, ptr %scevgep89.i, align 4 store i32 %cj.11.i100, ptr %scevgep89.i, align 4
store i32 %4, ptr undef, align 4 store i32 %4, ptr undef, align 4
br i1 undef, label %bb211.i, label %bb218.i br i1 %c12, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i bb211.i: ; preds = %bb168.i
br label %bb218.i br label %bb218.i
bb218.i: ; preds = %bb211.i, %bb168.i bb218.i: ; preds = %bb211.i, %bb168.i
%cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2] %cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2]
%9 = icmp slt i32 %tmp105.i, undef ; <i1> [#uses=1] %9 = icmp slt i32 %tmp105.i, undef ; <i1> [#uses=1]
br i1 %9, label %bb220.i, label %bb158.i br i1 %9, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i bb220.i: ; preds = %bb218.i, %bb153.i
%cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=0] %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=0]
br i1 undef, label %bb221.i, label %bb228.i br i1 %c13, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i bb221.i: ; preds = %bb220.i
br label %bb228.i br label %bb228.i
bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
br i1 undef, label %bb74.i, label %bb145.i br i1 %c14, label %bb74.i, label %bb145.i
bb15: ; preds = %bb11, %bb8 bb15: ; preds = %bb11, %bb8
br i1 undef, label %return, label %bb9 br i1 %c15, label %return, label %bb9
return: ; preds = %bb15 return: ; preds = %bb15
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin9 ; RUN: llc < %s -mtriple=armv6-apple-darwin9
@r = external global i32 ; <ptr> [#uses=1] @r = external global i32 ; <ptr> [#uses=1]
@qr = external global i32 ; <ptr> [#uses=1] @qr = external global i32 ; <ptr> [#uses=1]
@II = external global ptr ; <ptr> [#uses=1] @II = external global ptr ; <ptr> [#uses=1]
@no_mis = external global i32 ; <ptr> [#uses=1] @no_mis = external global i32 ; <ptr> [#uses=1]
@name1 = external global ptr ; <ptr> [#uses=1] @name1 = external global ptr ; <ptr> [#uses=1]
declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17) nounwind {
entry: entry:
br i1 undef, label %bb5, label %bb br i1 %c0, label %bb5, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br label %bb br label %bb
bb5: ; preds = %entry bb5: ; preds = %entry
br i1 undef, label %bb6, label %bb8 br i1 %c1, label %bb6, label %bb8
bb6: ; preds = %bb6, %bb5 bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6 br i1 %c2, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5 bb8: ; preds = %bb6, %bb5
%0 = load ptr, ptr @name1, align 4 ; <ptr> [#uses=0] %0 = load ptr, ptr @name1, align 4 ; <ptr> [#uses=0]
br label %bb15 br label %bb15
bb9: ; preds = %bb15 bb9: ; preds = %bb15
br i1 undef, label %bb10, label %bb11 br i1 %c3, label %bb10, label %bb11
bb10: ; preds = %bb9 bb10: ; preds = %bb9
unreachable unreachable
bb11: ; preds = %bb9 bb11: ; preds = %bb9
store i32 0, ptr @no_mis, align 4 store i32 0, ptr @no_mis, align 4
%1 = getelementptr i8, ptr %A, i32 0 ; <ptr> [#uses=1] %1 = getelementptr i8, ptr %A, i32 0 ; <ptr> [#uses=1]
%2 = getelementptr i8, ptr %B, i32 0 ; <ptr> [#uses=1] %2 = getelementptr i8, ptr %B, i32 0 ; <ptr> [#uses=1]
tail call void @diff(ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind tail call void @diff(ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
br i1 undef, label %bb15, label %bb12 br i1 %c4, label %bb15, label %bb12
bb12: ; preds = %bb11 bb12: ; preds = %bb11
%3 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1] %3 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1]
%4 = load i32, ptr @r, align 4 ; <i32> [#uses=1] %4 = load i32, ptr @r, align 4 ; <i32> [#uses=1]
%5 = load i32, ptr @qr, align 4 ; <i32> [#uses=1] %5 = load i32, ptr @qr, align 4 ; <i32> [#uses=1]
br label %bb228.i br label %bb228.i
bb74.i: ; preds = %bb228.i bb74.i: ; preds = %bb228.i
br i1 undef, label %bb138.i, label %bb145.i br i1 %c5, label %bb138.i, label %bb145.i
bb138.i: ; preds = %bb74.i bb138.i: ; preds = %bb74.i
br label %bb145.i br label %bb145.i
bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
br i1 undef, label %bb146.i, label %bb151.i br i1 %c6, label %bb146.i, label %bb151.i
bb146.i: ; preds = %bb145.i bb146.i: ; preds = %bb145.i
br i1 undef, label %bb228.i, label %bb151.i br i1 %c7, label %bb228.i, label %bb151.i
bb151.i: ; preds = %bb146.i, %bb145.i bb151.i: ; preds = %bb146.i, %bb145.i
br i1 undef, label %bb153.i, label %bb228.i br i1 %c8, label %bb153.i, label %bb228.i
bb153.i: ; preds = %bb151.i bb153.i: ; preds = %bb151.i
%6 = add i32 undef, -1 ; <i32> [#uses=3] %6 = add i32 undef, -1 ; <i32> [#uses=3]
br i1 undef, label %bb220.i, label %bb.nph.i98 br i1 %c9, label %bb220.i, label %bb.nph.i98
bb.nph.i98: ; preds = %bb153.i bb.nph.i98: ; preds = %bb153.i
br label %bb158.i br label %bb158.i
bb158.i: ; preds = %bb218.i, %bb.nph.i98 bb158.i: ; preds = %bb218.i, %bb.nph.i98
%c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1] %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1]
%f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1] %f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1]
%pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %10, %bb218.i ] ; <i32> [#uses=1] %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %10, %bb218.i ] ; <i32> [#uses=1]
%fj.515.i = phi i32 [ %6, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2] %fj.515.i = phi i32 [ %6, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2]
%fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3] %fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3]
%cj.811.i = phi i32 [ %6, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3] %cj.811.i = phi i32 [ %6, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3]
%ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2] %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2]
%7 = sub i32 %f.419.i, %4 ; <i32> [#uses=5] %7 = sub i32 %f.419.i, %4 ; <i32> [#uses=5]
%8 = sub i32 %c.1020.i, %5 ; <i32> [#uses=2] %8 = sub i32 %c.1020.i, %5 ; <i32> [#uses=2]
%9 = icmp slt i32 %7, %8 ; <i1> [#uses=1] %9 = icmp slt i32 %7, %8 ; <i1> [#uses=1]
br i1 %9, label %bb168.i, label %bb160.i br i1 %9, label %bb168.i, label %bb160.i
bb160.i: ; preds = %bb158.i bb160.i: ; preds = %bb158.i
br i1 undef, label %bb161.i, label %bb168.i br i1 %c10, label %bb161.i, label %bb168.i
bb161.i: ; preds = %bb160.i bb161.i: ; preds = %bb160.i
br i1 undef, label %bb168.i, label %bb163.i br i1 %c11, label %bb168.i, label %bb163.i
bb163.i: ; preds = %bb161.i bb163.i: ; preds = %bb161.i
br i1 undef, label %bb167.i, label %bb168.i br i1 %c12, label %bb167.i, label %bb168.i
bb167.i: ; preds = %bb163.i bb167.i: ; preds = %bb163.i
br label %bb168.i br label %bb168.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2] %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2] %f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2]
%scevgep88.i = getelementptr i32, ptr %3, i32 undef ; <ptr> [#uses=1] %scevgep88.i = getelementptr i32, ptr %3, i32 undef ; <ptr> [#uses=1]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1] %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1]
%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
%10 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1] %10 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
br i1 undef, label %bb211.i, label %bb218.i br i1 %c13, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i bb211.i: ; preds = %bb168.i
br label %bb218.i br label %bb218.i
bb218.i: ; preds = %bb211.i, %bb168.i bb218.i: ; preds = %bb211.i, %bb168.i
br i1 undef, label %bb220.i, label %bb158.i br i1 %c14, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i bb220.i: ; preds = %bb218.i, %bb153.i
%11 = getelementptr i32, ptr null, i32 %6 ; <ptr> [#uses=1] %11 = getelementptr i32, ptr null, i32 %6 ; <ptr> [#uses=1]
store i32 undef, ptr %11, align 4 store i32 undef, ptr %11, align 4
br i1 undef, label %bb221.i, label %bb228.i br i1 %c15, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i bb221.i: ; preds = %bb220.i
br label %bb228.i br label %bb228.i
bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
br i1 undef, label %bb74.i, label %bb145.i br i1 %c16, label %bb74.i, label %bb145.i
bb15: ; preds = %bb11, %bb8 bb15: ; preds = %bb11, %bb8
br i1 undef, label %return, label %bb9 br i1 %c17, label %return, label %bb9
return: ; preds = %bb15 return: ; preds = %bb15
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin9 ; RUN: llc < %s -mtriple=armv6-apple-darwin9
@XX = external global ptr ; <ptr> [#uses=1] @XX = external global ptr ; <ptr> [#uses=1]
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) nounwind {
entry: entry:
br i1 undef, label %bb5, label %bb br i1 %c0, label %bb5, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br label %bb br label %bb
bb5: ; preds = %entry bb5: ; preds = %entry
br i1 undef, label %bb6, label %bb8 br i1 %c1, label %bb6, label %bb8
bb6: ; preds = %bb6, %bb5 bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6 br i1 %c2, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5 bb8: ; preds = %bb6, %bb5
br label %bb15 br label %bb15
bb9: ; preds = %bb15 bb9: ; preds = %bb15
br i1 undef, label %bb10, label %bb11 br i1 %c3, label %bb10, label %bb11
bb10: ; preds = %bb9 bb10: ; preds = %bb9
unreachable unreachable
bb11: ; preds = %bb9 bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12 br i1 %c4, label %bb15, label %bb12
bb12: ; preds = %bb11 bb12: ; preds = %bb11
%0 = load ptr, ptr @XX, align 4 ; <ptr> [#uses=0] %0 = load ptr, ptr @XX, align 4 ; <ptr> [#uses=0]
br label %bb228.i br label %bb228.i
bb74.i: ; preds = %bb228.i bb74.i: ; preds = %bb228.i
br i1 undef, label %bb138.i, label %bb145.i br i1 %c5, label %bb138.i, label %bb145.i
bb138.i: ; preds = %bb74.i bb138.i: ; preds = %bb74.i
br label %bb145.i br label %bb145.i
bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
br i1 undef, label %bb146.i, label %bb151.i br i1 %c6, label %bb146.i, label %bb151.i
bb146.i: ; preds = %bb145.i bb146.i: ; preds = %bb145.i
br i1 undef, label %bb228.i, label %bb151.i br i1 %c7, label %bb228.i, label %bb151.i
bb151.i: ; preds = %bb146.i, %bb145.i bb151.i: ; preds = %bb146.i, %bb145.i
br i1 undef, label %bb153.i, label %bb228.i br i1 %c8, label %bb153.i, label %bb228.i
bb153.i: ; preds = %bb151.i bb153.i: ; preds = %bb151.i
br i1 undef, label %bb220.i, label %bb.nph.i98 br i1 %c9, label %bb220.i, label %bb.nph.i98
bb.nph.i98: ; preds = %bb153.i bb.nph.i98: ; preds = %bb153.i
br label %bb158.i br label %bb158.i
bb158.i: ; preds = %bb218.i, %bb.nph.i98 bb158.i: ; preds = %bb218.i, %bb.nph.i98
%1 = sub i32 undef, undef ; <i32> [#uses=4] %1 = sub i32 undef, undef ; <i32> [#uses=4]
%2 = sub i32 undef, undef ; <i32> [#uses=1] %2 = sub i32 undef, undef ; <i32> [#uses=1]
br i1 undef, label %bb168.i, label %bb160.i br i1 %c10, label %bb168.i, label %bb160.i
bb160.i: ; preds = %bb158.i bb160.i: ; preds = %bb158.i
br i1 undef, label %bb161.i, label %bb168.i br i1 %c11, label %bb161.i, label %bb168.i
bb161.i: ; preds = %bb160.i bb161.i: ; preds = %bb160.i
br i1 undef, label %bb168.i, label %bb163.i br i1 %c12, label %bb168.i, label %bb163.i
bb163.i: ; preds = %bb161.i bb163.i: ; preds = %bb161.i
br i1 undef, label %bb167.i, label %bb168.i br i1 %c13, label %bb167.i, label %bb168.i
bb167.i: ; preds = %bb163.i bb167.i: ; preds = %bb163.i
br label %bb168.i br label %bb168.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1] %f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
store i32 %c.14.i, ptr undef, align 4 store i32 %c.14.i, ptr undef, align 4
store i32 undef, ptr null, align 4 store i32 undef, ptr null, align 4
br i1 undef, label %bb211.i, label %bb218.i br i1 %c14, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i bb211.i: ; preds = %bb168.i
br label %bb218.i br label %bb218.i
bb218.i: ; preds = %bb211.i, %bb168.i bb218.i: ; preds = %bb211.i, %bb168.i
br i1 undef, label %bb220.i, label %bb158.i br i1 %c15, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i bb220.i: ; preds = %bb218.i, %bb153.i
br i1 undef, label %bb221.i, label %bb228.i br i1 %c16, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i bb221.i: ; preds = %bb220.i
br label %bb228.i br label %bb228.i
bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
br i1 undef, label %bb74.i, label %bb145.i br i1 %c17, label %bb74.i, label %bb145.i
bb15: ; preds = %bb11, %bb8 bb15: ; preds = %bb11, %bb8
br i1 undef, label %return, label %bb9 br i1 %c18, label %return, label %bb9
return: ; preds = %bb15 return: ; preds = %bb15
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin9 ; RUN: llc < %s -mtriple=armv6-apple-darwin9
@qr = external global i32 ; <ptr> [#uses=1] @qr = external global i32 ; <ptr> [#uses=1]
@II = external global ptr ; <ptr> [#uses=1] @II = external global ptr ; <ptr> [#uses=1]
@JJ = external global ptr ; <ptr> [#uses=1] @JJ = external global ptr ; <ptr> [#uses=1]
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind { define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13) nounwind {
entry: entry:
br i1 undef, label %bb5, label %bb br i1 %c0, label %bb5, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br label %bb br label %bb
bb5: ; preds = %entry bb5: ; preds = %entry
br i1 undef, label %bb6, label %bb8 br i1 %c1, label %bb6, label %bb8
bb6: ; preds = %bb6, %bb5 bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6 br i1 %c2, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5 bb8: ; preds = %bb6, %bb5
br label %bb15 br label %bb15
bb9: ; preds = %bb15 bb9: ; preds = %bb15
br i1 undef, label %bb10, label %bb11 br i1 %c3, label %bb10, label %bb11
bb10: ; preds = %bb9 bb10: ; preds = %bb9
unreachable unreachable
bb11: ; preds = %bb9 bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12 br i1 %c4, label %bb15, label %bb12
bb12: ; preds = %bb11 bb12: ; preds = %bb11
%0 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1] %0 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1]
%1 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1] %1 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1]
%2 = load i32, ptr @qr, align 4 ; <i32> [#uses=1] %2 = load i32, ptr @qr, align 4 ; <i32> [#uses=1]
br label %bb228.i br label %bb228.i
bb74.i: ; preds = %bb228.i bb74.i: ; preds = %bb228.i
br i1 undef, label %bb138.i, label %bb145.i br i1 %c5, label %bb138.i, label %bb145.i
bb138.i: ; preds = %bb74.i bb138.i: ; preds = %bb74.i
br label %bb145.i br label %bb145.i
bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
%cflag.0.i = phi i16 [ %cflag.1.i, %bb228.i ], [ %cflag.1.i, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=2] %cflag.0.i = phi i16 [ %cflag.1.i, %bb228.i ], [ %cflag.1.i, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=2]
br i1 undef, label %bb146.i, label %bb151.i br i1 %c6, label %bb146.i, label %bb151.i
bb146.i: ; preds = %bb145.i bb146.i: ; preds = %bb145.i
br i1 undef, label %bb228.i, label %bb151.i br i1 %c7, label %bb228.i, label %bb151.i
bb151.i: ; preds = %bb146.i, %bb145.i bb151.i: ; preds = %bb146.i, %bb145.i
%.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1] %.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1]
%or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1] %or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1]
br i1 %or.cond298, label %bb153.i, label %bb228.i br i1 %or.cond298, label %bb153.i, label %bb228.i
bb153.i: ; preds = %bb151.i bb153.i: ; preds = %bb151.i
br i1 undef, label %bb220.i, label %bb.nph.i98 br i1 %c8, label %bb220.i, label %bb.nph.i98
bb.nph.i98: ; preds = %bb153.i bb.nph.i98: ; preds = %bb153.i
br label %bb158.i br label %bb158.i
bb158.i: ; preds = %bb218.i, %bb.nph.i98 bb158.i: ; preds = %bb218.i, %bb.nph.i98
%c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1] %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1]
%f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1] %f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1]
%cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1] %cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1]
%pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1] %pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1]
%pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %6, %bb218.i ] ; <i32> [#uses=1] %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %6, %bb218.i ] ; <i32> [#uses=1]
%fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2] %fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2]
%fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3] %fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3]
%cj.811.i = phi i32 [ undef, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3] %cj.811.i = phi i32 [ undef, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3]
%ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2] %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2]
%3 = sub i32 %f.419.i, 0 ; <i32> [#uses=5] %3 = sub i32 %f.419.i, 0 ; <i32> [#uses=5]
%4 = sub i32 %c.1020.i, %2 ; <i32> [#uses=2] %4 = sub i32 %c.1020.i, %2 ; <i32> [#uses=2]
%5 = icmp slt i32 %3, %4 ; <i1> [#uses=1] %5 = icmp slt i32 %3, %4 ; <i1> [#uses=1]
br i1 %5, label %bb168.i, label %bb160.i br i1 %5, label %bb168.i, label %bb160.i
bb160.i: ; preds = %bb158.i bb160.i: ; preds = %bb158.i
br i1 undef, label %bb161.i, label %bb168.i br i1 %c9, label %bb161.i, label %bb168.i
bb161.i: ; preds = %bb160.i bb161.i: ; preds = %bb160.i
br i1 undef, label %bb168.i, label %bb163.i br i1 %c10, label %bb168.i, label %bb163.i
bb163.i: ; preds = %bb161.i bb163.i: ; preds = %bb161.i
br i1 undef, label %bb167.i, label %bb168.i br i1 %c11, label %bb167.i, label %bb168.i
bb167.i: ; preds = %bb163.i bb167.i: ; preds = %bb163.i
br label %bb168.i br label %bb168.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2] %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2] %f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2]
%scevgep88.i = getelementptr i32, ptr %0, i32 undef ; <ptr> [#uses=2] %scevgep88.i = getelementptr i32, ptr %0, i32 undef ; <ptr> [#uses=2]
%scevgep89.i = getelementptr i32, ptr %1, i32 undef ; <ptr> [#uses=2] %scevgep89.i = getelementptr i32, ptr %1, i32 undef ; <ptr> [#uses=2]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0] %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2] %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2]
%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
%6 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1] %6 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
%7 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1] %7 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
store i32 %ci.12.i, ptr %scevgep88.i, align 4 store i32 %ci.12.i, ptr %scevgep88.i, align 4
store i32 %cj.11.i100, ptr %scevgep89.i, align 4 store i32 %cj.11.i100, ptr %scevgep89.i, align 4
br i1 undef, label %bb211.i, label %bb218.i br i1 %c12, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i bb211.i: ; preds = %bb168.i
br label %bb218.i br label %bb218.i
bb218.i: ; preds = %bb211.i, %bb168.i bb218.i: ; preds = %bb211.i, %bb168.i
%cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2] %cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2]
%8 = icmp slt i32 undef, undef ; <i1> [#uses=1] %8 = icmp slt i32 undef, undef ; <i1> [#uses=1]
br i1 %8, label %bb220.i, label %bb158.i br i1 %8, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i bb220.i: ; preds = %bb218.i, %bb153.i
%cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=2] %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=2]
br i1 undef, label %bb221.i, label %bb228.i br i1 %c13, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i bb221.i: ; preds = %bb220.i
br label %bb228.i br label %bb228.i
bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
%cflag.1.i = phi i16 [ 0, %bb146.i ], [ %cflag.0.i, %bb151.i ], [ %cflag.4.lcssa.i, %bb220.i ], [ 1, %bb12 ], [ %cflag.4.lcssa.i, %bb221.i ] ; <i16> [#uses=2] %cflag.1.i = phi i16 [ 0, %bb146.i ], [ %cflag.0.i, %bb151.i ], [ %cflag.4.lcssa.i, %bb220.i ], [ 1, %bb12 ], [ %cflag.4.lcssa.i, %bb221.i ] ; <i16> [#uses=2]
br i1 false, label %bb74.i, label %bb145.i br i1 false, label %bb74.i, label %bb145.i
bb15: ; preds = %bb11, %bb8 bb15: ; preds = %bb11, %bb8
br i1 false, label %return, label %bb9 br i1 false, label %return, label %bb9
return: ; preds = %bb15 return: ; preds = %bb15
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin10 ; RUN: llc < %s -mtriple=armv6-apple-darwin10
%struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr } %struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr }
%struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr } %struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr }
%struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr } %struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr }
%struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 } %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 }
%struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 } %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 }
declare i32 @strlen(ptr nocapture) nounwind readonly declare i32 @strlen(ptr nocapture) nounwind readonly
define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12) nounwind {
entry: entry:
br i1 undef, label %bb126, label %bb1 br i1 %c0, label %bb126, label %bb1
bb1: ; preds = %entry bb1: ; preds = %entry
br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit br i1 %c1, label %cli_calloc.exit.thread, label %cli_calloc.exit
cli_calloc.exit.thread: ; preds = %bb1 cli_calloc.exit.thread: ; preds = %bb1
ret i32 -114 ret i32 -114
cli_calloc.exit: ; preds = %bb1 cli_calloc.exit: ; preds = %bb1
store i16 %parts, ptr undef, align 4 store i16 %parts, ptr undef, align 4
br i1 undef, label %bb52, label %bb4 br i1 %c2, label %bb52, label %bb4
bb4: ; preds = %cli_calloc.exit bb4: ; preds = %cli_calloc.exit
br i1 undef, label %bb.i, label %bb1.i3 br i1 %c3, label %bb.i, label %bb1.i3
bb.i: ; preds = %bb4 bb.i: ; preds = %bb4
unreachable unreachable
bb1.i3: ; preds = %bb4 bb1.i3: ; preds = %bb4
br i1 undef, label %bb2.i4, label %cli_strdup.exit br i1 %c4, label %bb2.i4, label %cli_strdup.exit
bb2.i4: ; preds = %bb1.i3 bb2.i4: ; preds = %bb1.i3
ret i32 -114 ret i32 -114
cli_strdup.exit: ; preds = %bb1.i3 cli_strdup.exit: ; preds = %bb1.i3
br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 br i1 %c5, label %cli_calloc.exit54.thread, label %cli_calloc.exit54
cli_calloc.exit54.thread: ; preds = %cli_strdup.exit cli_calloc.exit54.thread: ; preds = %cli_strdup.exit
ret i32 -114 ret i32 -114
cli_calloc.exit54: ; preds = %cli_strdup.exit cli_calloc.exit54: ; preds = %cli_strdup.exit
br label %bb45 br label %bb45
cli_calloc.exit70.thread: ; preds = %bb45 cli_calloc.exit70.thread: ; preds = %bb45
unreachable unreachable
cli_calloc.exit70: ; preds = %bb45 cli_calloc.exit70: ; preds = %bb45
br i1 undef, label %bb.i83, label %bb1.i84 br i1 %c6, label %bb.i83, label %bb1.i84
bb.i83: ; preds = %cli_calloc.exit70 bb.i83: ; preds = %cli_calloc.exit70
unreachable unreachable
bb1.i84: ; preds = %cli_calloc.exit70 bb1.i84: ; preds = %cli_calloc.exit70
br i1 undef, label %bb2.i85, label %bb17 br i1 %c7, label %bb2.i85, label %bb17
bb2.i85: ; preds = %bb1.i84 bb2.i85: ; preds = %bb1.i84
unreachable unreachable
bb17: ; preds = %bb1.i84 bb17: ; preds = %bb1.i84
br i1 undef, label %bb22, label %bb.nph br i1 %c8, label %bb22, label %bb.nph
bb.nph: ; preds = %bb17 bb.nph: ; preds = %bb17
br label %bb18 br label %bb18
bb18: ; preds = %bb18, %bb.nph bb18: ; preds = %bb18, %bb.nph
br i1 undef, label %bb18, label %bb22 br i1 %c9, label %bb18, label %bb22
bb22: ; preds = %bb18, %bb17 bb22: ; preds = %bb18, %bb17
br i1 undef, label %bb25, label %bb43.preheader br i1 %c10, label %bb25, label %bb43.preheader
bb43.preheader: ; preds = %bb22 bb43.preheader: ; preds = %bb22
br i1 undef, label %bb28, label %bb45 br i1 %c11, label %bb28, label %bb45
bb25: ; preds = %bb22 bb25: ; preds = %bb22
unreachable unreachable
bb28: ; preds = %bb43.preheader bb28: ; preds = %bb43.preheader
unreachable unreachable
bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 br i1 %c12, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
bb52: ; preds = %cli_calloc.exit bb52: ; preds = %cli_calloc.exit
%0 = load i16, ptr undef, align 4 ; <i16> [#uses=1] %0 = load i16, ptr undef, align 4 ; <i16> [#uses=1]
%1 = icmp eq i16 %0, 0 ; <i1> [#uses=1] %1 = icmp eq i16 %0, 0 ; <i1> [#uses=1]
%iftmp.20.0 = select i1 %1, ptr %hexsig, ptr null ; <ptr> [#uses=1] %iftmp.20.0 = select i1 %1, ptr %hexsig, ptr null ; <ptr> [#uses=1]
%2 = tail call i32 @strlen(ptr %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] %2 = tail call i32 @strlen(ptr %iftmp.20.0) nounwind readonly ; <i32> [#uses=0]
unreachable unreachable
bb126: ; preds = %entry bb126: ; preds = %entry
ret i32 -117 ret i32 -117
} }

llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll

; RUN: llc -mtriple=arm-eabi %s -o /dev/null ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
%struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr } %struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr }
%struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr } %struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr }
%struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr } %struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr }
%struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 } %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 }
%struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 } %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 }
define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind { define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11) nounwind {
entry: entry:
br i1 undef, label %bb126, label %bb1 br i1 %c0, label %bb126, label %bb1
bb1: ; preds = %entry bb1: ; preds = %entry
br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit br i1 %c1, label %cli_calloc.exit.thread, label %cli_calloc.exit
cli_calloc.exit.thread: ; preds = %bb1 cli_calloc.exit.thread: ; preds = %bb1
ret i32 -114 ret i32 -114
cli_calloc.exit: ; preds = %bb1 cli_calloc.exit: ; preds = %bb1
br i1 undef, label %bb52, label %bb4 br i1 %c2, label %bb52, label %bb4
bb4: ; preds = %cli_calloc.exit bb4: ; preds = %cli_calloc.exit
br i1 undef, label %bb.i, label %bb1.i3 br i1 %c3, label %bb.i, label %bb1.i3
bb.i: ; preds = %bb4 bb.i: ; preds = %bb4
unreachable unreachable
bb1.i3: ; preds = %bb4 bb1.i3: ; preds = %bb4
br i1 undef, label %bb2.i4, label %cli_strdup.exit br i1 %c4, label %bb2.i4, label %cli_strdup.exit
bb2.i4: ; preds = %bb1.i3 bb2.i4: ; preds = %bb1.i3
ret i32 -114 ret i32 -114
cli_strdup.exit: ; preds = %bb1.i3 cli_strdup.exit: ; preds = %bb1.i3
br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54 br i1 %c5, label %cli_calloc.exit54.thread, label %cli_calloc.exit54
cli_calloc.exit54.thread: ; preds = %cli_strdup.exit cli_calloc.exit54.thread: ; preds = %cli_strdup.exit
ret i32 -114 ret i32 -114
cli_calloc.exit54: ; preds = %cli_strdup.exit cli_calloc.exit54: ; preds = %cli_strdup.exit
br label %bb45 br label %bb45
cli_calloc.exit70.thread: ; preds = %bb45 cli_calloc.exit70.thread: ; preds = %bb45
unreachable unreachable
cli_calloc.exit70: ; preds = %bb45 cli_calloc.exit70: ; preds = %bb45
br i1 undef, label %bb.i83, label %bb1.i84 br i1 %c6, label %bb.i83, label %bb1.i84
bb.i83: ; preds = %cli_calloc.exit70 bb.i83: ; preds = %cli_calloc.exit70
unreachable unreachable
bb1.i84: ; preds = %cli_calloc.exit70 bb1.i84: ; preds = %cli_calloc.exit70
br i1 undef, label %bb2.i85, label %bb17 br i1 %c7, label %bb2.i85, label %bb17
bb2.i85: ; preds = %bb1.i84 bb2.i85: ; preds = %bb1.i84
unreachable unreachable
bb17: ; preds = %bb1.i84 bb17: ; preds = %bb1.i84
br i1 undef, label %bb22, label %bb.nph br i1 %c8, label %bb22, label %bb.nph
bb.nph: ; preds = %bb17 bb.nph: ; preds = %bb17
br label %bb18 br label %bb18
bb18: ; preds = %bb18, %bb.nph bb18: ; preds = %bb18, %bb.nph
br i1 undef, label %bb18, label %bb22 br i1 %c9, label %bb18, label %bb22
bb22: ; preds = %bb18, %bb17 bb22: ; preds = %bb18, %bb17
%0 = getelementptr i8, ptr null, i32 10 ; <ptr> [#uses=1] %0 = getelementptr i8, ptr null, i32 10 ; <ptr> [#uses=1]
%1 = load i16, ptr %0, align 2 ; <i16> [#uses=1] %1 = load i16, ptr %0, align 2 ; <i16> [#uses=1]
%2 = add i16 %1, 1 ; <i16> [#uses=1] %2 = add i16 %1, 1 ; <i16> [#uses=1]
%3 = zext i16 %2 to i32 ; <i32> [#uses=1] %3 = zext i16 %2 to i32 ; <i32> [#uses=1]
%4 = mul i32 %3, 3 ; <i32> [#uses=1] %4 = mul i32 %3, 3 ; <i32> [#uses=1]
%5 = add i32 %4, -1 ; <i32> [#uses=1] %5 = add i32 %4, -1 ; <i32> [#uses=1]
%6 = icmp eq i32 %5, undef ; <i1> [#uses=1] %6 = icmp eq i32 %5, undef ; <i1> [#uses=1]
br i1 %6, label %bb25, label %bb43.preheader br i1 %6, label %bb25, label %bb43.preheader
bb43.preheader: ; preds = %bb22 bb43.preheader: ; preds = %bb22
br i1 undef, label %bb28, label %bb45 br i1 %c10, label %bb28, label %bb45
bb25: ; preds = %bb22 bb25: ; preds = %bb22
unreachable unreachable
bb28: ; preds = %bb43.preheader bb28: ; preds = %bb43.preheader
unreachable unreachable
bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 br i1 %c11, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
bb52: ; preds = %cli_calloc.exit bb52: ; preds = %cli_calloc.exit
unreachable unreachable
bb126: ; preds = %entry bb126: ; preds = %entry
ret i32 -117 ret i32 -117
} }

llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll

; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3 ; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3
@a = external global double ; <ptr> [#uses=1] @a = external global double ; <ptr> [#uses=1]
declare double @llvm.exp.f64(double) nounwind readonly declare double @llvm.exp.f64(double) nounwind readonly
define void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind { define void @findratio(ptr nocapture %res1, ptr nocapture %res2, i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
br label %bb br label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
br i1 undef, label %bb28, label %bb br i1 %c0, label %bb28, label %bb
bb28: ; preds = %bb bb28: ; preds = %bb
%0 = load double, ptr @a, align 4 ; <double> [#uses=2] %0 = load double, ptr @a, align 4 ; <double> [#uses=2]
%1 = fadd double %0, undef ; <double> [#uses=2] %1 = fadd double %0, undef ; <double> [#uses=2]
br i1 undef, label %bb59, label %bb60 br i1 %c1, label %bb59, label %bb60
bb59: ; preds = %bb28 bb59: ; preds = %bb28
%2 = fsub double -0.000000e+00, undef ; <double> [#uses=2] %2 = fsub double -0.000000e+00, undef ; <double> [#uses=2]
br label %bb61 br label %bb61
bb60: ; preds = %bb28 bb60: ; preds = %bb28
%3 = tail call double @llvm.exp.f64(double undef) nounwind ; <double> [#uses=1] %3 = tail call double @llvm.exp.f64(double undef) nounwind ; <double> [#uses=1]
%4 = fsub double -0.000000e+00, %3 ; <double> [#uses=2] %4 = fsub double -0.000000e+00, %3 ; <double> [#uses=2]
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesbb61: ; preds = %bb60, %bb59
%.pn12 = fadd double %.pn16, undef ; <double> [#uses=1] %.pn12 = fadd double %.pn16, undef ; <double> [#uses=1]
%.pn10 = fadd double %.pn14, %.pn15 ; <double> [#uses=1] %.pn10 = fadd double %.pn14, %.pn15 ; <double> [#uses=1]
%.pn8 = fsub double %.pn12, undef ; <double> [#uses=1] %.pn8 = fsub double %.pn12, undef ; <double> [#uses=1]
%.pn6 = fsub double %.pn10, %.pn11 ; <double> [#uses=1] %.pn6 = fsub double %.pn10, %.pn11 ; <double> [#uses=1]
%.pn4 = fadd double %.pn8, undef ; <double> [#uses=1] %.pn4 = fadd double %.pn8, undef ; <double> [#uses=1]
%.pn2 = fadd double %.pn6, %.pn7 ; <double> [#uses=1] %.pn2 = fadd double %.pn6, %.pn7 ; <double> [#uses=1]
%N1.0 = fsub double %.pn4, undef ; <double> [#uses=1] %N1.0 = fsub double %.pn4, undef ; <double> [#uses=1]
%D1.0 = fsub double %.pn2, undef ; <double> [#uses=2] %D1.0 = fsub double %.pn2, undef ; <double> [#uses=2]
br i1 undef, label %bb62, label %bb64 br i1 %c2, label %bb62, label %bb64
bb62: ; preds = %bb61 bb62: ; preds = %bb61
%7 = fadd double %D1.0, undef ; <double> [#uses=1] %7 = fadd double %D1.0, undef ; <double> [#uses=1]
br label %bb64 br label %bb64
bb64: ; preds = %bb62, %bb61 bb64: ; preds = %bb62, %bb61
%.pn = phi double [ undef, %bb62 ], [ %N1.0, %bb61 ] ; <double> [#uses=1] %.pn = phi double [ undef, %bb62 ], [ %N1.0, %bb61 ] ; <double> [#uses=1]
%.pn1 = phi double [ %7, %bb62 ], [ %D1.0, %bb61 ] ; <double> [#uses=1] %.pn1 = phi double [ %7, %bb62 ], [ %D1.0, %bb61 ] ; <double> [#uses=1]
%x.1 = fdiv double %.pn, %.pn1 ; <double> [#uses=0] %x.1 = fdiv double %.pn, %.pn1 ; <double> [#uses=0]
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll

; RUN: llc < %s -mtriple=arm-linux-gnueabi ; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR4528 ; PR4528
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv6-elf" target triple = "armv6-elf"
define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size) nounwind optsize { define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size, i1 %c0, i1 %c1, i1 %c2) nounwind optsize {
entry: entry:
br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i br i1 %c0, label %fault_in_pages_writeable.exit, label %bb5.i
bb5.i: ; preds = %entry bb5.i: ; preds = %entry
%asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1] %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1]
%0 = icmp eq i32 %asmtmp.i, 0 ; <i1> [#uses=1] %0 = icmp eq i32 %asmtmp.i, 0 ; <i1> [#uses=1]
br i1 %0, label %bb6.i, label %fault_in_pages_writeable.exit br i1 %0, label %bb6.i, label %fault_in_pages_writeable.exit
bb6.i: ; preds = %bb5.i bb6.i: ; preds = %bb5.i
br i1 undef, label %fault_in_pages_writeable.exit, label %bb7.i br i1 %c1, label %fault_in_pages_writeable.exit, label %bb7.i
bb7.i: ; preds = %bb6.i bb7.i: ; preds = %bb6.i
unreachable unreachable
fault_in_pages_writeable.exit: ; preds = %bb6.i, %bb5.i, %entry fault_in_pages_writeable.exit: ; preds = %bb6.i, %bb5.i, %entry
br i1 undef, label %bb2, label %bb3 br i1 %c2, label %bb2, label %bb3
bb2: ; preds = %fault_in_pages_writeable.exit bb2: ; preds = %fault_in_pages_writeable.exit
unreachable unreachable
bb3: ; preds = %fault_in_pages_writeable.exit bb3: ; preds = %fault_in_pages_writeable.exit
%1 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; <i32> [#uses=0] %1 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; <i32> [#uses=0]
unreachable unreachable
} }
declare i32 @__copy_to_user(ptr, ptr, i32) declare i32 @__copy_to_user(ptr, ptr, i32)

llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll

; RUN: llc < %s -mtriple=arm-linux-gnueabi ; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR4528 ; PR4528
define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size, i1 %c0) nounwind optsize {
entry: entry:
br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i br i1 %c0, label %fault_in_pages_writeable.exit, label %bb5.i
bb5.i: ; preds = %entry bb5.i: ; preds = %entry
%asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1] %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1]
br label %fault_in_pages_writeable.exit br label %fault_in_pages_writeable.exit
fault_in_pages_writeable.exit: ; preds = %bb5.i, %entry fault_in_pages_writeable.exit: ; preds = %bb5.i, %entry
%0 = phi i32 [ 0, %entry ], [ %asmtmp.i, %bb5.i ] ; <i32> [#uses=1] %0 = phi i32 [ 0, %entry ], [ %asmtmp.i, %bb5.i ] ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
Show All 11 Lines

llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll

; RUN: llc < %s -mtriple=arm-linux-gnueabi ; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR4528 ; PR4528
; Inline asm is allowed to contain operands "=&r", "0". ; Inline asm is allowed to contain operands "=&r", "0".
%struct.device_dma_parameters = type { i32, i32 } %struct.device_dma_parameters = type { i32, i32 }
%struct.iovec = type { ptr, i32 } %struct.iovec = type { ptr, i32 }
define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags) nounwind optsize { define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags, i1 %c0, i1 %c1) nounwind optsize {
entry: entry:
br label %bb8 br label %bb8
bb: ; preds = %bb8 bb: ; preds = %bb8
br i1 undef, label %bb10, label %bb2 br i1 %c0, label %bb10, label %bb2
bb2: ; preds = %bb bb2: ; preds = %bb
%asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1] %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1]
%asmresult = extractvalue %struct.device_dma_parameters %asmtmp, 0; <i32> [#uses=1] %asmresult = extractvalue %struct.device_dma_parameters %asmtmp, 0; <i32> [#uses=1]
%0 = icmp eq i32 %asmresult, 0 ; <i1> [#uses=1] %0 = icmp eq i32 %asmresult, 0 ; <i1> [#uses=1]
br i1 %0, label %bb7, label %bb4 br i1 %0, label %bb7, label %bb4
bb4: ; preds = %bb2 bb4: ; preds = %bb2
br i1 undef, label %bb10, label %bb9 br i1 %c1, label %bb10, label %bb9
bb7: ; preds = %bb2 bb7: ; preds = %bb2
%1 = add i32 %2, 1 ; <i32> [#uses=1] %1 = add i32 %2, 1 ; <i32> [#uses=1]
br label %bb8 br label %bb8
bb8: ; preds = %bb7, %entry bb8: ; preds = %bb7, %entry
%2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; <i32> [#uses=3] %2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; <i32> [#uses=3]
%scevgep22 = getelementptr %struct.iovec, ptr %iov, i32 %2, i32 0; <ptr> [#uses=0] %scevgep22 = getelementptr %struct.iovec, ptr %iov, i32 %2, i32 0; <ptr> [#uses=0]
Show All 11 Lines

llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll

; RUN: llc < %s -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8 ; RUN: llc < %s -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
; ModuleID = '<stdin>' ; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-apple-darwin9" target triple = "armv7-apple-darwin9"
%struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr } %struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr }
@g = common global ptr null @g = common global ptr null
define ptr @tsp(ptr %t, i32 %nproc) nounwind { define ptr @tsp(ptr %t, i32 %nproc, i1 %c0, i1 %c1) nounwind {
entry: entry:
%t.idx51.val.i = load double, ptr null ; <double> [#uses=1] %t.idx51.val.i = load double, ptr null ; <double> [#uses=1]
br i1 undef, label %bb4.i, label %bb.i br i1 %c0, label %bb4.i, label %bb.i
bb.i: ; preds = %entry bb.i: ; preds = %entry
unreachable unreachable
bb4.i: ; preds = %entry bb4.i: ; preds = %entry
%0 = load ptr, ptr @g, align 4 ; <ptr> [#uses=2] %0 = load ptr, ptr @g, align 4 ; <ptr> [#uses=2]
%.idx45.i = getelementptr %struct.tree, ptr %0, i32 0, i32 1 ; <ptr> [#uses=1] %.idx45.i = getelementptr %struct.tree, ptr %0, i32 0, i32 1 ; <ptr> [#uses=1]
%.idx45.val.i = load double, ptr %.idx45.i ; <double> [#uses=1] %.idx45.val.i = load double, ptr %.idx45.i ; <double> [#uses=1]
%.idx46.i = getelementptr %struct.tree, ptr %0, i32 0, i32 2 ; <ptr> [#uses=1] %.idx46.i = getelementptr %struct.tree, ptr %0, i32 0, i32 2 ; <ptr> [#uses=1]
%.idx46.val.i = load double, ptr %.idx46.i ; <double> [#uses=1] %.idx46.val.i = load double, ptr %.idx46.i ; <double> [#uses=1]
%1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2] %1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2]
%2 = fmul double %1, %1 ; <double> [#uses=1] %2 = fmul double %1, %1 ; <double> [#uses=1]
%3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2] %3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2]
%4 = fmul double %3, %3 ; <double> [#uses=1] %4 = fmul double %3, %3 ; <double> [#uses=1]
%5 = fadd double %2, %4 ; <double> [#uses=1] %5 = fadd double %2, %4 ; <double> [#uses=1]
%6 = tail call double @llvm.sqrt.f64(double %5) nounwind ; <double> [#uses=1] %6 = tail call double @llvm.sqrt.f64(double %5) nounwind ; <double> [#uses=1]
br i1 undef, label %bb7.i4, label %bb6.i br i1 %c1, label %bb7.i4, label %bb6.i
bb6.i: ; preds = %bb4.i bb6.i: ; preds = %bb4.i
br label %bb7.i4 br label %bb7.i4
bb7.i4: ; preds = %bb6.i, %bb4.i bb7.i4: ; preds = %bb6.i, %bb4.i
%tton1.0.i = phi double [ %6, %bb6.i ], [ undef, %bb4.i ] ; <double> [#uses=0] %tton1.0.i = phi double [ %6, %bb6.i ], [ undef, %bb4.i ] ; <double> [#uses=0]
unreachable unreachable
} }
declare double @llvm.sqrt.f64(double) nounwind readonly declare double @llvm.sqrt.f64(double) nounwind readonly

llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll

; RUN: llc -mtriple thumbv7---elf -mattr=+neon -filetype asm -o - %s | FileCheck %s ; RUN: llc -mtriple thumbv7---elf -mattr=+neon -filetype asm -o - %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf" target triple = "thumbv7-elf"
%bar = type { float, float, float } %bar = type { float, float, float }
%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 } %baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
%foo = type { <4 x float> } %foo = type { <4 x float> }
%quux = type { ptr, ptr, i32 } %quux = type { ptr, ptr, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
define void @aaaa(ptr %this, ptr %block) { define void @aaaa(ptr %this, ptr %block, i1 %c0, i1 %c1) {
entry: entry:
br i1 undef, label %bb.nph269, label %bb201 br i1 %c0, label %bb.nph269, label %bb201
bb.nph269: bb.nph269:
br label %bb12 br label %bb12
bb12: bb12:
%0 = fmul <4 x float> undef, undef %0 = fmul <4 x float> undef, undef
%1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3> %1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3>
%2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> zeroinitializer %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> zeroinitializer
%3 = fadd <4 x float> undef, %2 %3 = fadd <4 x float> undef, %2
br i1 undef, label %bb194, label %bb186 br i1 %c1, label %bb194, label %bb186
bb186: bb186:
br label %bb194 br label %bb194
bb194: bb194:
%besterror.0.0 = phi <4 x float> [ %3, %bb186 ], [ undef, %bb12 ] %besterror.0.0 = phi <4 x float> [ %3, %bb186 ], [ undef, %bb12 ]
%indvar.next294 = add i32 undef, 1 %indvar.next294 = add i32 undef, 1
br label %bb12 br label %bb12
bb201: bb201:
ret void ret void
} }
; CHECK-NOT: fldmfdd ; CHECK-NOT: fldmfdd

llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll

; RUN: llc < %s -mattr=+neon ; RUN: llc < %s -mattr=+neon
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf" target triple = "thumbv7-elf"
define void @foo() nounwind { define void @foo(i1 %c0) nounwind {
entry: entry:
%0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1]
%tmp28 = extractelement <2 x float> %0, i32 0 ; <float> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; <float> [#uses=1]
%1 = fcmp une float %tmp28, 4.900000e+01 ; <i1> [#uses=1] %1 = fcmp une float %tmp28, 4.900000e+01 ; <i1> [#uses=1]
br i1 %1, label %bb, label %bb7 br i1 %1, label %bb, label %bb7
bb: ; preds = %entry bb: ; preds = %entry
unreachable unreachable
bb7: ; preds = %entry bb7: ; preds = %entry
br i1 undef, label %bb8, label %bb9 br i1 %c0, label %bb8, label %bb9
bb8: ; preds = %bb7 bb8: ; preds = %bb7
unreachable unreachable
bb9: ; preds = %bb7 bb9: ; preds = %bb7
ret void ret void
} }
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone

llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll

; RUN: llc -mattr=+neon < %s ; RUN: llc -mattr=+neon < %s
; PR4965 ; PR4965
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi" target triple = "armv7-eabi"
%struct.fr = type { [6 x %struct.pl] } %struct.fr = type { [6 x %struct.pl] }
%struct.obb = type { %"struct.m4", %"struct.p3" } %struct.obb = type { %"struct.m4", %"struct.p3" }
%struct.pl = type { %"struct.p3" } %struct.pl = type { %"struct.p3" }
%"struct.m4" = type { %"struct.p3", %"struct.p3", %"struct.p3", %"struct.p3" } %"struct.m4" = type { %"struct.p3", %"struct.p3", %"struct.p3", %"struct.p3" }
%"struct.p3" = type { <4 x float> } %"struct.p3" = type { <4 x float> }
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind { define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box, i1 %c0) nounwind {
entry: entry:
%val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1] %val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1]
%val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1] %val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1]
%elt3.i.i = getelementptr inbounds %struct.obb, ptr %box, i32 0, i32 0, i32 2, i32 0 ; <ptr> [#uses=1] %elt3.i.i = getelementptr inbounds %struct.obb, ptr %box, i32 0, i32 0, i32 2, i32 0 ; <ptr> [#uses=1]
%val4.i.i = load <4 x float>, ptr %elt3.i.i ; <<4 x float>> [#uses=1] %val4.i.i = load <4 x float>, ptr %elt3.i.i ; <<4 x float>> [#uses=1]
%0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
%1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1] %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]
br label %bb33 br label %bb33
Show All 23 Linesbb: ; preds = %bb33
%23 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %22, <2 x float> %22) nounwind ; <<2 x float>> [#uses=2] %23 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %22, <2 x float> %22) nounwind ; <<2 x float>> [#uses=2]
%24 = shufflevector <2 x float> %23, <2 x float> %23, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %24 = shufflevector <2 x float> %23, <2 x float> %23, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%25 = fadd <4 x float> %24, zeroinitializer ; <<4 x float>> [#uses=1] %25 = fadd <4 x float> %24, zeroinitializer ; <<4 x float>> [#uses=1]
%tmp46 = extractelement <4 x float> %25, i32 0 ; <float> [#uses=1] %tmp46 = extractelement <4 x float> %25, i32 0 ; <float> [#uses=1]
%26 = fcmp olt float %tmp46, 0.000000e+00 ; <i1> [#uses=1] %26 = fcmp olt float %tmp46, 0.000000e+00 ; <i1> [#uses=1]
br i1 %26, label %bb41, label %bb33 br i1 %26, label %bb41, label %bb33
bb33: ; preds = %bb, %entry bb33: ; preds = %bb, %entry
br i1 undef, label %bb34, label %bb br i1 %c0, label %bb34, label %bb
bb34: ; preds = %bb33 bb34: ; preds = %bb33
ret i8 undef ret i8 undef
bb41: ; preds = %bb bb41: ; preds = %bb
ret i8 1 ret i8 1
} }

llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll

; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 ; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9
; PR4986 ; PR4986
define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems, i1 %c0, i1 %c1) nounwind {
entry: entry:
br i1 undef, label %return, label %bb.preheader br i1 %c0, label %return, label %bb.preheader
bb.preheader: ; preds = %entry bb.preheader: ; preds = %entry
br label %bb br label %bb
bb: ; preds = %bb, %bb.preheader bb: ; preds = %bb, %bb.preheader
%0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1] %2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1] %3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
%4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1] %4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1]
%5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1] %5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1]
store float %5, ptr undef, align 4 store float %5, ptr undef, align 4
br i1 undef, label %return, label %bb br i1 %c1, label %return, label %bb
return: ; preds = %bb, %entry return: ; preds = %bb, %entry
ret void ret void
} }
define arm_aapcs_vfpcc <4 x float> @bar(ptr nocapture %pBuffer, i32 %numItems) nounwind { define arm_aapcs_vfpcc <4 x float> @bar(ptr nocapture %pBuffer, i32 %numItems) nounwind {
%1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1] %2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1] %3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1]
%4 = insertelement <4 x float> %3, float undef, i32 3 ; <<4 x float>> [#uses=1] %4 = insertelement <4 x float> %3, float undef, i32 3 ; <<4 x float>> [#uses=1]
%5 = shufflevector <4 x float> %4, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] %5 = shufflevector <4 x float> %4, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
%6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1] %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
ret <4 x float> %6 ret <4 x float> %6
} }

llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll

; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
; PR5024 ; PR5024
%bar = type { %foo, %foo } %bar = type { %foo, %foo }
%foo = type { <4 x float> } %foo = type { <4 x float> }
declare arm_aapcs_vfpcc float @aaa(ptr nocapture) nounwind readonly declare arm_aapcs_vfpcc float @aaa(ptr nocapture) nounwind readonly
declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind
define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems) nounwind { define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems, i1 %c0) nounwind {
entry: entry:
br i1 undef, label %return, label %bb.nph br i1 %c0, label %return, label %bb.nph
bb.nph: ; preds = %entry bb.nph: ; preds = %entry
%0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; <ptr> [#uses=0] %0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; <ptr> [#uses=0]
%1 = call arm_aapcs_vfpcc float @aaa(ptr undef) nounwind ; <float> [#uses=0] %1 = call arm_aapcs_vfpcc float @aaa(ptr undef) nounwind ; <float> [#uses=0]
unreachable unreachable
return: ; preds = %entry return: ; preds = %entry
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll

; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s
; PR5367 ; PR5367
define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems) nounwind { define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems, i1 %c0, i1 %c1) nounwind {
entry: entry:
br i1 undef, label %return, label %bb br i1 %c0, label %return, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%0 = load float, ptr undef, align 4 ; <float> [#uses=1] %0 = load float, ptr undef, align 4 ; <float> [#uses=1]
%1 = load float, ptr null, align 4 ; <float> [#uses=1] %1 = load float, ptr null, align 4 ; <float> [#uses=1]
%2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1] %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2] %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2]
%4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
%5 = insertelement <4 x float> %4, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=4] %5 = insertelement <4 x float> %4, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=4]
Show All 34 Linesbb: ; preds = %bb, %entry
%40 = fadd <4 x float> %36, %39 ; <<4 x float>> [#uses=1] %40 = fadd <4 x float> %36, %39 ; <<4 x float>> [#uses=1]
%41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1] %41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1]
%42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1] %42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
%43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1] %43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1]
store float undef, ptr undef, align 4 store float undef, ptr undef, align 4
store float 0.000000e+00, ptr null, align 4 store float 0.000000e+00, ptr null, align 4
%44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1] %44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1]
store float %44, ptr undef, align 4 store float %44, ptr undef, align 4
br i1 undef, label %return, label %bb br i1 %c1, label %return, label %bb
return: ; preds = %bb, %entry return: ; preds = %bb, %entry
ret void ret void
} }
declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone

llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll

; RUN: llc -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 < %s | FileCheck %s ; RUN: llc -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi" target triple = "armv7-eabi"
define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind { define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems, i1 %c0, i1 %c1) nounwind {
entry: entry:
br i1 undef, label %return, label %bb br i1 %c0, label %return, label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
; CHECK: vld1.16 {d16[], d17[]} ; CHECK: vld1.16 {d16[], d17[]}
%0 = load i16, ptr undef, align 2 %0 = load i16, ptr undef, align 2
%1 = insertelement <8 x i16> undef, i16 %0, i32 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 2
%2 = insertelement <8 x i16> %1, i16 undef, i32 3 %2 = insertelement <8 x i16> %1, i16 undef, i32 3
%3 = mul <8 x i16> %2, %2 %3 = mul <8 x i16> %2, %2
%4 = extractelement <8 x i16> %3, i32 2 %4 = extractelement <8 x i16> %3, i32 2
store i16 %4, ptr undef, align 2 store i16 %4, ptr undef, align 2
br i1 undef, label %return, label %bb br i1 %c1, label %return, label %bb
return: ; preds = %bb, %entry return: ; preds = %bb, %entry
ret void ret void
} }

llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll

; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5410 ; PR5410
%0 = type { float, float, float, float } %0 = type { float, float, float, float }
%pln = type { %vec, float } %pln = type { %vec, float }
%vec = type { [4 x float] } %vec = type { [4 x float] }
define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint) { define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint, i1 %c0) {
entry: entry:
br i1 undef, label %bb81, label %bb48 br i1 %c0, label %bb81, label %bb48
bb48: ; preds = %entry bb48: ; preds = %entry
%0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0] %0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0]
ret float 0.000000e+00 ret float 0.000000e+00
bb81: ; preds = %entry bb81: ; preds = %entry
ret float 0.000000e+00 ret float 0.000000e+00
} }
declare arm_aapcs_vfpcc %0 @bbb(ptr nocapture, ptr nocapture, ptr nocapture) nounwind declare arm_aapcs_vfpcc %0 @bbb(ptr nocapture, ptr nocapture, ptr nocapture) nounwind

llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll

; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5411 ; PR5411
%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 } %bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
%baz = type { ptr, i32 } %baz = type { ptr, i32 }
%foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz } %foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] } %quad = type { [4 x float] }
%quux = type { %quad, %quad } %quux = type { %quad, %quad }
%quuz = type { [4 x ptr], [4 x float], i32 } %quuz = type { [4 x ptr], [4 x float], i32 }
define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %c0) {
entry: entry:
br i1 undef, label %bb85, label %bb br i1 %c0, label %bb85, label %bb
bb: ; preds = %entry bb: ; preds = %entry
%0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; <ptr> [#uses=2] %0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; <ptr> [#uses=2]
%1 = load float, ptr undef, align 4 ; <float> [#uses=1] %1 = load float, ptr undef, align 4 ; <float> [#uses=1]
%2 = fsub float 0.000000e+00, undef ; <float> [#uses=2] %2 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
%3 = fmul float 0.000000e+00, undef ; <float> [#uses=1] %3 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
%4 = load float, ptr %0, align 4 ; <float> [#uses=3] %4 = load float, ptr %0, align 4 ; <float> [#uses=3]
%5 = fmul float %4, %2 ; <float> [#uses=1] %5 = fmul float %4, %2 ; <float> [#uses=1]
Show All 21 Lines

llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll

; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5412 ; PR5412
%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 } %bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
%baz = type { ptr, i32 } %baz = type { ptr, i32 }
%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz } %foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] } %quad = type { [4 x float] }
%quux = type { [4 x ptr], [4 x float], i32 } %quux = type { [4 x ptr], [4 x float], i32 }
%quuz = type { %quad, %quad } %quuz = type { %quad, %quad }
define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %c0, i1 %c1) {
entry: entry:
br i1 undef, label %bb85, label %bb br i1 %c0, label %bb85, label %bb
bb: ; preds = %entry bb: ; preds = %entry
br i1 undef, label %bb3.i, label %bb2.i br i1 %c1, label %bb3.i, label %bb2.i
bb2.i: ; preds = %bb bb2.i: ; preds = %bb
br label %bb3.i br label %bb3.i
bb3.i: ; preds = %bb2.i, %bb bb3.i: ; preds = %bb2.i, %bb
%0 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=0] %0 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=0]
%1 = fsub float 0.000000e+00, undef ; <float> [#uses=1] %1 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
%2 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=2] %2 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=2]
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll

; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s ; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5412 ; PR5412
; rdar://7384107 ; rdar://7384107
%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 } %bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
%baz = type { ptr, i32 } %baz = type { ptr, i32 }
%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz } %foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] } %quad = type { [4 x float] }
%quux = type { [4 x ptr], [4 x float], i32 } %quux = type { [4 x ptr], [4 x float], i32 }
%quuz = type { %quad, %quad } %quuz = type { %quad, %quad }
define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) { define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced, i1 %c0) {
entry: entry:
%0 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2] %0 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2]
br i1 false, label %bb85, label %bb br i1 false, label %bb85, label %bb
bb: ; preds = %entry bb: ; preds = %entry
br i1 undef, label %bb3.i, label %bb2.i br i1 %c0, label %bb3.i, label %bb2.i
bb2.i: ; preds = %bb bb2.i: ; preds = %bb
br label %bb3.i br label %bb3.i
bb3.i: ; preds = %bb2.i, %bb bb3.i: ; preds = %bb2.i, %bb
%1 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1] %1 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1]
%2 = fsub float 0.000000e+00, undef ; <float> [#uses=1] %2 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
%3 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1] %3 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll

; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi
define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
%1 = load i32, ptr undef ; <i32> [#uses=1] %1 = load i32, ptr undef ; <i32> [#uses=1]
%2 = sub i32 %1, 48 ; <i32> [#uses=1] %2 = sub i32 %1, 48 ; <i32> [#uses=1]
br i1 undef, label %stack_overflow, label %no_overflow br i1 %c0, label %stack_overflow, label %no_overflow
stack_overflow: ; preds = %0 stack_overflow: ; preds = %0
unreachable unreachable
no_overflow: ; preds = %0 no_overflow: ; preds = %0
%frame = inttoptr i32 %2 to ptr ; <ptr> [#uses=4] %frame = inttoptr i32 %2 to ptr ; <ptr> [#uses=4]
%3 = load i32, ptr undef ; <i32> [#uses=1] %3 = load i32, ptr undef ; <i32> [#uses=1]
%4 = load i32, ptr null ; <i32> [#uses=1] %4 = load i32, ptr null ; <i32> [#uses=1]
%5 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; <ptr> [#uses=1] %5 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; <ptr> [#uses=1]
%6 = load ptr, ptr %5 ; <ptr> [#uses=1] %6 = load ptr, ptr %5 ; <ptr> [#uses=1]
%7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; <ptr> [#uses=1] %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; <ptr> [#uses=1]
%8 = load i32, ptr %7 ; <i32> [#uses=1] %8 = load i32, ptr %7 ; <i32> [#uses=1]
br i1 undef, label %bci_13, label %bci_4 br i1 %c1, label %bci_13, label %bci_4
bci_13: ; preds = %no_overflow bci_13: ; preds = %no_overflow
br i1 undef, label %bci_30, label %bci_21 br i1 %c2, label %bci_30, label %bci_21
bci_30: ; preds = %bci_13 bci_30: ; preds = %bci_13
br i1 undef, label %bci_46, label %bci_35 br i1 %c3, label %bci_46, label %bci_35
bci_46: ; preds = %bci_30 bci_46: ; preds = %bci_30
%9 = sub i32 %4, %3 ; <i32> [#uses=1] %9 = sub i32 %4, %3 ; <i32> [#uses=1]
%10 = load ptr, ptr null ; <ptr> [#uses=1] %10 = load ptr, ptr null ; <ptr> [#uses=1]
%base_pc7 = load i32, ptr undef ; <i32> [#uses=2] %base_pc7 = load i32, ptr undef ; <i32> [#uses=2]
%11 = add i32 %base_pc7, 0 ; <i32> [#uses=1] %11 = add i32 %base_pc7, 0 ; <i32> [#uses=1]
%12 = inttoptr i32 %11 to ptr ; <ptr> [#uses=1] %12 = inttoptr i32 %11 to ptr ; <ptr> [#uses=1]
%entry_point = load ptr, ptr %12 ; <ptr> [#uses=1] %entry_point = load ptr, ptr %12 ; <ptr> [#uses=1]
%13 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 1 ; <ptr> [#uses=1] %13 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 1 ; <ptr> [#uses=1]
%14 = ptrtoint ptr %13 to i32 ; <i32> [#uses=1] %14 = ptrtoint ptr %13 to i32 ; <i32> [#uses=1]
store i32 %14, ptr undef store i32 %14, ptr undef
%15 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 2 ; <ptr> [#uses=1] %15 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 2 ; <ptr> [#uses=1]
store i32 %8, ptr %15 store i32 %8, ptr %15
store i32 %9, ptr undef store i32 %9, ptr undef
store ptr %method, ptr undef store ptr %method, ptr undef
%16 = add i32 %base_pc, 20 ; <i32> [#uses=1] %16 = add i32 %base_pc, 20 ; <i32> [#uses=1]
store i32 %16, ptr undef store i32 %16, ptr undef
store ptr %6, ptr undef store ptr %6, ptr undef
call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread) call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread)
br i1 undef, label %no_exception, label %exception br i1 %c4, label %no_exception, label %exception
exception: ; preds = %bci_46 exception: ; preds = %bci_46
ret void ret void
no_exception: ; preds = %bci_46 no_exception: ; preds = %bci_46
ret void ret void
bci_35: ; preds = %bci_30 bci_35: ; preds = %bci_30
ret void ret void
bci_21: ; preds = %bci_13 bci_21: ; preds = %bci_13
ret void ret void
bci_4: ; preds = %no_overflow bci_4: ; preds = %no_overflow
ret void ret void
} }

llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll

; RUN: llc -mtriple=arm-eabi %s -o /dev/null ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) { define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread, i1 %c0, i1 %c1, i1 %c2) {
%1 = sub i32 undef, 48 ; <i32> [#uses=1] %1 = sub i32 undef, 48 ; <i32> [#uses=1]
br i1 undef, label %stack_overflow, label %no_overflow br i1 %c0, label %stack_overflow, label %no_overflow
stack_overflow: ; preds = %0 stack_overflow: ; preds = %0
unreachable unreachable
no_overflow: ; preds = %0 no_overflow: ; preds = %0
%frame = inttoptr i32 %1 to ptr ; <ptr> [#uses=4] %frame = inttoptr i32 %1 to ptr ; <ptr> [#uses=4]
%2 = load i32, ptr null ; <i32> [#uses=2] %2 = load i32, ptr null ; <i32> [#uses=2]
%3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; <ptr> [#uses=1] %3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; <ptr> [#uses=1]
%4 = load i32, ptr %3 ; <i32> [#uses=2] %4 = load i32, ptr %3 ; <i32> [#uses=2]
%5 = load ptr, ptr undef ; <ptr> [#uses=2] %5 = load ptr, ptr undef ; <ptr> [#uses=2]
br i1 undef, label %bci_13, label %bci_4 br i1 %c1, label %bci_13, label %bci_4
bci_13: ; preds = %no_overflow bci_13: ; preds = %no_overflow
br i1 undef, label %bci_30, label %bci_21 br i1 %c2, label %bci_30, label %bci_21
bci_30: ; preds = %bci_13 bci_30: ; preds = %bci_13
%6 = icmp sle i32 %2, %4 ; <i1> [#uses=1] %6 = icmp sle i32 %2, %4 ; <i1> [#uses=1]
br i1 %6, label %bci_46, label %bci_35 br i1 %6, label %bci_46, label %bci_35
bci_46: ; preds = %bci_30 bci_46: ; preds = %bci_30
store ptr %method, ptr undef store ptr %method, ptr undef
br i1 false, label %no_exception, label %exception br i1 false, label %no_exception, label %exception
Show All 26 Lines

llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll

; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values. ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.
define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction) nounwind { define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction, i1 %c0) nounwind {
entry: entry:
%.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1]
%0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1]
%1 = fsub <4 x float> %0, undef ; <<4 x float>> [#uses=1] %1 = fsub <4 x float> %0, undef ; <<4 x float>> [#uses=1]
%2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=1] %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=1]
%3 = shufflevector <4 x float> undef, <4 x float> %2, <4 x i32> <i32 2, i32 3, i32 6, i32 7> ; <<4 x float>> [#uses=1] %3 = shufflevector <4 x float> undef, <4 x float> %2, <4 x i32> <i32 2, i32 3, i32 6, i32 7> ; <<4 x float>> [#uses=1]
%4 = fmul <4 x float> %3, <float 0.000000e+00, float 0x3FED906BC0000000, float 0x3FE6A09E60000000, float 0xBFD87DE2A0000000> ; <<4 x float>> [#uses=1] %4 = fmul <4 x float> %3, <float 0.000000e+00, float 0x3FED906BC0000000, float 0x3FE6A09E60000000, float 0xBFD87DE2A0000000> ; <<4 x float>> [#uses=1]
%5 = fadd <4 x float> undef, %4 ; <<4 x float>> [#uses=1] %5 = fadd <4 x float> undef, %4 ; <<4 x float>> [#uses=1]
%6 = fadd <4 x float> undef, %5 ; <<4 x float>> [#uses=1] %6 = fadd <4 x float> undef, %5 ; <<4 x float>> [#uses=1]
%7 = fadd <4 x float> undef, %6 ; <<4 x float>> [#uses=1] %7 = fadd <4 x float> undef, %6 ; <<4 x float>> [#uses=1]
br i1 undef, label %bb4, label %bb3 br i1 %c0, label %bb4, label %bb3
bb3: ; preds = %entry bb3: ; preds = %entry
%8 = shufflevector <4 x float> undef, <4 x float> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=0] %8 = shufflevector <4 x float> undef, <4 x float> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=0]
ret void ret void
bb4: ; preds = %entry bb4: ; preds = %entry
ret void ret void
} }

llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll

; RUN: llc -mtriple=arm-eabi -mcpu=arm1136jf-s %s -o /dev/null ; RUN: llc -mtriple=arm-eabi -mcpu=arm1136jf-s %s -o /dev/null
; Radar 7854640 ; Radar 7854640
define void @test() nounwind { define void @test(i1 %c0) nounwind {
bb: bb:
br i1 undef, label %bb9, label %bb10 br i1 %c0, label %bb9, label %bb10
bb9: bb9:
%tmp63 = bitcast <4 x float> zeroinitializer to i128 %tmp63 = bitcast <4 x float> zeroinitializer to i128
%tmp64 = trunc i128 %tmp63 to i32 %tmp64 = trunc i128 %tmp63 to i32
br label %bb10 br label %bb10
bb10: bb10:
%0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ] %0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]
ret void ret void
} }

llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll

; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs ; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs
target triple = "arm-pc-linux-gnu" target triple = "arm-pc-linux-gnu"
; This test case would accidentally use the same physreg for two virtregs ; This test case would accidentally use the same physreg for two virtregs
; because allocVirtReg forgot to check if registers were already used in the ; because allocVirtReg forgot to check if registers were already used in the
; instruction. ; instruction.
; This caused the RegScavenger to complain, but -verify-machineinstrs also ; This caused the RegScavenger to complain, but -verify-machineinstrs also
; catches it. ; catches it.
%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
@search = external global %struct.CHESS_POSITION ; <ptr> [#uses=1] @search = external global %struct.CHESS_POSITION ; <ptr> [#uses=1]
@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <ptr> [#uses=1] @bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <ptr> [#uses=1]
declare fastcc i32 @FirstOne() declare fastcc i32 @FirstOne()
define fastcc void @Evaluate() { define fastcc void @Evaluate(i1 %c0) {
entry: entry:
br i1 false, label %cond_false186, label %cond_true br i1 false, label %cond_false186, label %cond_true
cond_true: ; preds = %entry cond_true: ; preds = %entry
ret void ret void
cond_false186: ; preds = %entry cond_false186: ; preds = %entry
br i1 false, label %cond_true293, label %bb203 br i1 false, label %cond_true293, label %bb203
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesbb1567: ; preds = %cond_true1254
%shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1] %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
%tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1] %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1]
%tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1] %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1]
%tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1] %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1]
%gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1] %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1]
%tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <ptr> [#uses=1] %tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <ptr> [#uses=1]
%tmp1599 = load i32, ptr %tmp1598 ; <i32> [#uses=1] %tmp1599 = load i32, ptr %tmp1598 ; <i32> [#uses=1]
%tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1] %tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1]
br i1 undef, label %cond_next1637, label %cond_true1607 br i1 %c0, label %cond_next1637, label %cond_true1607
cond_true1607: ; preds = %bb1567 cond_true1607: ; preds = %bb1567
ret void ret void
cond_next1637: ; preds = %bb1567 cond_next1637: ; preds = %bb1567
%tmp1662 = sub i32 %tmp1602, 0 ; <i32> [#uses=0] %tmp1662 = sub i32 %tmp1602, 0 ; <i32> [#uses=0]
ret void ret void
} }

llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll

; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast
; rdar://problem/7948106 ; rdar://problem/7948106
;; This test would spill %R4 before the call to zz, but it forgot to move the ;; This test would spill %R4 before the call to zz, but it forgot to move the
; 'last use' marker to the spill. ; 'last use' marker to the spill.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv6-apple-darwin" target triple = "armv6-apple-darwin"
%struct.q = type { i32, i32 } %struct.q = type { i32, i32 }
@.str = external constant [1 x i8] ; <ptr> [#uses=1] @.str = external constant [1 x i8] ; <ptr> [#uses=1]
define void @yy(ptr %qq) nounwind { define void @yy(ptr %qq, i1 %c0) nounwind {
entry: entry:
%vla6 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1] %vla6 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%vla10 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%vla14 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1] %vla14 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%vla18 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1] %vla18 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%tmp21 = load i32, ptr undef ; <i32> [#uses=1] %tmp21 = load i32, ptr undef ; <i32> [#uses=1]
%0 = mul i32 1, %tmp21 ; <i32> [#uses=1] %0 = mul i32 1, %tmp21 ; <i32> [#uses=1]
%vla22 = alloca i8, i32 %0, align 1 ; <ptr> [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; <ptr> [#uses=1]
call void (...) @zz(ptr @.str, i32 2, i32 1) call void (...) @zz(ptr @.str, i32 2, i32 1)
br i1 undef, label %if.then, label %if.end36 br i1 %c0, label %if.then, label %if.end36
if.then: ; preds = %entry if.then: ; preds = %entry
%call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; <i32> [#uses=0] %call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; <i32> [#uses=0]
%call35 = call i32 (...) @x(ptr undef, ptr %vla14, ptr %vla18, ptr %vla22, i32 undef) ; <i32> [#uses=0] %call35 = call i32 (...) @x(ptr undef, ptr %vla14, ptr %vla18, ptr %vla22, i32 undef) ; <i32> [#uses=0]
unreachable unreachable
if.end36: ; preds = %entry if.end36: ; preds = %entry
ret void ret void
} }
declare void @zz(...) declare void @zz(...)
declare i32 @x(...) declare i32 @x(...)

llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll

; RUN: llc < %s -mtriple=armv7-apple-darwin -O3 -mcpu=arm1136jf-s ; RUN: llc < %s -mtriple=armv7-apple-darwin -O3 -mcpu=arm1136jf-s
; PR7421 ; PR7421
%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
%struct.FILE = type { ptr } %struct.FILE = type { ptr }
%struct.tilebox = type { ptr, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.tilebox = type { ptr, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.cellbox = type { ptr, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, ptr, ptr, [8 x ptr] } %struct.cellbox = type { ptr, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, ptr, ptr, [8 x ptr] }
%struct.termbox = type { ptr, i32, i32, i32, i32, i32 } %struct.termbox = type { ptr, i32, i32, i32, i32, i32 }
@.str2708 = external constant [14 x i8], align 4 ; <ptr> [#uses=1] @.str2708 = external constant [14 x i8], align 4 ; <ptr> [#uses=1]
define void @TW_oldinput(ptr nocapture %fp) nounwind { define void @TW_oldinput(ptr nocapture %fp, i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind {
entry: entry:
%xcenter = alloca i32, align 4 ; <ptr> [#uses=2] %xcenter = alloca i32, align 4 ; <ptr> [#uses=2]
%0 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; <i32> [#uses=1] %0 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 4 ; <i1> [#uses=1] %1 = icmp eq i32 %0, 4 ; <i1> [#uses=1]
br i1 %1, label %bb, label %return br i1 %1, label %bb, label %return
bb: ; preds = %bb445, %entry bb: ; preds = %bb445, %entry
%2 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2] %2 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2]
%3 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 3 ; <ptr> [#uses=1] %3 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 3 ; <ptr> [#uses=1]
store i32 undef, ptr %3, align 4 store i32 undef, ptr %3, align 4
%4 = load i32, ptr undef, align 4 ; <i32> [#uses=3] %4 = load i32, ptr undef, align 4 ; <i32> [#uses=3]
%5 = icmp eq i32 undef, 1 ; <i1> [#uses=1] %5 = icmp eq i32 undef, 1 ; <i1> [#uses=1]
br i1 %5, label %bb10, label %bb445 br i1 %5, label %bb10, label %bb445
bb10: ; preds = %bb bb10: ; preds = %bb
br i1 undef, label %bb11, label %bb445 br i1 %c0, label %bb11, label %bb445
bb11: ; preds = %bb10 bb11: ; preds = %bb10
%6 = load ptr, ptr undef, align 4 ; <ptr> [#uses=3] %6 = load ptr, ptr undef, align 4 ; <ptr> [#uses=3]
%7 = load ptr, ptr null, align 4 ; <ptr> [#uses=1] %7 = load ptr, ptr null, align 4 ; <ptr> [#uses=1]
%8 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 13 ; <ptr> [#uses=1] %8 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 13 ; <ptr> [#uses=1]
%9 = load i32, ptr %8, align 4 ; <i32> [#uses=3] %9 = load i32, ptr %8, align 4 ; <i32> [#uses=3]
%10 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 15 ; <ptr> [#uses=1] %10 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 15 ; <ptr> [#uses=1]
%11 = load i32, ptr %10, align 4 ; <i32> [#uses=1] %11 = load i32, ptr %10, align 4 ; <i32> [#uses=1]
br i1 false, label %bb12, label %bb13 br i1 false, label %bb12, label %bb13
bb12: ; preds = %bb11 bb12: ; preds = %bb11
unreachable unreachable
bb13: ; preds = %bb11 bb13: ; preds = %bb11
%iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2] %iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2]
%12 = sub nsw i32 0, %9 ; <i32> [#uses=1] %12 = sub nsw i32 0, %9 ; <i32> [#uses=1]
%13 = sitofp i32 %12 to double ; <double> [#uses=1] %13 = sitofp i32 %12 to double ; <double> [#uses=1]
%14 = fdiv double %13, 0.000000e+00 ; <double> [#uses=1] %14 = fdiv double %13, 0.000000e+00 ; <double> [#uses=1]
%15 = fptosi double %14 to i32 ; <i32> [#uses=1] %15 = fptosi double %14 to i32 ; <i32> [#uses=1]
%iftmp.41.0.in = add i32 0, %15 ; <i32> [#uses=1] %iftmp.41.0.in = add i32 0, %15 ; <i32> [#uses=1]
%iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3] %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3]
br i1 undef, label %bb43.loopexit, label %bb21 br i1 %c1, label %bb43.loopexit, label %bb21
bb21: ; preds = %bb13 bb21: ; preds = %bb13
%16 = fptosi double undef to i32 ; <i32> [#uses=1] %16 = fptosi double undef to i32 ; <i32> [#uses=1]
%17 = fsub double undef, 0.000000e+00 ; <double> [#uses=1] %17 = fsub double undef, 0.000000e+00 ; <double> [#uses=1]
%not.460 = fcmp oge double %17, 5.000000e-01 ; <i1> [#uses=1] %not.460 = fcmp oge double %17, 5.000000e-01 ; <i1> [#uses=1]
%18 = zext i1 %not.460 to i32 ; <i32> [#uses=1] %18 = zext i1 %not.460 to i32 ; <i32> [#uses=1]
%iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; <i32> [#uses=1] %iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; <i32> [#uses=1]
%19 = add i32 %iftmp.42.0, %18 ; <i32> [#uses=1] %19 = add i32 %iftmp.42.0, %18 ; <i32> [#uses=1]
Show All 33 Linesbb36: ; preds = %bb43.loopexit, %bb36
%40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1] %40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1]
store i32 %40, ptr undef, align 4 store i32 %40, ptr undef, align 4
%41 = getelementptr inbounds %struct.termbox, ptr %termptr.0478, i32 0, i32 0 ; <ptr> [#uses=1] %41 = getelementptr inbounds %struct.termbox, ptr %termptr.0478, i32 0, i32 0 ; <ptr> [#uses=1]
%42 = load ptr, ptr %41, align 4 ; <ptr> [#uses=2] %42 = load ptr, ptr %41, align 4 ; <ptr> [#uses=2]
%43 = icmp eq ptr %42, null ; <i1> [#uses=1] %43 = icmp eq ptr %42, null ; <i1> [#uses=1]
br i1 %43, label %bb52.loopexit, label %bb36 br i1 %43, label %bb52.loopexit, label %bb36
bb43.loopexit: ; preds = %bb21, %bb13 bb43.loopexit: ; preds = %bb21, %bb13
br i1 undef, label %bb52.loopexit, label %bb36 br i1 %c2, label %bb52.loopexit, label %bb36
bb52.loopexit: ; preds = %bb43.loopexit, %bb36 bb52.loopexit: ; preds = %bb43.loopexit, %bb36
%44 = icmp eq i32 %4, 0 ; <i1> [#uses=1] %44 = icmp eq i32 %4, 0 ; <i1> [#uses=1]
br i1 %44, label %bb.nph485, label %bb54 br i1 %44, label %bb.nph485, label %bb54
bb54: ; preds = %bb52.loopexit bb54: ; preds = %bb52.loopexit
switch i32 %4, label %bb62 [ switch i32 %4, label %bb62 [
i32 2, label %bb56 i32 2, label %bb56
Show All 19 Lines
bb249: ; preds = %bb248 bb249: ; preds = %bb248
%46 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 21, i32 undef ; <ptr> [#uses=1] %46 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 21, i32 undef ; <ptr> [#uses=1]
%47 = load ptr, ptr %46, align 4 ; <ptr> [#uses=1] %47 = load ptr, ptr %46, align 4 ; <ptr> [#uses=1]
%48 = getelementptr inbounds %struct.tilebox, ptr %47, i32 0, i32 11 ; <ptr> [#uses=1] %48 = getelementptr inbounds %struct.tilebox, ptr %47, i32 0, i32 11 ; <ptr> [#uses=1]
store i32 undef, ptr %48, align 4 store i32 undef, ptr %48, align 4
unreachable unreachable
bb322: ; preds = %bb248 bb322: ; preds = %bb248
br i1 undef, label %bb248, label %bb445 br i1 %c3, label %bb248, label %bb445
bb445: ; preds = %bb322, %bb10, %bb bb445: ; preds = %bb322, %bb10, %bb
%49 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; <i32> [#uses=1] %49 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; <i32> [#uses=1]
%50 = icmp eq i32 %49, 4 ; <i1> [#uses=1] %50 = icmp eq i32 %49, 4 ; <i1> [#uses=1]
br i1 %50, label %bb, label %return br i1 %50, label %bb, label %return
return: ; preds = %bb445, %entry return: ; preds = %bb445, %entry
ret void ret void
} }
declare i32 @fscanf(ptr nocapture, ptr nocapture, ...) nounwind declare i32 @fscanf(ptr nocapture, ptr nocapture, ...) nounwind

llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll

; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
declare noalias ptr @malloc(i32) nounwind declare noalias ptr @malloc(i32) nounwind
define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels) nounwind { define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7) nounwind {
entry: entry:
br i1 undef, label %bb3.i, label %bb3 br i1 %c0, label %bb3.i, label %bb3
bb3.i: ; preds = %entry bb3.i: ; preds = %entry
unreachable unreachable
gl_error.exit: ; preds = %bb22 gl_error.exit: ; preds = %bb22
ret void ret void
bb3: ; preds = %entry bb3: ; preds = %entry
br i1 false, label %bb5, label %bb4 br i1 false, label %bb5, label %bb4
bb4: ; preds = %bb3 bb4: ; preds = %bb3
br label %bb5 br label %bb5
bb5: ; preds = %bb4, %bb3 bb5: ; preds = %bb4, %bb3
br i1 undef, label %bb19, label %bb22 br i1 %c1, label %bb19, label %bb22
bb19: ; preds = %bb5 bb19: ; preds = %bb5
switch i32 %type, label %bb3.i6.i [ switch i32 %type, label %bb3.i6.i [
i32 5120, label %bb1.i13 i32 5120, label %bb1.i13
i32 5121, label %bb1.i13 i32 5121, label %bb1.i13
i32 6656, label %bb9.i.i6 i32 6656, label %bb9.i.i6
] ]
bb9.i.i6: ; preds = %bb19 bb9.i.i6: ; preds = %bb19
br label %bb1.i13 br label %bb1.i13
bb3.i6.i: ; preds = %bb19 bb3.i6.i: ; preds = %bb19
unreachable unreachable
bb1.i13: ; preds = %bb9.i.i6, %bb19, %bb19 bb1.i13: ; preds = %bb9.i.i6, %bb19, %bb19
br i1 undef, label %bb3.i17, label %bb2.i16 br i1 %c2, label %bb3.i17, label %bb2.i16
bb2.i16: ; preds = %bb1.i13 bb2.i16: ; preds = %bb1.i13
unreachable unreachable
bb3.i17: ; preds = %bb1.i13 bb3.i17: ; preds = %bb1.i13
br i1 undef, label %bb4.i18, label %bb23.i br i1 %c3, label %bb4.i18, label %bb23.i
bb4.i18: ; preds = %bb3.i17 bb4.i18: ; preds = %bb3.i17
%0 = mul nsw i32 %height, %width %0 = mul nsw i32 %height, %width
%1 = and i32 %0, 7 %1 = and i32 %0, 7
%not..i = icmp ne i32 %1, 0 %not..i = icmp ne i32 %1, 0
%2 = zext i1 %not..i to i32 %2 = zext i1 %not..i to i32
%storemerge2.i = add i32 0, %2 %storemerge2.i = add i32 0, %2
%3 = call noalias ptr @malloc(i32 %storemerge2.i) nounwind %3 = call noalias ptr @malloc(i32 %storemerge2.i) nounwind
br i1 undef, label %bb3.i9, label %bb9.i br i1 %c4, label %bb3.i9, label %bb9.i
bb9.i: ; preds = %bb4.i18 bb9.i: ; preds = %bb4.i18
br i1 undef, label %bb13.i19, label %bb.i24.i br i1 %c5, label %bb13.i19, label %bb.i24.i
bb13.i19: ; preds = %bb9.i bb13.i19: ; preds = %bb9.i
br i1 undef, label %bb14.i20, label %bb15.i br i1 %c6, label %bb14.i20, label %bb15.i
bb14.i20: ; preds = %bb13.i19 bb14.i20: ; preds = %bb13.i19
unreachable unreachable
bb15.i: ; preds = %bb13.i19 bb15.i: ; preds = %bb13.i19
unreachable unreachable
bb.i24.i: ; preds = %bb.i24.i, %bb9.i bb.i24.i: ; preds = %bb.i24.i, %bb9.i
%storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ] %storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ]
%4 = add i32 %storemerge1.i21.i, 1 %4 = add i32 %storemerge1.i21.i, 1
%exitcond47.i = icmp eq i32 %4, %storemerge2.i %exitcond47.i = icmp eq i32 %4, %storemerge2.i
br i1 %exitcond47.i, label %bb22, label %bb.i24.i br i1 %exitcond47.i, label %bb22, label %bb.i24.i
bb23.i: ; preds = %bb3.i17 bb23.i: ; preds = %bb3.i17
unreachable unreachable
bb3.i9: ; preds = %bb4.i18 bb3.i9: ; preds = %bb4.i18
unreachable unreachable
bb22: ; preds = %bb.i24.i, %bb5 bb22: ; preds = %bb.i24.i, %bb5
br i1 undef, label %gl_error.exit, label %bb23 br i1 %c7, label %gl_error.exit, label %bb23
bb23: ; preds = %bb22 bb23: ; preds = %bb22
ret void ret void
} }

llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll

; RUN: llc < %s -verify-machineinstrs ; RUN: llc < %s -verify-machineinstrs
; PR8612 ; PR8612
; ;
; This test has an inline asm with early-clobber arguments. ; This test has an inline asm with early-clobber arguments.
; It is big enough that one of the early clobber registers is spilled. ; It is big enough that one of the early clobber registers is spilled.
; ;
; All the spillers would get the live ranges wrong when spilling an early ; All the spillers would get the live ranges wrong when spilling an early
; clobber, allowing the undef register to be allocated to the same register as ; clobber, allowing the undef register to be allocated to the same register as
; the early clobber. ; the early clobber.
; ;
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
target triple = "armv7-eabi" target triple = "armv7-eabi"
%0 = type { i32, i32 } %0 = type { i32, i32 }
define void @foo(ptr %in) nounwind { define void @foo(ptr %in, i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
br label %bb.i br label %bb.i
bb.i: ; preds = %bb.i, %entry bb.i: ; preds = %bb.i, %entry
br i1 undef, label %bb10.preheader.i, label %bb.i br i1 %c0, label %bb10.preheader.i, label %bb.i
bb10.preheader.i: ; preds = %bb.i bb10.preheader.i: ; preds = %bb.i
br label %bb10.i br label %bb10.i
bb10.i: ; preds = %bb10.i, %bb10.preheader.i bb10.i: ; preds = %bb10.i, %bb10.preheader.i
br i1 undef, label %bb27.i, label %bb10.i br i1 %c1, label %bb27.i, label %bb10.i
bb27.i: ; preds = %bb10.i bb27.i: ; preds = %bb10.i
br label %bb28.i br label %bb28.i
bb28.i: ; preds = %bb28.i, %bb27.i bb28.i: ; preds = %bb28.i, %bb27.i
br i1 undef, label %presymmetry.exit, label %bb28.i br i1 %c2, label %presymmetry.exit, label %bb28.i
presymmetry.exit: ; preds = %bb28.i presymmetry.exit: ; preds = %bb28.i
%tmp175387 = or i32 undef, 12 %tmp175387 = or i32 undef, 12
%scevgep101.i = getelementptr i32, ptr %in, i32 undef %scevgep101.i = getelementptr i32, ptr %in, i32 undef
%tmp189401 = or i32 undef, 7 %tmp189401 = or i32 undef, 7
%scevgep97.i = getelementptr i32, ptr %in, i32 undef %scevgep97.i = getelementptr i32, ptr %in, i32 undef
%tmp198410 = or i32 undef, 1 %tmp198410 = or i32 undef, 1
%scevgep.i48 = getelementptr i32, ptr %in, i32 undef %scevgep.i48 = getelementptr i32, ptr %in, i32 undef
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll

; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv5e-none-linux-gnueabi | FileCheck %s ; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv5e-none-linux-gnueabi | FileCheck %s
; PR8986: PostRA antidependence breaker must respect "earlyclobber". ; PR8986: PostRA antidependence breaker must respect "earlyclobber".
; armv5e generates mulv5 that cannot used the same reg for src/dest. ; armv5e generates mulv5 that cannot used the same reg for src/dest.
; ModuleID = '<stdin>' ; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
target triple = "armv5e-none-linux-gnueabi" target triple = "armv5e-none-linux-gnueabi"
define hidden fastcc void @storeAtts() nounwind { define hidden fastcc void @storeAtts(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8) nounwind {
entry: entry:
%.SV116 = alloca ptr %.SV116 = alloca ptr
br i1 undef, label %meshBB520, label %meshBB464 br i1 %c0, label %meshBB520, label %meshBB464
bb15: ; preds = %meshBB424 bb15: ; preds = %meshBB424
br i1 undef, label %bb216, label %meshBB396 br i1 %c1, label %bb216, label %meshBB396
bb22: ; preds = %meshBB396 bb22: ; preds = %meshBB396
br label %cBB564 br label %cBB564
cBB564: ; preds = %cBB564, %bb22 cBB564: ; preds = %cBB564, %bb22
br label %cBB564 br label %cBB564
poolStoreString.exit.thread: ; preds = %meshBB424 poolStoreString.exit.thread: ; preds = %meshBB424
ret void ret void
bb78: ; preds = %meshBB412 bb78: ; preds = %meshBB412
unreachable unreachable
bb129: ; preds = %meshBB540 bb129: ; preds = %meshBB540
br i1 undef, label %bb131.loopexit, label %meshBB540 br i1 %c2, label %bb131.loopexit, label %meshBB540
bb131.loopexit: ; preds = %bb129 bb131.loopexit: ; preds = %bb129
br label %bb131 br label %bb131
bb131: ; preds = %bb135, %bb131.loopexit bb131: ; preds = %bb135, %bb131.loopexit
br i1 undef, label %bb134, label %meshBB396 br i1 %c3, label %bb134, label %meshBB396
bb134: ; preds = %bb131 bb134: ; preds = %bb131
unreachable unreachable
bb135: ; preds = %meshBB396 bb135: ; preds = %meshBB396
%uriHash.1.phi.load = load i32, ptr undef %uriHash.1.phi.load = load i32, ptr undef
%.load120 = load ptr, ptr %.SV116 %.load120 = load ptr, ptr %.SV116
%.phi24 = load i8, ptr null %.phi24 = load i8, ptr null
Show All 14 Lines
bb212: ; preds = %meshBB540 bb212: ; preds = %meshBB540
unreachable unreachable
bb216: ; preds = %bb15 bb216: ; preds = %bb15
ret void ret void
meshBB396: ; preds = %bb131, %bb15 meshBB396: ; preds = %bb131, %bb15
br i1 undef, label %bb135, label %bb22 br i1 %c4, label %bb135, label %bb22
meshBB412: ; preds = %meshBB464 meshBB412: ; preds = %meshBB464
br i1 undef, label %meshBB504, label %bb78 br i1 %c5, label %meshBB504, label %bb78
meshBB424: ; preds = %meshBB464 meshBB424: ; preds = %meshBB464
br i1 undef, label %poolStoreString.exit.thread, label %bb15 br i1 %c6, label %poolStoreString.exit.thread, label %bb15
meshBB464: ; preds = %entry meshBB464: ; preds = %entry
br i1 undef, label %meshBB424, label %meshBB412 br i1 %c7, label %meshBB424, label %meshBB412
meshBB472: ; preds = %meshBB504, %bb135 meshBB472: ; preds = %meshBB504, %bb135
unreachable unreachable
meshBB504: ; preds = %meshBB412 meshBB504: ; preds = %meshBB412
br label %meshBB472 br label %meshBB472
meshBB520: ; preds = %entry meshBB520: ; preds = %entry
br label %meshBB540 br label %meshBB540
meshBB540: ; preds = %meshBB520, %bb129 meshBB540: ; preds = %meshBB520, %bb129
br i1 undef, label %bb212, label %bb129 br i1 %c8, label %bb212, label %bb129
} }

llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll

; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -frame-pointer=all -mcpu=cortex-a8 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -frame-pointer=all -mcpu=cortex-a8
; rdar://9117613 ; rdar://9117613
%struct.mo = type { i32, ptr } %struct.mo = type { i32, ptr }
%struct.mo_pops = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr } %struct.mo_pops = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%struct.ui = type { ptr, ptr, i32, ptr, ptr, i64, ptr, ptr, ptr } %struct.ui = type { ptr, ptr, i32, ptr, ptr, i64, ptr, ptr, ptr }
define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize) nounwind { define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize, i1 %c0, i1 %c1, i1 %c2) nounwind {
entry: entry:
br i1 undef, label %bb1, label %bb br i1 %c0, label %bb1, label %bb
bb: ; preds = %entry bb: ; preds = %entry
unreachable unreachable
bb1: ; preds = %entry bb1: ; preds = %entry
%0 = call ptr @vn_pp_to_ui(ptr undef) nounwind %0 = call ptr @vn_pp_to_ui(ptr undef) nounwind
call void @llvm.memset.p0.i32(ptr align 4 undef, i8 0, i32 40, i1 false) call void @llvm.memset.p0.i32(ptr align 4 undef, i8 0, i32 40, i1 false)
store ptr undef, ptr %0, align 4 store ptr undef, ptr %0, align 4
%1 = getelementptr inbounds %struct.ui, ptr %0, i32 0, i32 5 %1 = getelementptr inbounds %struct.ui, ptr %0, i32 0, i32 5
%2 = load i64, ptr %1, align 4 %2 = load i64, ptr %1, align 4
%3 = call i32 @mo_create_nnm(ptr undef, i64 %2, ptr undef) nounwind %3 = call i32 @mo_create_nnm(ptr undef, i64 %2, ptr undef) nounwind
br i1 undef, label %bb3, label %bb2 br i1 %c1, label %bb3, label %bb2
bb2: ; preds = %bb1 bb2: ; preds = %bb1
unreachable unreachable
bb3: ; preds = %bb1 bb3: ; preds = %bb1
br i1 undef, label %bb4, label %bb6 br i1 %c2, label %bb4, label %bb6
bb4: ; preds = %bb3 bb4: ; preds = %bb3
%4 = call i32 @vn_size(ptr %vp, ptr %1, ptr undef) nounwind %4 = call i32 @vn_size(ptr %vp, ptr %1, ptr undef) nounwind
unreachable unreachable
bb6: ; preds = %bb3 bb6: ; preds = %bb3
ret i32 0 ret i32 0
} }
declare ptr @vn_pp_to_ui(ptr) declare ptr @vn_pp_to_ui(ptr)
declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
declare i32 @mo_create_nnm(ptr, i64, ptr) declare i32 @mo_create_nnm(ptr, i64, ptr)
declare i32 @vn_size(ptr, ptr, ptr) declare i32 @vn_size(ptr, ptr, ptr)

llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll

; RUN: llc < %s -mtriple=thumbv7-apple-ios ; RUN: llc < %s -mtriple=thumbv7-apple-ios
; If converter was being too cute. It look for root BBs (which don't have ; If converter was being too cute. It look for root BBs (which don't have
; successors) and use inverse depth first search to traverse the BBs. However ; successors) and use inverse depth first search to traverse the BBs. However
; that doesn't work when the CFG has infinite loops. Simply do a linear ; that doesn't work when the CFG has infinite loops. Simply do a linear
; traversal of all BBs work just fine. ; traversal of all BBs work just fine.
; rdar://9344645 ; rdar://9344645
%struct.hc = type { i32, i32, i32, i32 } %struct.hc = type { i32, i32, i32, i32 }
define i32 @t(i32 %type) optsize { define i32 @t(i32 %type, i1 %c0, i1 %c1, i1 %c2, i1 %c3) optsize {
entry: entry:
br i1 undef, label %if.then, label %if.else br i1 %c0, label %if.then, label %if.else
if.then: if.then:
unreachable unreachable
if.else: if.else:
br i1 undef, label %if.then15, label %if.else18 br i1 %c1, label %if.then15, label %if.else18
if.then15: if.then15:
unreachable unreachable
if.else18: if.else18:
switch i32 %type, label %if.else173 [ switch i32 %type, label %if.else173 [
i32 3, label %if.then115 i32 3, label %if.then115
i32 1, label %if.then102 i32 1, label %if.then102
] ]
if.then102: if.then102:
br i1 undef, label %cond.true10.i, label %t.exit br i1 %c2, label %cond.true10.i, label %t.exit
cond.true10.i: cond.true10.i:
br label %t.exit br label %t.exit
t.exit: t.exit:
unreachable unreachable
if.then115: if.then115:
br i1 undef, label %if.else163, label %if.else145 br i1 %c3, label %if.else163, label %if.else145
if.else145: if.else145:
%call150 = call fastcc ptr @foo(ptr undef, i32 34865152) optsize %call150 = call fastcc ptr @foo(ptr undef, i32 34865152) optsize
br label %while.body172 br label %while.body172
if.else163: if.else163:
%call168 = call fastcc ptr @foo(ptr undef, i32 34078720) optsize %call168 = call fastcc ptr @foo(ptr undef, i32 34078720) optsize
br label %while.body172 br label %while.body172
Show All 10 Lines

llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll

; RUN: llc -O3 -mtriple=armv6-apple-darwin -relocation-model=pic < %s ; RUN: llc -O3 -mtriple=armv6-apple-darwin -relocation-model=pic < %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
define void @compdecomp() nounwind { define void @compdecomp(i1 %c0) nounwind {
entry: entry:
%heap = alloca [256 x i32], align 4 %heap = alloca [256 x i32], align 4
br i1 undef, label %bb25.lr.ph, label %bb17 br i1 %c0, label %bb25.lr.ph, label %bb17
bb17: ; preds = %bb17, %entry bb17: ; preds = %bb17, %entry
br label %bb17 br label %bb17
bb25.lr.ph: ; preds = %entry bb25.lr.ph: ; preds = %entry
%0 = sdiv i32 undef, 2 %0 = sdiv i32 undef, 2
br label %bb5.i br label %bb5.i
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llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll

; RUN: llc -mcpu=cortex-a8 < %s ; RUN: llc -mcpu=cortex-a8 < %s
; rdar://problem/10137436: sqlite3 miscompile ; rdar://problem/10137436: sqlite3 miscompile
; ;
; CHECK: subs ; CHECK: subs
; CHECK: cmp ; CHECK: cmp
; CHECK: it ; CHECK: it
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-ios4.0.0" target triple = "thumbv7-apple-ios4.0.0"
declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind
define hidden fastcc i32 @sqlite3VdbeExec(ptr %p) nounwind { define hidden fastcc i32 @sqlite3VdbeExec(ptr %p, i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind {
entry: entry:
br label %sqlite3VarintLen.exit7424 br label %sqlite3VarintLen.exit7424
sqlite3VarintLen.exit7424: ; preds = %do.body.i7423 sqlite3VarintLen.exit7424: ; preds = %do.body.i7423
br label %do.body.i br label %do.body.i
do.body.i: ; preds = %do.body.i, %sqlite3VarintLen.exit7424 do.body.i: ; preds = %do.body.i, %sqlite3VarintLen.exit7424
br i1 undef, label %do.body.i, label %sqlite3VarintLen.exit br i1 %c0, label %do.body.i, label %sqlite3VarintLen.exit
sqlite3VarintLen.exit: ; preds = %do.body.i sqlite3VarintLen.exit: ; preds = %do.body.i
%sub2322 = add i64 undef, undef %sub2322 = add i64 undef, undef
br i1 undef, label %too_big, label %if.end2327 br i1 %c1, label %too_big, label %if.end2327
if.end2327: ; preds = %sqlite3VarintLen.exit if.end2327: ; preds = %sqlite3VarintLen.exit
br i1 undef, label %if.end2341, label %no_mem br i1 %c2, label %if.end2341, label %no_mem
if.end2341: ; preds = %if.end2327 if.end2341: ; preds = %if.end2327
br label %for.body2355 br label %for.body2355
for.body2355: ; preds = %for.body2355, %if.end2341 for.body2355: ; preds = %for.body2355, %if.end2341
%add2366 = add nsw i32 undef, undef %add2366 = add nsw i32 undef, undef
br i1 undef, label %for.body2377, label %for.body2355 br i1 %c3, label %for.body2377, label %for.body2355
for.body2377: ; preds = %for.body2355 for.body2377: ; preds = %for.body2355
%conv23836154 = zext i32 %add2366 to i64 %conv23836154 = zext i32 %add2366 to i64
%sub2384 = sub i64 %sub2322, %conv23836154 %sub2384 = sub i64 %sub2322, %conv23836154
%conv2385 = trunc i64 %sub2384 to i32 %conv2385 = trunc i64 %sub2384 to i32
%len.0.i = select i1 undef, i32 %conv2385, i32 undef %len.0.i = select i1 undef, i32 %conv2385, i32 undef
%sub.i7384 = sub nsw i32 %len.0.i, 0 %sub.i7384 = sub nsw i32 %len.0.i, 0
%call.i.i7385 = call ptr @__memset_chk(ptr undef, i32 0, i32 %sub.i7384, i32 undef) nounwind %call.i.i7385 = call ptr @__memset_chk(ptr undef, i32 0, i32 %sub.i7384, i32 undef) nounwind
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llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll

; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc < %s -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; RUN: llc < %s -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS
; Radar 10266272 ; Radar 10266272
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios4.0.0" target triple = "thumbv7-apple-ios4.0.0"
; STATS-NOT: machine-sink ; STATS-NOT: machine-sink
define i32 @foo(i32 %h, i32 %arg1) nounwind readonly ssp { define i32 @foo(i32 %h, i32 %arg1, i1 %c0) nounwind readonly ssp {
entry: entry:
br label %for.cond br label %for.cond
for.cond: ; preds = %for.body, %entry for.cond: ; preds = %for.body, %entry
%cmp = icmp slt i32 0, %h %cmp = icmp slt i32 0, %h
br i1 %cmp, label %for.body, label %if.end299 br i1 %cmp, label %for.body, label %if.end299
for.body: ; preds = %for.cond for.body: ; preds = %for.cond
Show All 9 Linesfor.body: ; preds = %for.cond
%2 = load i8, ptr undef, align 1 %2 = load i8, ptr undef, align 1
%conv110 = zext i8 %2 to i32 %conv110 = zext i8 %2 to i32
%sub111 = sub nsw i32 %conv108, %conv110 %sub111 = sub nsw i32 %conv108, %conv110
%cmp112 = icmp slt i32 %sub111, 0 %cmp112 = icmp slt i32 %sub111, 0
%sub115 = sub nsw i32 0, %sub111 %sub115 = sub nsw i32 0, %sub111
%abs = select i1 %cmp112, i32 %sub115, i32 %sub111 %abs = select i1 %cmp112, i32 %sub115, i32 %sub111
%add95 = add i32 %v.5, %v.8 %add95 = add i32 %v.5, %v.8
%add117 = add i32 %add95, %abs %add117 = add i32 %add95, %abs
br i1 undef, label %for.cond, label %if.end299 br i1 %c0, label %for.cond, label %if.end299
if.end299: ; preds = %for.body, %for.cond if.end299: ; preds = %for.body, %for.cond
%s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ] %s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ]
ret i32 %s.10 ret i32 %s.10
} }

llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll

; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs ; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs
; PR11829 ; PR11829
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi" target triple = "armv7-none-linux-gnueabi"
define arm_aapcs_vfpcc void @foo(ptr nocapture %arg) nounwind uwtable align 2 { define arm_aapcs_vfpcc void @foo(ptr nocapture %arg, i1 %c0) nounwind uwtable align 2 {
bb: bb:
br i1 undef, label %bb1, label %bb2 br i1 %c0, label %bb1, label %bb2
bb1: ; preds = %bb bb1: ; preds = %bb
unreachable unreachable
bb2: ; preds = %bb bb2: ; preds = %bb
br label %bb3 br label %bb3
bb3: ; preds = %bb4, %bb2 bb3: ; preds = %bb4, %bb2
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llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll

Show All 32 Linesbb:
%tmp23 = bitcast <4 x float> %tmp22 to <2 x i64> %tmp23 = bitcast <4 x float> %tmp22 to <2 x i64>
%tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp25 = bitcast <1 x i64> %tmp24 to <2 x float> %tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
%tmp26 = extractelement <2 x float> %tmp25, i32 0 %tmp26 = extractelement <2 x float> %tmp25, i32 0
tail call arm_aapcs_vfpcc void @bar(ptr undef, float undef, float %tmp26, float 0.000000e+00) nounwind tail call arm_aapcs_vfpcc void @bar(ptr undef, float undef, float %tmp26, float 0.000000e+00) nounwind
ret void ret void
} }
define arm_aapcs_vfpcc void @foo2() nounwind uwtable { define arm_aapcs_vfpcc void @foo2(i1 %c0) nounwind uwtable {
entry: entry:
br i1 undef, label %for.end, label %cond.end295 br i1 %c0, label %for.end, label %cond.end295
cond.end295: ; preds = %entry cond.end295: ; preds = %entry
%shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
%shuffle.i38.i.i1036 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i38.i.i1036 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
%shuffle.i37.i.i1037 = shufflevector <1 x i64> %shuffle.i39.i.i1035, <1 x i64> %shuffle.i38.i.i1036, <2 x i32> <i32 0, i32 1> %shuffle.i37.i.i1037 = shufflevector <1 x i64> %shuffle.i39.i.i1035, <1 x i64> %shuffle.i38.i.i1036, <2 x i32> <i32 0, i32 1>
%0 = bitcast <2 x i64> %shuffle.i37.i.i1037 to <4 x float> %0 = bitcast <2 x i64> %shuffle.i37.i.i1037 to <4 x float>
%1 = bitcast <4 x float> undef to <2 x i64> %1 = bitcast <4 x float> undef to <2 x i64>
%shuffle.i36.i.i = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i36.i.i = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
Show All 21 Lines

llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll

; RUN: llc < %s -mcpu=cortex-a9 -join-liveintervals=0 -verify-machineinstrs ; RUN: llc < %s -mcpu=cortex-a9 -join-liveintervals=0 -verify-machineinstrs
; PR11765 ; PR11765
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi" target triple = "armv7-none-linux-gnueabi"
; This test case exercises the MachineCopyPropagation pass by disabling the ; This test case exercises the MachineCopyPropagation pass by disabling the
; RegisterCoalescer. ; RegisterCoalescer.
define arm_aapcs_vfpcc void @foo(ptr %arg) nounwind uwtable align 2 { define arm_aapcs_vfpcc void @foo(ptr %arg, i1 %c0, i1 %c1) nounwind uwtable align 2 {
bb: bb:
br i1 undef, label %bb1, label %bb2 br i1 %c0, label %bb1, label %bb2
bb1: ; preds = %bb bb1: ; preds = %bb
unreachable unreachable
bb2: ; preds = %bb bb2: ; preds = %bb
br i1 undef, label %bb92, label %bb3 br i1 %c1, label %bb92, label %bb3
bb3: ; preds = %bb2 bb3: ; preds = %bb2
%tmp = or <4 x i32> undef, undef %tmp = or <4 x i32> undef, undef
%tmp4 = bitcast <4 x i32> %tmp to <4 x float> %tmp4 = bitcast <4 x i32> %tmp to <4 x float>
%tmp5 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp4 %tmp5 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp4
%tmp6 = bitcast <4 x i32> zeroinitializer to <4 x float> %tmp6 = bitcast <4 x i32> zeroinitializer to <4 x float>
%tmp7 = fmul <4 x float> %tmp6, <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00> %tmp7 = fmul <4 x float> %tmp6, <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
%tmp8 = bitcast <4 x float> %tmp7 to <2 x i64> %tmp8 = bitcast <4 x float> %tmp7 to <2 x i64>
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll

; RUN: llc -mcpu=cortex-a8 -verify-machineinstrs < %s ; RUN: llc -mcpu=cortex-a8 -verify-machineinstrs < %s
; PR12165 ; PR12165
target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:32" target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:32"
target triple = "arm-none-linux" target triple = "arm-none-linux"
define hidden void @_strtod_r() nounwind { define hidden void @_strtod_r(i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind {
br i1 undef, label %1, label %2 br i1 %c0, label %1, label %2
; <label>:1 ; preds = %0 ; <label>:1 ; preds = %0
br label %2 br label %2
; <label>:2 ; preds = %1, %0 ; <label>:2 ; preds = %1, %0
br i1 undef, label %3, label %8 br i1 %c1, label %3, label %8
; <label>:3 ; preds = %2 ; <label>:3 ; preds = %2
br i1 undef, label %4, label %7 br i1 %c2, label %4, label %7
; <label>:4 ; preds = %3 ; <label>:4 ; preds = %3
%5 = call i32 @llvm.get.rounding() %5 = call i32 @llvm.get.rounding()
%6 = icmp eq i32 %5, 1 %6 = icmp eq i32 %5, 1
br i1 %6, label %8, label %7 br i1 %6, label %8, label %7
; <label>:7 ; preds = %4, %3 ; <label>:7 ; preds = %4, %3
unreachable unreachable
; <label>:8 ; preds = %4, %2 ; <label>:8 ; preds = %4, %2
br i1 undef, label %9, label %10 br i1 %c3, label %9, label %10
; <label>:9 ; preds = %8 ; <label>:9 ; preds = %8
br label %10 br label %10
; <label>:10 ; preds = %9, %8 ; <label>:10 ; preds = %9, %8
ret void ret void
} }
declare i32 @llvm.get.rounding() nounwind declare i32 @llvm.get.rounding() nounwind

llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll

; RUN: llc < %s ; RUN: llc < %s
; PR11861 ; PR11861
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi" target triple = "armv7-none-linux-gnueabi"
define arm_aapcs_vfpcc void @foo() nounwind align 2 { define arm_aapcs_vfpcc void @foo(i1 %c0) nounwind align 2 {
br i1 undef, label %5, label %1 br i1 %c0, label %5, label %1
; <label>:1 ; preds = %0 ; <label>:1 ; preds = %0
%2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1> %2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%3 = bitcast <2 x i64> %2 to <4 x float> %3 = bitcast <2 x i64> %2 to <4 x float>
store <4 x float> zeroinitializer, ptr undef, align 16 store <4 x float> zeroinitializer, ptr undef, align 16
store <4 x float> zeroinitializer, ptr undef, align 16 store <4 x float> zeroinitializer, ptr undef, align 16
store <4 x float> %3, ptr undef, align 16 store <4 x float> %3, ptr undef, align 16
%4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2 %4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2
store <4 x float> %4, ptr undef, align 16 store <4 x float> %4, ptr undef, align 16
unreachable unreachable
; <label>:5 ; preds = %0 ; <label>:5 ; preds = %0
ret void ret void
} }

llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll

; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -enable-unsafe-fp-math %s -o /dev/null ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -enable-unsafe-fp-math %s -o /dev/null
;target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" ;target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
;target triple = "armv7-none-linux-gnueabi" ;target triple = "armv7-none-linux-gnueabi"
define arm_aapcs_vfpcc void @foo(<4 x float> %arg) nounwind align 2 { define arm_aapcs_vfpcc void @foo(<4 x float> %arg, i1 %c0) nounwind align 2 {
bb4: bb4:
%tmp = extractelement <2 x float> undef, i32 0 %tmp = extractelement <2 x float> undef, i32 0
br i1 undef, label %bb18, label %bb5 br i1 %c0, label %bb18, label %bb5
bb5: ; preds = %bb4 bb5: ; preds = %bb4
%tmp6 = fadd float %tmp, -1.500000e+01 %tmp6 = fadd float %tmp, -1.500000e+01
%tmp7 = fdiv float %tmp6, 2.000000e+01 %tmp7 = fdiv float %tmp6, 2.000000e+01
%tmp8 = fadd float %tmp7, 1.000000e+00 %tmp8 = fadd float %tmp7, 1.000000e+00
%tmp9 = fdiv float 1.000000e+00, %tmp8 %tmp9 = fdiv float 1.000000e+00, %tmp8
%tmp10 = fsub float 1.000000e+00, %tmp9 %tmp10 = fsub float 1.000000e+00, %tmp9
%tmp11 = fmul float %tmp10, 1.000000e+01 %tmp11 = fmul float %tmp10, 1.000000e+01
Show All 12 Lines

llvm/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll

Show All 19 Lines
declare ptr @__cxa_begin_catch(ptr) declare ptr @__cxa_begin_catch(ptr)
declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
declare void @__cxa_end_catch() declare void @__cxa_end_catch()
declare void @_ZSt9terminatev() declare void @_ZSt9terminatev()
define hidden double @t(ptr %self, ptr nocapture %_cmd) optsize ssp personality ptr @__gxx_personality_sj0 { define hidden double @t(ptr %self, ptr nocapture %_cmd, i1 %c0) optsize ssp personality ptr @__gxx_personality_sj0 {
entry: entry:
%call = invoke double undef(ptr undef) optsize %call = invoke double undef(ptr undef) optsize
to label %try.cont unwind label %lpad to label %try.cont unwind label %lpad
lpad: ; preds = %entry lpad: ; preds = %entry
%0 = landingpad { ptr, i32 } %0 = landingpad { ptr, i32 }
catch ptr @_ZTI13ParseErrorMsg catch ptr @_ZTI13ParseErrorMsg
br i1 undef, label %catch, label %eh.resume br i1 %c0, label %catch, label %eh.resume
catch: ; preds = %lpad catch: ; preds = %lpad
invoke void @objc_msgSend(ptr undef, ptr undef, ptr undef) optsize invoke void @objc_msgSend(ptr undef, ptr undef, ptr undef) optsize
to label %invoke.cont2 unwind label %lpad1 to label %invoke.cont2 unwind label %lpad1
invoke.cont2: ; preds = %catch invoke.cont2: ; preds = %catch
br label %try.cont br label %try.cont
Show All 27 Lines

llvm/test/CodeGen/ARM/2012-05-29-TailDupBug.ll

; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -verify-machineinstrs < %s ; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -verify-machineinstrs < %s
; Teach taildup to update livein set to appease verifier. ; Teach taildup to update livein set to appease verifier.
; rdar://11538365 ; rdar://11538365
%struct.__CFString.2 = type opaque %struct.__CFString.2 = type opaque
declare void @CFRelease(ptr) declare void @CFRelease(ptr)
define hidden fastcc i32 @t() ssp { define hidden fastcc i32 @t(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18) ssp {
entry: entry:
%mylocale.i.i = alloca [256 x i8], align 1 %mylocale.i.i = alloca [256 x i8], align 1
br i1 undef, label %return, label %CFStringIsHyphenationAvailableForLocale.exit br i1 %c0, label %return, label %CFStringIsHyphenationAvailableForLocale.exit
CFStringIsHyphenationAvailableForLocale.exit: ; preds = %entry CFStringIsHyphenationAvailableForLocale.exit: ; preds = %entry
br i1 undef, label %return, label %if.end br i1 %c1, label %return, label %if.end
if.end: ; preds = %CFStringIsHyphenationAvailableForLocale.exit if.end: ; preds = %CFStringIsHyphenationAvailableForLocale.exit
br i1 undef, label %if.end8.thread.i, label %if.then.i br i1 %c2, label %if.end8.thread.i, label %if.then.i
if.then.i: ; preds = %if.end if.then.i: ; preds = %if.end
br i1 undef, label %if.end8.thread.i, label %if.end8.i br i1 %c3, label %if.end8.thread.i, label %if.end8.i
if.end8.thread.i: ; preds = %if.then.i, %if.end if.end8.thread.i: ; preds = %if.then.i, %if.end
unreachable unreachable
if.end8.i: ; preds = %if.then.i if.end8.i: ; preds = %if.then.i
br i1 undef, label %if.then11.i, label %__CFHyphenationPullTokenizer.exit br i1 %c4, label %if.then11.i, label %__CFHyphenationPullTokenizer.exit
if.then11.i: ; preds = %if.end8.i if.then11.i: ; preds = %if.end8.i
unreachable unreachable
__CFHyphenationPullTokenizer.exit: ; preds = %if.end8.i __CFHyphenationPullTokenizer.exit: ; preds = %if.end8.i
br i1 undef, label %if.end68, label %if.then3 br i1 %c5, label %if.end68, label %if.then3
if.then3: ; preds = %__CFHyphenationPullTokenizer.exit if.then3: ; preds = %__CFHyphenationPullTokenizer.exit
br i1 undef, label %cond.end, label %cond.false br i1 %c6, label %cond.end, label %cond.false
cond.false: ; preds = %if.then3 cond.false: ; preds = %if.then3
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.false, %if.then3 cond.end: ; preds = %cond.false, %if.then3
br i1 undef, label %while.end, label %while.body br i1 %c7, label %while.end, label %while.body
while.body: ; preds = %cond.end while.body: ; preds = %cond.end
unreachable unreachable
while.end: ; preds = %cond.end while.end: ; preds = %cond.end
br i1 undef, label %if.end5.i, label %if.then.i16 br i1 %c8, label %if.end5.i, label %if.then.i16
if.then.i16: ; preds = %while.end if.then.i16: ; preds = %while.end
br i1 undef, label %if.then4.i, label %if.end5.i br i1 %c9, label %if.then4.i, label %if.end5.i
if.then4.i: ; preds = %if.then.i16 if.then4.i: ; preds = %if.then.i16
br i1 false, label %cleanup.thread, label %if.end.i20 br i1 false, label %cleanup.thread, label %if.end.i20
if.end5.i: ; preds = %if.then.i16, %while.end if.end5.i: ; preds = %if.then.i16, %while.end
unreachable unreachable
if.end.i20: ; preds = %if.then4.i if.end.i20: ; preds = %if.then4.i
br label %for.body.i146.i br label %for.body.i146.i
for.body.i146.i: ; preds = %for.body.i146.i, %if.end.i20 for.body.i146.i: ; preds = %for.body.i146.i, %if.end.i20
br i1 undef, label %if.end20.i, label %for.body.i146.i br i1 %c10, label %if.end20.i, label %for.body.i146.i
if.end20.i: ; preds = %for.body.i146.i if.end20.i: ; preds = %for.body.i146.i
br i1 undef, label %cleanup.thread, label %if.end23.i br i1 %c11, label %cleanup.thread, label %if.end23.i
if.end23.i: ; preds = %if.end20.i if.end23.i: ; preds = %if.end20.i
br label %for.body.i94.i br label %for.body.i94.i
for.body.i94.i: ; preds = %for.body.i94.i, %if.end23.i for.body.i94.i: ; preds = %for.body.i94.i, %if.end23.i
br i1 undef, label %if.then28.i, label %for.body.i94.i br i1 %c12, label %if.then28.i, label %for.body.i94.i
if.then28.i: ; preds = %for.body.i94.i if.then28.i: ; preds = %for.body.i94.i
br i1 undef, label %cond.true.i26, label %land.lhs.true br i1 %c13, label %cond.true.i26, label %land.lhs.true
cond.true.i26: ; preds = %if.then28.i cond.true.i26: ; preds = %if.then28.i
br label %land.lhs.true br label %land.lhs.true
land.lhs.true: ; preds = %cond.true.i26, %if.then28.i land.lhs.true: ; preds = %cond.true.i26, %if.then28.i
br i1 false, label %cleanup.thread, label %if.end35 br i1 false, label %cleanup.thread, label %if.end35
if.end35: ; preds = %land.lhs.true if.end35: ; preds = %land.lhs.true
br i1 undef, label %cleanup.thread, label %if.end45 br i1 %c14, label %cleanup.thread, label %if.end45
if.end45: ; preds = %if.end35 if.end45: ; preds = %if.end35
br i1 undef, label %if.then50, label %if.end.i37 br i1 %c15, label %if.then50, label %if.end.i37
if.end.i37: ; preds = %if.end45 if.end.i37: ; preds = %if.end45
br label %if.then50 br label %if.then50
if.then50: ; preds = %if.end.i37, %if.end45 if.then50: ; preds = %if.end.i37, %if.end45
br i1 undef, label %__CFHyphenationGetHyphensForString.exit, label %if.end.i br i1 %c16, label %__CFHyphenationGetHyphensForString.exit, label %if.end.i
if.end.i: ; preds = %if.then50 if.end.i: ; preds = %if.then50
br i1 undef, label %cleanup.i, label %cond.true.i br i1 %c17, label %cleanup.i, label %cond.true.i
cond.true.i: ; preds = %if.end.i cond.true.i: ; preds = %if.end.i
br i1 undef, label %for.cond16.preheader.i, label %for.cond57.preheader.i br i1 %c18, label %for.cond16.preheader.i, label %for.cond57.preheader.i
for.cond16.preheader.i: ; preds = %cond.true.i for.cond16.preheader.i: ; preds = %cond.true.i
%cmp1791.i = icmp sgt i32 undef, 1 %cmp1791.i = icmp sgt i32 undef, 1
br i1 %cmp1791.i, label %for.body18.i, label %for.cond57.preheader.i br i1 %cmp1791.i, label %for.body18.i, label %for.cond57.preheader.i
for.cond57.preheader.i: ; preds = %for.cond16.preheader.i, %cond.true.i for.cond57.preheader.i: ; preds = %for.cond16.preheader.i, %cond.true.i
%sub69.i = add i32 undef, -2 %sub69.i = add i32 undef, -2
br label %cleanup.i br label %cleanup.i
Show All 31 Lines

llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll

; RUN: llc < %s ; RUN: llc < %s
; PR13377 ; PR13377
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi" target triple = "armv7-none-linux-gnueabi"
%0 = type { <4 x float> } %0 = type { <4 x float> }
define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable { define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, i1 %c10, i1 %c11, i1 %c12, i1 %c13, i1 %c14, i1 %c15, i1 %c16, i1 %c17, i1 %c18, i1 %c19, i1 %c20, i1 %c21, i1 %c22, i1 %c23, i1 %c24) nounwind uwtable {
br i1 undef, label %4, label %5 br i1 %c0, label %4, label %5
; <label>:4 ; preds = %3 ; <label>:4 ; preds = %3
unreachable unreachable
; <label>:5 ; preds = %3 ; <label>:5 ; preds = %3
br i1 undef, label %7, label %6 br i1 %c1, label %7, label %6
; <label>:6 ; preds = %5 ; <label>:6 ; preds = %5
unreachable unreachable
; <label>:7 ; preds = %5 ; <label>:7 ; preds = %5
br i1 undef, label %8, label %10 br i1 %c2, label %8, label %10
; <label>:8 ; preds = %7 ; <label>:8 ; preds = %7
br i1 undef, label %9, label %10 br i1 %c3, label %9, label %10
; <label>:9 ; preds = %8 ; <label>:9 ; preds = %8
br i1 undef, label %11, label %10 br i1 %c4, label %11, label %10
; <label>:10 ; preds = %9, %8, %7 ; <label>:10 ; preds = %9, %8, %7
unreachable unreachable
; <label>:11 ; preds = %9 ; <label>:11 ; preds = %9
br i1 undef, label %13, label %12 br i1 %c5, label %13, label %12
; <label>:12 ; preds = %11 ; <label>:12 ; preds = %11
unreachable unreachable
; <label>:13 ; preds = %11 ; <label>:13 ; preds = %11
br i1 undef, label %15, label %14 br i1 %c6, label %15, label %14
; <label>:14 ; preds = %13 ; <label>:14 ; preds = %13
unreachable unreachable
; <label>:15 ; preds = %13 ; <label>:15 ; preds = %13
br i1 undef, label %18, label %16 br i1 %c7, label %18, label %16
; <label>:16 ; preds = %15 ; <label>:16 ; preds = %15
br i1 undef, label %17, label %18 br i1 %c8, label %17, label %18
; <label>:17 ; preds = %16 ; <label>:17 ; preds = %16
unreachable unreachable
; <label>:18 ; preds = %16, %15 ; <label>:18 ; preds = %16, %15
br i1 undef, label %68, label %19 br i1 %c9, label %68, label %19
; <label>:19 ; preds = %18 ; <label>:19 ; preds = %18
br label %20 br label %20
; <label>:20 ; preds = %20, %19 ; <label>:20 ; preds = %20, %19
br i1 undef, label %21, label %20 br i1 %c10, label %21, label %20
; <label>:21 ; preds = %20 ; <label>:21 ; preds = %20
br i1 undef, label %22, label %68 br i1 %c11, label %22, label %68
; <label>:22 ; preds = %21 ; <label>:22 ; preds = %21
br i1 undef, label %23, label %24 br i1 %c12, label %23, label %24
; <label>:23 ; preds = %22 ; <label>:23 ; preds = %22
unreachable unreachable
; <label>:24 ; preds = %22 ; <label>:24 ; preds = %22
br i1 undef, label %26, label %25 br i1 %c13, label %26, label %25
; <label>:25 ; preds = %24 ; <label>:25 ; preds = %24
unreachable unreachable
; <label>:26 ; preds = %24 ; <label>:26 ; preds = %24
br i1 undef, label %28, label %27 br i1 %c14, label %28, label %27
; <label>:27 ; preds = %26 ; <label>:27 ; preds = %26
unreachable unreachable
; <label>:28 ; preds = %26 ; <label>:28 ; preds = %26
br i1 undef, label %29, label %30, !prof !0 br i1 %c15, label %29, label %30, !prof !0
; <label>:29 ; preds = %28 ; <label>:29 ; preds = %28
br label %30 br label %30
; <label>:30 ; preds = %29, %28 ; <label>:30 ; preds = %29, %28
br i1 undef, label %31, label %32, !prof !0 br i1 %c16, label %31, label %32, !prof !0
; <label>:31 ; preds = %30 ; <label>:31 ; preds = %30
br label %32 br label %32
; <label>:32 ; preds = %31, %30 ; <label>:32 ; preds = %31, %30
br i1 undef, label %34, label %33 br i1 %c17, label %34, label %33
; <label>:33 ; preds = %32 ; <label>:33 ; preds = %32
unreachable unreachable
; <label>:34 ; preds = %32 ; <label>:34 ; preds = %32
br i1 undef, label %35, label %36, !prof !0 br i1 %c18, label %35, label %36, !prof !0
; <label>:35 ; preds = %34 ; <label>:35 ; preds = %34
br label %36 br label %36
; <label>:36 ; preds = %35, %34 ; <label>:36 ; preds = %35, %34
br i1 undef, label %37, label %38, !prof !0 br i1 %c19, label %37, label %38, !prof !0
; <label>:37 ; preds = %36 ; <label>:37 ; preds = %36
br label %38 br label %38
; <label>:38 ; preds = %37, %36 ; <label>:38 ; preds = %37, %36
br i1 undef, label %39, label %67 br i1 %c20, label %39, label %67
; <label>:39 ; preds = %38 ; <label>:39 ; preds = %38
br i1 undef, label %40, label %41 br i1 %c21, label %40, label %41
; <label>:40 ; preds = %39 ; <label>:40 ; preds = %39
br i1 undef, label %64, label %41 br i1 %c22, label %64, label %41
; <label>:41 ; preds = %40, %39 ; <label>:41 ; preds = %40, %39
br i1 undef, label %64, label %42 br i1 %c23, label %64, label %42
; <label>:42 ; preds = %41 ; <label>:42 ; preds = %41
%43 = fadd <4 x float> undef, undef %43 = fadd <4 x float> undef, undef
%44 = fadd <4 x float> undef, undef %44 = fadd <4 x float> undef, undef
%45 = fmul <4 x float> undef, undef %45 = fmul <4 x float> undef, undef
%46 = fmul <4 x float> %45, %43 %46 = fmul <4 x float> %45, %43
%47 = fmul <4 x float> undef, %44 %47 = fmul <4 x float> undef, %44
%48 = load <4 x float>, ptr undef, align 8 %48 = load <4 x float>, ptr undef, align 8
Show All 14 Lines; <label>:42 ; preds = %41
%63 = fadd <4 x float> %47, %62 %63 = fadd <4 x float> %47, %62
store <4 x float> %46, ptr undef, align 8 store <4 x float> %46, ptr undef, align 8
call arm_aapcs_vfpcc void @bar(ptr undef, float 0.000000e+00) nounwind call arm_aapcs_vfpcc void @bar(ptr undef, float 0.000000e+00) nounwind
call arm_aapcs_vfpcc void @bar(ptr undef, float 0.000000e+00) nounwind call arm_aapcs_vfpcc void @bar(ptr undef, float 0.000000e+00) nounwind
store <4 x float> %63, ptr undef, align 8 store <4 x float> %63, ptr undef, align 8
unreachable unreachable
; <label>:64 ; preds = %41, %40 ; <label>:64 ; preds = %41, %40
br i1 undef, label %65, label %66 br i1 %c24, label %65, label %66
; <label>:65 ; preds = %64 ; <label>:65 ; preds = %64
unreachable unreachable
; <label>:66 ; preds = %64 ; <label>:66 ; preds = %64
unreachable unreachable
; <label>:67 ; preds = %38 ; <label>:67 ; preds = %38
Show All 9 Lines

llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll

; RUN: llc < %s -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s ; RUN: llc < %s -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7--linux-gnueabi" target triple = "armv7--linux-gnueabi"
; CHECK-LABEL: function ; CHECK-LABEL: function
define void @function() { define void @function(i1 %c0) {
; CHECK: cmp r0, #0 ; CHECK: cmp r0, #0
; CHECK: bxne lr ; CHECK: bxne lr
entry: entry:
br i1 undef, label %vector.body, label %for.end br i1 %c0, label %vector.body, label %for.end
; CHECK: vld1.32 {d16, d17}, [r0] ; CHECK: vld1.32 {d16, d17}, [r0]
; CHECK: vbic.i32 q8, #0xff ; CHECK: vbic.i32 q8, #0xff
; CHECK: vorr q8, q8, q9 ; CHECK: vorr q8, q8, q9
; CHECK: vst1.32 {d16, d17}, [r0] ; CHECK: vst1.32 {d16, d17}, [r0]
vector.body: vector.body:
%wide.load = load <4 x i32>, ptr undef, align 4 %wide.load = load <4 x i32>, ptr undef, align 4
%0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936> %0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>
Show All 11 Lines

llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll

; RUN: llc < %s ; RUN: llc < %s
; This test has around 4000 bytes of local variables and it also stresses register allocation ; This test has around 4000 bytes of local variables and it also stresses register allocation
; to force a register scavenging. It tests if the stack is treated as "BigStack" and thus ; to force a register scavenging. It tests if the stack is treated as "BigStack" and thus
; spill slots are reserved. If not, reg scavenger will assert. ; spill slots are reserved. If not, reg scavenger will assert.
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
target triple = "thumbv7--linux-android" target triple = "thumbv7--linux-android"
%struct.r = type { ptr, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x ptr], [10 x ptr], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], ptr, float } %struct.r = type { ptr, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x ptr], [10 x ptr], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], ptr, float }
define void @foo(ptr %this, ptr %srcR, ptr %srcC, ptr %tempPntsX, ptr %tY, ptr %ms, ptr %sX, ptr %sY, ptr dereferenceable(4) %num, ptr %tm, i32 %SR, i32 %lev, ptr %tdata, i32 %siW, i32 %pyw, i32 %pyh, ptr %sdata) #0 align 2 { define void @foo(ptr %this, ptr %srcR, ptr %srcC, ptr %tempPntsX, ptr %tY, ptr %ms, ptr %sX, ptr %sY, ptr dereferenceable(4) %num, ptr %tm, i32 %SR, i32 %lev, ptr %tdata, i32 %siW, i32 %pyw, i32 %pyh, ptr %sdata, i1 %c0) #0 align 2 {
entry: entry:
%sFV = alloca [49 x float], align 4 %sFV = alloca [49 x float], align 4
%tFV = alloca [49 x float], align 4 %tFV = alloca [49 x float], align 4
%TIM = alloca [9 x float], align 4 %TIM = alloca [9 x float], align 4
%sort_tmp = alloca [432 x float], align 4 %sort_tmp = alloca [432 x float], align 4
%msDiffs = alloca [432 x float], align 4 %msDiffs = alloca [432 x float], align 4
%TM.sroa.0.0.copyload = load float, ptr %tm, align 4 %TM.sroa.0.0.copyload = load float, ptr %tm, align 4
%TM.sroa.8.0.copyload = load float, ptr null, align 4 %TM.sroa.8.0.copyload = load float, ptr null, align 4
%TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, ptr %tm, i32 6 %TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, ptr %tm, i32 6
%TM.sroa.9.0.copyload = load float, ptr %TM.sroa.9.0..sroa_idx813, align 4 %TM.sroa.9.0.copyload = load float, ptr %TM.sroa.9.0..sroa_idx813, align 4
%TM.sroa.11.0.copyload = load float, ptr undef, align 4 %TM.sroa.11.0.copyload = load float, ptr undef, align 4
br i1 undef, label %for.body.lr.ph, label %if.then343 br i1 %c0, label %for.body.lr.ph, label %if.then343
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
%arrayidx8 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 0 %arrayidx8 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 0
%arrayidx12 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 6 %arrayidx12 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 6
%arrayidx15 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 4 %arrayidx15 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 4
%arrayidx20 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 7 %arrayidx20 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 7
%arrayidx24 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 0 %arrayidx24 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 0
%arrayidx28 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 6 %arrayidx28 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 6
▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll

; RUN: llc -o - %s -mtriple thumbv4-unknown-linux-android | FileCheck --check-prefix=V4 %s ; RUN: llc -o - %s -mtriple thumbv4-unknown-linux-android | FileCheck --check-prefix=V4 %s
; RUN: llc -o - %s -mtriple thumbv5-unknown-linux-android | FileCheck --check-prefix=V5 %s ; RUN: llc -o - %s -mtriple thumbv5-unknown-linux-android | FileCheck --check-prefix=V5 %s
; V4: udf #254 ; V4: udf #254
; V5: bkpt #0 ; V5: bkpt #0
define i1 @a(i32 %b) !dbg !3 { define i1 @a(i32 %b, i1 %c0) !dbg !3 {
br i1 undef, label %c, label %d, !dbg !4 br i1 %c0, label %c, label %d, !dbg !4
d: ; preds = %0 d: ; preds = %0
call void @llvm.debugtrap() call void @llvm.debugtrap()
br label %ah, !dbg !4 br label %ah, !dbg !4
c: ; preds = %0 c: ; preds = %0
%aj = icmp ne i20 undef, 5 %aj = icmp ne i20 undef, 5
br label %ah, !dbg !4 br label %ah, !dbg !4
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/arm-frame-lowering-no-terminator.ll

; RUN: llc < %s ; RUN: llc < %s
; Ensure that ARMFrameLowering can emit an epilogue when there's no terminator. ; Ensure that ARMFrameLowering can emit an epilogue when there's no terminator.
; This is the crasher from PR29072. ; This is the crasher from PR29072.
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7-unknown-linux-gnueabihf" target triple = "armv7-unknown-linux-gnueabihf"
%t1 = type { [4 x float] } %t1 = type { [4 x float] }
%t3 = type { ptr } %t3 = type { ptr }
%t2 = type { %t3, i8, %t1, %t1, float } %t2 = type { %t3, i8, %t1, %t1, float }
define internal void @foo(ptr nocapture %this, ptr nocapture readonly %triangle, i32 %partId, i32 %triangleIndex) { define internal void @foo(ptr nocapture %this, ptr nocapture readonly %triangle, i32 %partId, i32 %triangleIndex, i1 %c0) {
entry: entry:
br i1 undef, label %if.else, label %if.end br i1 %c0, label %if.else, label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
%0 = load float, ptr %triangle, align 4 %0 = load float, ptr %triangle, align 4
%arrayidx5.i = getelementptr inbounds %t1, ptr %triangle, i32 0, i32 0, i32 1 %arrayidx5.i = getelementptr inbounds %t1, ptr %triangle, i32 0, i32 0, i32 1
%1 = load float, ptr %arrayidx5.i, align 4 %1 = load float, ptr %arrayidx5.i, align 4
%2 = load float, ptr null, align 4 %2 = load float, ptr null, align 4
%arrayidx11.i = getelementptr inbounds %t1, ptr %triangle, i32 0, i32 0, i32 2 %arrayidx11.i = getelementptr inbounds %t1, ptr %triangle, i32 0, i32 0, i32 2
%3 = load float, ptr %arrayidx11.i, align 4 %3 = load float, ptr %arrayidx11.i, align 4
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll

Show First 20 Lines • Show All 1,348 Lines • ▼ Show 20 Lines
; and Restore blocks are control flow equivalent, the loop searches for the ; and Restore blocks are control flow equivalent, the loop searches for the
; immediate (post) dominator for the (restore) save blocks. When either the Save ; immediate (post) dominator for the (restore) save blocks. When either the Save
; or Restore block is located in an infinite loop the only immediate (post) ; or Restore block is located in an infinite loop the only immediate (post)
; dominator is itself. In this case, we cannot perform shrink wrapping, but we ; dominator is itself. In this case, we cannot perform shrink wrapping, but we
; should return gracefully and continue compilation. ; should return gracefully and continue compilation.
; The only condition for this test is the compilation finishes correctly. ; The only condition for this test is the compilation finishes correctly.
; infiniteloop ; infiniteloop
; pop ; pop
define void @infiniteloop() "frame-pointer"="all" { define void @infiniteloop(i1 %c0) "frame-pointer"="all" {
; ARM-LABEL: infiniteloop: ; ARM-LABEL: infiniteloop:
; ARM: @ %bb.0: @ %entry ; ARM: @ %bb.0: @ %entry
; ARM-NEXT: push {r4, r5, r7, lr} ; ARM-NEXT: push {r4, r5, r7, lr}
; ARM-NEXT: add r7, sp, #8 ; ARM-NEXT: add r7, sp, #8
; ARM-NEXT: mov r0, #0 ; ARM-NEXT: mov r0, #0
; ARM-NEXT: cmp r0, #0 ; ARM-NEXT: cmp r0, #0
; ARM-NEXT: bne LBB9_3 ; ARM-NEXT: bne LBB9_3
; ARM-NEXT: @ %bb.1: @ %if.then ; ARM-NEXT: @ %bb.1: @ %if.then
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; THUMB-DISABLE-NEXT: add r1, r2 ; THUMB-DISABLE-NEXT: add r1, r2
; THUMB-DISABLE-NEXT: str r1, [r0] ; THUMB-DISABLE-NEXT: str r1, [r0]
; THUMB-DISABLE-NEXT: b LBB9_2 ; THUMB-DISABLE-NEXT: b LBB9_2
; THUMB-DISABLE-NEXT: LBB9_3: @ %if.end ; THUMB-DISABLE-NEXT: LBB9_3: @ %if.end
; THUMB-DISABLE-NEXT: sub.w r4, r7, #8 ; THUMB-DISABLE-NEXT: sub.w r4, r7, #8
; THUMB-DISABLE-NEXT: mov sp, r4 ; THUMB-DISABLE-NEXT: mov sp, r4
; THUMB-DISABLE-NEXT: pop {r4, r5, r7, pc} ; THUMB-DISABLE-NEXT: pop {r4, r5, r7, pc}
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: if.then:
%ptr = alloca i32, i32 4 %ptr = alloca i32, i32 4
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ] %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
%call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"()
%add = add nsw i32 %call, %sum.03 %add = add nsw i32 %call, %sum.03
store i32 %add, ptr %ptr store i32 %add, ptr %ptr
br label %for.body br label %for.body
if.end: if.end:
ret void ret void
} }
; Another infinite loop test this time with a body bigger than just one block. ; Another infinite loop test this time with a body bigger than just one block.
; infiniteloop2 ; infiniteloop2
; pop ; pop
define void @infiniteloop2() "frame-pointer"="all" { define void @infiniteloop2(i1 %c0, i1 %c1) "frame-pointer"="all" {
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 %c0, label %if.then, label %if.end
if.then: if.then:
%ptr = alloca i32, i32 4 %ptr = alloca i32, i32 4
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2] %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2]
%call = tail call i32 asm "mov $0, #0", "=r,~{r4}"() %call = tail call i32 asm "mov $0, #0", "=r,~{r4}"()
%add = add nsw i32 %call, %sum.03 %add = add nsw i32 %call, %sum.03
store i32 %add, ptr %ptr store i32 %add, ptr %ptr
br i1 undef, label %body1, label %body2 br i1 %c1, label %body1, label %body2
body1: body1:
tail call void asm sideeffect "nop", "~{r4}"() tail call void asm sideeffect "nop", "~{r4}"()
br label %for.body br label %for.body
body2: body2:
tail call void asm sideeffect "nop", "~{r4}"() tail call void asm sideeffect "nop", "~{r4}"()
br label %for.body br label %for.body
if.end: if.end:
ret void ret void
} }
; Another infinite loop test this time with two nested infinite loop. ; Another infinite loop test this time with two nested infinite loop.
; infiniteloop3 ; infiniteloop3
; bx lr ; bx lr
define void @infiniteloop3() "frame-pointer"="all" { define void @infiniteloop3(i1 %c0, i1 %c1) "frame-pointer"="all" {
; ARM-LABEL: infiniteloop3: ; ARM-LABEL: infiniteloop3:
; ARM: @ %bb.0: @ %entry ; ARM: @ %bb.0: @ %entry
; ARM-NEXT: mov r0, #0 ; ARM-NEXT: mov r0, #0
; ARM-NEXT: cmp r0, #0 ; ARM-NEXT: cmp r0, #0
; ARM-NEXT: bne LBB11_5 ; ARM-NEXT: bne LBB11_5
; ARM-NEXT: @ %bb.1: @ %loop2a.preheader ; ARM-NEXT: @ %bb.1: @ %loop2a.preheader
; ARM-NEXT: mov r1, #0 ; ARM-NEXT: mov r1, #0
; ARM-NEXT: mov r2, r0 ; ARM-NEXT: mov r2, r0
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; THUMB-DISABLE-NEXT: @ %bb.4: @ in Loop: Header=BB11_3 Depth=1 ; THUMB-DISABLE-NEXT: @ %bb.4: @ in Loop: Header=BB11_3 Depth=1
; THUMB-DISABLE-NEXT: mov r0, r1 ; THUMB-DISABLE-NEXT: mov r0, r1
; THUMB-DISABLE-NEXT: mov r1, r3 ; THUMB-DISABLE-NEXT: mov r1, r3
; THUMB-DISABLE-NEXT: mov r2, r0 ; THUMB-DISABLE-NEXT: mov r2, r0
; THUMB-DISABLE-NEXT: b LBB11_3 ; THUMB-DISABLE-NEXT: b LBB11_3
; THUMB-DISABLE-NEXT: LBB11_5: @ %end ; THUMB-DISABLE-NEXT: LBB11_5: @ %end
; THUMB-DISABLE-NEXT: bx lr ; THUMB-DISABLE-NEXT: bx lr
entry: entry:
br i1 undef, label %loop2a, label %body br i1 %c0, label %loop2a, label %body
body: ; preds = %entry body: ; preds = %entry
br i1 undef, label %loop2a, label %end br i1 %c1, label %loop2a, label %end
loop1: ; preds = %loop2a, %loop2b loop1: ; preds = %loop2a, %loop2b
%var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ] %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]
%next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ] %next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ]
%0 = icmp eq ptr %var, null %0 = icmp eq ptr %var, null
%next.load = load ptr, ptr undef %next.load = load ptr, ptr undef
br i1 %0, label %loop2a, label %loop2b br i1 %0, label %loop2a, label %loop2b
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llvm/test/CodeGen/ARM/call-tc.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines; CHECKELF: b __aeabi_idiv
%0 = sdiv i32 %a, %b %0 = sdiv i32 %a, %b
ret i32 %0 ret i32 %0
} }
; Make sure the tail call instruction isn't deleted ; Make sure the tail call instruction isn't deleted
; rdar://8309338 ; rdar://8309338
declare void @foo() nounwind declare void @foo() nounwind
define void @t7() nounwind "frame-pointer"="all" { define void @t7(i1 %c0) nounwind "frame-pointer"="all" {
entry: entry:
; CHECKT2D-LABEL: t7: ; CHECKT2D-LABEL: t7:
; CHECKT2D: it ne ; CHECKT2D: it ne
; CHECKT2D-NEXT: bne.w _foo ; CHECKT2D-NEXT: bne.w _foo
; CHECKT2D-NEXT: LBB{{.*}}: ; CHECKT2D-NEXT: LBB{{.*}}:
; CHECKT2D-NEXT: push ; CHECKT2D-NEXT: push
; CHECKT2D-NEXT: mov r7, sp ; CHECKT2D-NEXT: mov r7, sp
; CHECKT2D-NEXT: bl _foo ; CHECKT2D-NEXT: bl _foo
br i1 undef, label %bb, label %bb1.lr.ph br i1 %c0, label %bb, label %bb1.lr.ph
bb1.lr.ph: bb1.lr.ph:
tail call void @foo() nounwind tail call void @foo() nounwind
unreachable unreachable
bb: bb:
tail call void @foo() nounwind tail call void @foo() nounwind
ret void ret void
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llvm/test/CodeGen/ARM/coalesce-subregs.ll

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Linesif.end: ; preds = %if.else, %if.then
tail call void @llvm.arm.neon.vst1.p0.v2f32(ptr %add.ptr, <2 x float> %x.0, i32 4) tail call void @llvm.arm.neon.vst1.p0.v2f32(ptr %add.ptr, <2 x float> %x.0, i32 4)
ret void ret void
} }
declare void @llvm.arm.neon.vst1.p0.v2f32(ptr, <2 x float>, i32) nounwind declare void @llvm.arm.neon.vst1.p0.v2f32(ptr, <2 x float>, i32) nounwind
declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr, i32) nounwind readonly declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr, i32) nounwind readonly
; CHECK: f4 ; CHECK: f4
; This function inserts a lane into a fully defined vector.
; The destination lane isn't read, so the subregs can coalesce. ; The destination lane isn't read, so the subregs can coalesce.
; CHECK-NOT: vmov ; CHECK-NOT: vmov
; CHECK-NOT: vorr ; CHECK-NOT: vorr
define void @f4(ptr %p, ptr %q) nounwind ssp { define void @f4(ptr %p, ptr %q) nounwind ssp {
entry: entry:
%vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr %p, i32 4) %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr %p, i32 4)
%tobool = icmp eq ptr %q, null %tobool = icmp eq ptr %q, null
br i1 %tobool, label %if.end, label %if.then br i1 %tobool, label %if.end, label %if.then
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Linesif.end: ; preds = %entry, %if.then
ret void ret void
} }
declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly
declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind
; CHECK: pr13999 ; CHECK: pr13999
define void @pr13999() nounwind readonly { define void @pr13999(i1 %c0) nounwind readonly {
entry: entry:
br i1 true, label %outer_loop, label %loop.end br i1 true, label %outer_loop, label %loop.end
outer_loop: outer_loop:
%d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ] %d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
%0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0 %0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0
br i1 undef, label %after_inner_loop, label %inner_loop br i1 %c0, label %after_inner_loop, label %inner_loop
inner_loop: inner_loop:
br i1 true, label %after_inner_loop, label %inner_loop br i1 true, label %after_inner_loop, label %inner_loop
after_inner_loop: after_inner_loop:
%1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>, %1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>,
%inner_loop ] %inner_loop ]
%2 = extractelement <2 x double> %1, i32 1 %2 = extractelement <2 x double> %1, i32 1
%add = fadd double 1.0, %2 %add = fadd double 1.0, %2
br i1 false, label %loop.end, label %outer_loop br i1 false, label %loop.end, label %outer_loop
loop.end: loop.end:
%d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ] %d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
ret void ret void
} }
; CHECK: pr14078 ; CHECK: pr14078
define arm_aapcs_vfpcc i32 @pr14078(ptr nocapture %arg, ptr nocapture %arg1, i32 %arg2) nounwind uwtable readonly { define arm_aapcs_vfpcc i32 @pr14078(ptr nocapture %arg, ptr nocapture %arg1, i32 %arg2, i1 %c0, i1 %c1) nounwind uwtable readonly {
bb: bb:
br i1 undef, label %bb31, label %bb3 br i1 %c0, label %bb31, label %bb3
bb3: ; preds = %bb12, %bb bb3: ; preds = %bb12, %bb
%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer %tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp4 = bitcast <1 x i64> %tmp to <2 x float> %tmp4 = bitcast <1 x i64> %tmp to <2 x float>
%tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <4 x i32> zeroinitializer %tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <4 x i32> zeroinitializer
%tmp6 = bitcast <4 x float> %tmp5 to <2 x i64> %tmp6 = bitcast <4 x float> %tmp5 to <2 x i64>
%tmp7 = shufflevector <2 x i64> %tmp6, <2 x i64> undef, <1 x i32> zeroinitializer %tmp7 = shufflevector <2 x i64> %tmp6, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp8 = bitcast <1 x i64> %tmp7 to <2 x float> %tmp8 = bitcast <1 x i64> %tmp7 to <2 x float>
%tmp9 = tail call <2 x float> @baz(<2 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00>, <2 x float> %tmp8, <2 x float> zeroinitializer) nounwind %tmp9 = tail call <2 x float> @baz(<2 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00>, <2 x float> %tmp8, <2 x float> zeroinitializer) nounwind
br i1 undef, label %bb10, label %bb12 br i1 %c1, label %bb10, label %bb12
bb10: ; preds = %bb3 bb10: ; preds = %bb3
%tmp11 = load <4 x float>, ptr undef, align 8 %tmp11 = load <4 x float>, ptr undef, align 8
br label %bb12 br label %bb12
bb12: ; preds = %bb10, %bb3 bb12: ; preds = %bb10, %bb3
%tmp13 = shufflevector <2 x float> %tmp9, <2 x float> zeroinitializer, <2 x i32> <i32 0, i32 2> %tmp13 = shufflevector <2 x float> %tmp9, <2 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>
%tmp14 = bitcast <2 x float> %tmp13 to <1 x i64> %tmp14 = bitcast <2 x float> %tmp13 to <1 x i64>
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; <rdar://problem/12758887> ; <rdar://problem/12758887>
; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than ; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than
; once under rare circumstances. When widening a register from QPR to DTriple ; once under rare circumstances. When widening a register from QPR to DTriple
; with the original virtual register in dsub_1_dsub_2, the double rewrite would ; with the original virtual register in dsub_1_dsub_2, the double rewrite would
; produce an invalid sub-register. ; produce an invalid sub-register.
; ;
; This is because dsub_1_dsub_2 is not an idempotent sub-register index. ; This is because dsub_1_dsub_2 is not an idempotent sub-register index.
; It will translate %vr:dsub_0 -> %vr:dsub_1. ; It will translate %vr:dsub_0 -> %vr:dsub_1.
define hidden fastcc void @radar12758887() nounwind optsize ssp { define hidden fastcc void @radar12758887(i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind optsize ssp {
entry: entry:
br i1 undef, label %for.body, label %for.end70 br i1 %c0, label %for.body, label %for.end70
for.body: ; preds = %for.end, %entry for.body: ; preds = %for.end, %entry
br i1 undef, label %for.body29, label %for.end br i1 %c1, label %for.body29, label %for.end
for.body29: ; preds = %for.body29, %for.body for.body29: ; preds = %for.body29, %for.body
%0 = load <2 x double>, ptr null, align 1 %0 = load <2 x double>, ptr null, align 1
%splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
%mul41 = fmul <2 x double> undef, %splat40 %mul41 = fmul <2 x double> undef, %splat40
%add42 = fadd <2 x double> undef, %mul41 %add42 = fadd <2 x double> undef, %mul41
%splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1> %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1>
%mul45 = fmul <2 x double> undef, %splat44 %mul45 = fmul <2 x double> undef, %splat44
%add46 = fadd <2 x double> undef, %mul45 %add46 = fadd <2 x double> undef, %mul45
br i1 undef, label %for.end, label %for.body29 br i1 %c2, label %for.end, label %for.body29
for.end: ; preds = %for.body29, %for.body for.end: ; preds = %for.body29, %for.body
%accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ] %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]
%accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ] %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]
%1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0> %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0>
%add58 = fadd <2 x double> undef, %1 %add58 = fadd <2 x double> undef, %1
%mul61 = fmul <2 x double> %add58, undef %mul61 = fmul <2 x double> %add58, undef
%add63 = fadd <2 x double> undef, %mul61 %add63 = fadd <2 x double> undef, %mul61
%add64 = fadd <2 x double> undef, %add63 %add64 = fadd <2 x double> undef, %add63
%add67 = fadd <2 x double> undef, %add64 %add67 = fadd <2 x double> undef, %add64
store <2 x double> %add67, ptr undef, align 1 store <2 x double> %add67, ptr undef, align 1
br i1 undef, label %for.end70, label %for.body br i1 %c3, label %for.end70, label %for.body
for.end70: ; preds = %for.end, %entry for.end70: ; preds = %for.end, %entry
ret void ret void
} }

llvm/test/CodeGen/ARM/crash-greedy-v6.ll

; RUN: llc -frame-pointer=all -relocation-model=pic < %s ; RUN: llc -frame-pointer=all -relocation-model=pic < %s
; RUN: llc -frame-pointer=all -relocation-model=pic -O0 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED ; RUN: llc -frame-pointer=all -relocation-model=pic -O0 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
target triple = "armv6-apple-ios" target triple = "armv6-apple-ios"
; Reduced from 177.mesa. This test causes a live range split before an LDR_POST instruction. ; Reduced from 177.mesa. This test causes a live range split before an LDR_POST instruction.
; That requires leaveIntvBefore to be very accurate about the redefined value number. define internal void @sample_nearest_3d(ptr nocapture %tObj, i32 %n, ptr nocapture %s, ptr nocapture %t, ptr nocapture %u, ptr nocapture %lambda, ptr nocapture %red, ptr nocapture %green, ptr nocapture %blue, ptr nocapture %alpha, i1 %c0) nounwind ssp {
define internal void @sample_nearest_3d(ptr nocapture %tObj, i32 %n, ptr nocapture %s, ptr nocapture %t, ptr nocapture %u, ptr nocapture %lambda, ptr nocapture %red, ptr nocapture %green, ptr nocapture %blue, ptr nocapture %alpha) nounwind ssp {
entry: entry:
br i1 undef, label %for.end, label %for.body.lr.ph br i1 %c0, label %for.end, label %for.body.lr.ph
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
br label %for.body br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph for.body: ; preds = %for.body, %for.body.lr.ph
; SOURCE-SCHED: ldr ; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr ; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr ; SOURCE-SCHED: ldr
Show All 35 Lines

llvm/test/CodeGen/ARM/crash-greedy.ll

; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -frame-pointer=all -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -frame-pointer=all -verify-machineinstrs | FileCheck %s
; ;
; ARM tests that crash or fail with the greedy register allocator. ; ARM tests that crash or fail with the greedy register allocator.
target triple = "thumbv7-apple-darwin" target triple = "thumbv7-apple-darwin"
declare double @exp(double) declare double @exp(double)
; CHECK: remat_subreg ; CHECK: remat_subreg
define void @remat_subreg(ptr nocapture %x, ptr %y, i32 %n, i32 %z, float %c, float %lambda, ptr nocapture %ret_f, ptr nocapture %ret_df, i1 %cond) nounwind { define void @remat_subreg(ptr nocapture %x, ptr %y, i32 %n, i32 %z, float %c, float %lambda, ptr nocapture %ret_f, ptr nocapture %ret_df, i1 %cond, i1 %c0) nounwind {
entry: entry:
%conv16 = fpext float %lambda to double %conv16 = fpext float %lambda to double
%mul17 = fmul double %conv16, -1.000000e+00 %mul17 = fmul double %conv16, -1.000000e+00
br i1 %cond, label %cond.end.us, label %cond.end br i1 %cond, label %cond.end.us, label %cond.end
cond.end.us: ; preds = %entry cond.end.us: ; preds = %entry
unreachable unreachable
cond.end: ; preds = %cond.end, %entry cond.end: ; preds = %cond.end, %entry
%mul = fmul double undef, 0.000000e+00 %mul = fmul double undef, 0.000000e+00
%add = fadd double undef, %mul %add = fadd double undef, %mul
%add46 = fadd double undef, undef %add46 = fadd double undef, undef
%add75 = fadd double 0.000000e+00, undef %add75 = fadd double 0.000000e+00, undef
br i1 undef, label %for.end, label %cond.end br i1 %c0, label %for.end, label %cond.end
for.end: ; preds = %cond.end for.end: ; preds = %cond.end
%conv78 = sitofp i32 %z to double %conv78 = sitofp i32 %z to double
%conv83 = fpext float %c to double %conv83 = fpext float %c to double
%mul84 = fmul double %mul17, %conv83 %mul84 = fmul double %mul17, %conv83
%call85 = tail call double @exp(double %mul84) nounwind %call85 = tail call double @exp(double %mul84) nounwind
%mul86 = fmul double %conv78, %call85 %mul86 = fmul double %conv78, %call85
%add88 = fadd double 0.000000e+00, %mul86 %add88 = fadd double 0.000000e+00, %mul86
Show All 25 Lines; CHECK: vldr
store float %conv150, ptr %ret_df, align 4 store float %conv150, ptr %ret_df, align 4
ret void ret void
} }
; CHECK: insert_elem ; CHECK: insert_elem
; This test has a sub-register copy with a kill flag: ; This test has a sub-register copy with a kill flag:
; %6:ssub_3 = COPY killed %6:ssub_2; QPR_VFP2:%6 ; %6:ssub_3 = COPY killed %6:ssub_2; QPR_VFP2:%6
; The rewriter must do something sensible with that, or the scavenger crashes. ; The rewriter must do something sensible with that, or the scavenger crashes.
define void @insert_elem() nounwind { define void @insert_elem(i1 %c0, i1 %c1) nounwind {
entry: entry:
br i1 undef, label %if.end251, label %if.then84 br i1 %c0, label %if.end251, label %if.then84
if.then84: ; preds = %entry if.then84: ; preds = %entry
br i1 undef, label %if.end251, label %if.then195 br i1 %c1, label %if.end251, label %if.then195
if.then195: ; preds = %if.then84 if.then195: ; preds = %if.then84
%div = fdiv float 1.000000e+00, undef %div = fdiv float 1.000000e+00, undef
%vecinit207 = insertelement <4 x float> undef, float %div, i32 1 %vecinit207 = insertelement <4 x float> undef, float %div, i32 1
%vecinit208 = insertelement <4 x float> %vecinit207, float 1.000000e+00, i32 2 %vecinit208 = insertelement <4 x float> %vecinit207, float 1.000000e+00, i32 2
%vecinit209 = insertelement <4 x float> %vecinit208, float 1.000000e+00, i32 3 %vecinit209 = insertelement <4 x float> %vecinit208, float 1.000000e+00, i32 3
%mul216 = fmul <4 x float> zeroinitializer, %vecinit209 %mul216 = fmul <4 x float> zeroinitializer, %vecinit209
store <4 x float> %mul216, ptr undef, align 16 store <4 x float> %mul216, ptr undef, align 16
br label %if.end251 br label %if.end251
if.end251: ; preds = %if.then195, %if.then84, %entry if.end251: ; preds = %if.then195, %if.then84, %entry
ret void ret void
} }
; Coalescer failure: removeCopyByCommutingDef leaves a bad kill flag ; Coalescer failure: removeCopyByCommutingDef leaves a bad kill flag
; behind. ; behind.
define void @rdar11950722() nounwind readonly optsize ssp align 2 { define void @rdar11950722(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5) nounwind readonly optsize ssp align 2 {
entry: entry:
br i1 undef, label %land.lhs.true7, label %lor.lhs.false.i br i1 %c0, label %land.lhs.true7, label %lor.lhs.false.i
lor.lhs.false.i: lor.lhs.false.i:
br i1 undef, label %if.then10.i, label %land.lhs.true7 br i1 %c1, label %if.then10.i, label %land.lhs.true7
if.then10.i: if.then10.i:
%xFlags.1.i = select i1 undef, i32 0, i32 undef %xFlags.1.i = select i1 undef, i32 0, i32 undef
br i1 undef, label %land.lhs.true33.i, label %f.exit br i1 %c2, label %land.lhs.true33.i, label %f.exit
land.lhs.true33.i: land.lhs.true33.i:
%and26.i = and i32 %xFlags.1.i, 8 %and26.i = and i32 %xFlags.1.i, 8
%cmp27.i = icmp eq i32 %and26.i, 0 %cmp27.i = icmp eq i32 %and26.i, 0
%and29.i = and i32 %xFlags.1.i, 2147483645 %and29.i = and i32 %xFlags.1.i, 2147483645
%xFlags.1.and29.i = select i1 %cmp27.i, i32 %xFlags.1.i, i32 %and29.i %xFlags.1.and29.i = select i1 %cmp27.i, i32 %xFlags.1.i, i32 %and29.i
%and34.i = and i32 %xFlags.1.i, 8 %and34.i = and i32 %xFlags.1.i, 8
%cmp35.i = icmp eq i32 %and34.i, 0 %cmp35.i = icmp eq i32 %and34.i, 0
%and37.i = and i32 %xFlags.1.i, 2147483645 %and37.i = and i32 %xFlags.1.i, 2147483645
%yFlags.1.and37.i = select i1 %cmp35.i, i32 %xFlags.1.i, i32 %and37.i %yFlags.1.and37.i = select i1 %cmp35.i, i32 %xFlags.1.i, i32 %and37.i
br label %f.exit br label %f.exit
f.exit: f.exit:
%xFlags.3.i = phi i32 [ %xFlags.1.and29.i, %land.lhs.true33.i ], [ %xFlags.1.i, %if.then10.i ] %xFlags.3.i = phi i32 [ %xFlags.1.and29.i, %land.lhs.true33.i ], [ %xFlags.1.i, %if.then10.i ]
%yFlags.2.i = phi i32 [ %yFlags.1.and37.i, %land.lhs.true33.i ], [ %xFlags.1.i, %if.then10.i ] %yFlags.2.i = phi i32 [ %yFlags.1.and37.i, %land.lhs.true33.i ], [ %xFlags.1.i, %if.then10.i ]
%cmp40.i = icmp eq i32 %xFlags.3.i, %yFlags.2.i %cmp40.i = icmp eq i32 %xFlags.3.i, %yFlags.2.i
br i1 %cmp40.i, label %land.lhs.true7, label %land.end br i1 %cmp40.i, label %land.lhs.true7, label %land.end
land.lhs.true7: land.lhs.true7:
br i1 undef, label %land.lhs.true34, label %lor.lhs.false27 br i1 %c3, label %land.lhs.true34, label %lor.lhs.false27
lor.lhs.false27: lor.lhs.false27:
br i1 undef, label %land.lhs.true34, label %land.end br i1 %c4, label %land.lhs.true34, label %land.end
land.lhs.true34: land.lhs.true34:
br i1 undef, label %land.end, label %lor.lhs.false44 br i1 %c5, label %land.end, label %lor.lhs.false44
lor.lhs.false44: lor.lhs.false44:
ret void ret void
land.end: land.end:
ret void ret void
} }

llvm/test/CodeGen/ARM/crash.ll

; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-arm-pseudo-expand ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-arm-pseudo-expand
; <rdar://problem/8529919> ; <rdar://problem/8529919>
%struct.foo = type { i32, i32 } %struct.foo = type { i32, i32 }
define void @func() nounwind { define void @func(i1 %c0, i1 %c1) nounwind {
entry: entry:
%tmp = load i32, ptr undef, align 4 %tmp = load i32, ptr undef, align 4
br label %bb1 br label %bb1
bb1: bb1:
%tmp1 = and i32 %tmp, 16 %tmp1 = and i32 %tmp, 16
%tmp2 = icmp eq i32 %tmp1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%invok.1.i = select i1 %tmp2, i32 undef, i32 0 %invok.1.i = select i1 %tmp2, i32 undef, i32 0
%tmp119 = add i32 %invok.1.i, 0 %tmp119 = add i32 %invok.1.i, 0
br i1 undef, label %bb2, label %exit br i1 %c0, label %bb2, label %exit
bb2: bb2:
%tmp120 = add i32 %tmp119, 0 %tmp120 = add i32 %tmp119, 0
%scevgep810.i = getelementptr %struct.foo, ptr null, i32 %tmp120, i32 1 %scevgep810.i = getelementptr %struct.foo, ptr null, i32 %tmp120, i32 1
store i32 undef, ptr %scevgep810.i, align 4 store i32 undef, ptr %scevgep810.i, align 4
br i1 undef, label %bb2, label %bb3 br i1 %c1, label %bb2, label %bb3
bb3: bb3:
br i1 %tmp2, label %bb2, label %bb2 br i1 %tmp2, label %bb2, label %bb2
exit: exit:
ret void ret void
} }
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llvm/test/CodeGen/ARM/debug-info-qreg.ll

Show All 11 Lines
;CHECK-NEXT: @ ;CHECK-NEXT: @
;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: DW_OP_piece
;CHECK-NEXT: 8 ;CHECK-NEXT: 8
@.str = external constant [13 x i8] @.str = external constant [13 x i8]
declare <4 x float> @test0001(float) nounwind readnone ssp declare <4 x float> @test0001(float) nounwind readnone ssp
define i32 @main(i32 %argc, ptr nocapture %argv, <4 x float> %x, <4 x float> %y) nounwind ssp !dbg !10 { define i32 @main(i32 %argc, ptr nocapture %argv, <4 x float> %x, <4 x float> %y, i1 %c0) nounwind ssp !dbg !10 {
entry: entry:
br label %for.body9 br label %for.body9
for.body9: ; preds = %for.body9, %entry for.body9: ; preds = %for.body9, %entry
%add19 = fadd <4 x float> %x, %y, !dbg !39 %add19 = fadd <4 x float> %x, %y, !dbg !39
br i1 undef, label %for.end54, label %for.body9, !dbg !44 br i1 %c0, label %for.end54, label %for.body9, !dbg !44
for.end54: ; preds = %for.body9 for.end54: ; preds = %for.body9
tail call void @llvm.dbg.value(metadata <4 x float> %add19, metadata !27, metadata !DIExpression()), !dbg !39 tail call void @llvm.dbg.value(metadata <4 x float> %add19, metadata !27, metadata !DIExpression()), !dbg !39
%tmp115 = extractelement <4 x float> %add19, i32 1 %tmp115 = extractelement <4 x float> %add19, i32 1
%conv6.i75 = fpext float %tmp115 to double, !dbg !45 %conv6.i75 = fpext float %tmp115 to double, !dbg !45
%call.i82 = tail call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 %call.i82 = tail call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
ret i32 0, !dbg !49 ret i32 0, !dbg !49
} }
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llvm/test/CodeGen/ARM/fcmp-xo.ll

Show All 12 Lines
; CHECK-NEXT: vmovmi.f32 s2, s4 ; CHECK-NEXT: vmovmi.f32 s2, s4
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%1 = fcmp nsz olt float %a0, 0.000000e+00 %1 = fcmp nsz olt float %a0, 0.000000e+00
%2 = select i1 %1, float -5.000000e-01, float 5.000000e-01 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
ret float %2 ret float %2
} }
define arm_aapcs_vfpcc float @float1(float %a0) local_unnamed_addr { define arm_aapcs_vfpcc float @float1(float %a0, i1 %c0) local_unnamed_addr {
; CHECK-LABEL: float1: ; CHECK-LABEL: float1:
; CHECK: @ %bb.0: @ %.end ; CHECK: @ %bb.0: @ %.end
; CHECK-NEXT: vmov.f32 s2, #1.000000e+00 ; CHECK-NEXT: vmov.f32 s2, #1.000000e+00
; CHECK-NEXT: vmov.f32 s4, #5.000000e-01 ; CHECK-NEXT: vmov.f32 s4, #5.000000e-01
; CHECK-NEXT: vmov.f32 s6, #-5.000000e-01 ; CHECK-NEXT: vmov.f32 s6, #-5.000000e-01
; CHECK-NEXT: vcmp.f32 s2, s0 ; CHECK-NEXT: vcmp.f32 s2, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f32 s0, s6, s4 ; CHECK-NEXT: vselgt.f32 s0, s6, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
br i1 undef, label %.end, label %1 br i1 %c0, label %.end, label %1
%2 = fcmp nsz olt float %a0, 1.000000e+00 %2 = fcmp nsz olt float %a0, 1.000000e+00
%3 = select i1 %2, float -5.000000e-01, float 5.000000e-01 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
br label %.end br label %.end
.end: .end:
%4 = phi float [ undef, %0 ], [ %3, %1] %4 = phi float [ undef, %0 ], [ %3, %1]
ret float %4 ret float %4
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llvm/test/CodeGen/ARM/i1.ll

; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
define i32 @test1() { define i32 @test1(i1 %c0) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: mov r0, #0 ; CHECK: mov r0, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
entry: entry:
br i1 undef, label %t, label %f br i1 %c0, label %t, label %f
t: t:
ret i32 4 ret i32 4
f: f:
ret i32 2 ret i32 2
} }

llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll

; RUN: llc < %s -mtriple=armv4t--linux-androideabi -stop-after=if-converter | FileCheck %s ; RUN: llc < %s -mtriple=armv4t--linux-androideabi -stop-after=if-converter | FileCheck %s
; Fix a bug triggered in IfConverterTriangle when CvtBB has multiple ; Fix a bug triggered in IfConverterTriangle when CvtBB has multiple
; predecessors. ; predecessors.
; PR18752 ; PR18752
%classK = type { i8, %classF } %classK = type { i8, %classF }
%classF = type { i8 } %classF = type { i8 }
%classL = type { %classG, i32, i32 } %classL = type { %classG, i32, i32 }
%classG = type { ptr } %classG = type { ptr }
%classM2 = type { %classL } %classM2 = type { %classL }
define zeroext i1 @test(ptr %this, ptr nocapture readnone %p0, ptr nocapture readnone %p1, ptr nocapture readnone %p2, i32 %a0) align 2 { define zeroext i1 @test(ptr %this, ptr nocapture readnone %p0, ptr nocapture readnone %p1, ptr nocapture readnone %p2, i32 %a0, i1 %c0, i1 %c1) align 2 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 %c0, label %for.end, label %for.body
; Before if conversion, we have ; Before if conversion, we have
; for.body -> lor.lhs.false.i (50%) ; for.body -> lor.lhs.false.i (50%)
; -> for.cond.backedge (50%) ; -> for.cond.backedge (50%)
; lor.lhs.false.i -> for.cond.backedge (100%) ; lor.lhs.false.i -> for.cond.backedge (100%)
; -> cond.false.i (0%) ; -> cond.false.i (0%)
; Afer if conversion, we have ; Afer if conversion, we have
; for.body -> for.cond.backedge (100%) ; for.body -> for.cond.backedge (100%)
; -> cond.false.i (0%) ; -> cond.false.i (0%)
; CHECK: bb.1.for.body: ; CHECK: bb.1.for.body:
; CHECK: successors: %bb.2(0x80000000), %bb.5(0x00000000) ; CHECK: successors: %bb.2(0x80000000), %bb.5(0x00000000)
for.body: for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1 br i1 %c1, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1
for.cond.backedge: for.cond.backedge:
%tobool = icmp eq ptr %p0, null %tobool = icmp eq ptr %p0, null
br i1 %tobool, label %for.end, label %for.body br i1 %tobool, label %for.end, label %for.body
lor.lhs.false.i: lor.lhs.false.i:
%tobool.i.i7 = icmp eq i32 %a0, 0 %tobool.i.i7 = icmp eq i32 %a0, 0
br i1 %tobool.i.i7, label %for.cond.backedge, label %cond.false.i br i1 %tobool.i.i7, label %for.cond.backedge, label %cond.false.i
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llvm/test/CodeGen/ARM/ifcvt10.ll

; RUN: llc < %s -mtriple=arm-apple-ios -arm-atomic-cfg-tidy=0 -mcpu=cortex-a9 | FileCheck %s ; RUN: llc < %s -mtriple=arm-apple-ios -arm-atomic-cfg-tidy=0 -mcpu=cortex-a9 | FileCheck %s
; rdar://8402126 ; rdar://8402126
; Make sure if-converter is not predicating vldmia and ldmia. These are ; Make sure if-converter is not predicating vldmia and ldmia. These are
; micro-coded and would have long issue latency even if predicated on ; micro-coded and would have long issue latency even if predicated on
; false predicate. ; false predicate.
define void @t(double %a, double %b, double %c, double %d, ptr nocapture %solutions, ptr nocapture %x) nounwind "frame-pointer"="all" { define void @t(double %a, double %b, double %c, double %d, ptr nocapture %solutions, ptr nocapture %x, i1 %c0) nounwind "frame-pointer"="all" {
entry: entry:
; CHECK-LABEL: t: ; CHECK-LABEL: t:
; CHECK: vpop {d8} ; CHECK: vpop {d8}
; CHECK-NOT: vpopne ; CHECK-NOT: vpopne
; CHECK: pop {r7, pc} ; CHECK: pop {r7, pc}
br i1 undef, label %if.else, label %if.then br i1 %c0, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%mul73 = fmul double %a, 0.000000e+00 %mul73 = fmul double %a, 0.000000e+00
%sub76 = fsub double %mul73, %mul73 %sub76 = fsub double %mul73, %mul73
store double %sub76, ptr undef, align 4 store double %sub76, ptr undef, align 4
%call88 = tail call double @cos(double 0.000000e+00) nounwind %call88 = tail call double @cos(double 0.000000e+00) nounwind
%mul89 = fmul double %call88, %call88 %mul89 = fmul double %call88, %call88
%sub92 = fsub double %mul89, %mul89 %sub92 = fsub double %mul89, %mul89
Show All 13 Lines

llvm/test/CodeGen/ARM/ifcvt9.ll

; RUN: llc -mtriple=arm-eabi %s -o /dev/null ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
define fastcc void @t() nounwind { define fastcc void @t(i1 %c0) nounwind {
entry: entry:
br i1 undef, label %bb.i.i3, label %growMapping.exit br i1 %c0, label %bb.i.i3, label %growMapping.exit
bb.i.i3: ; preds = %entry bb.i.i3: ; preds = %entry
unreachable unreachable
growMapping.exit: ; preds = %entry growMapping.exit: ; preds = %entry
unreachable unreachable
} }

llvm/test/CodeGen/ARM/interval-update-remat.ll

; RUN: llc -verify-regalloc < %s ; RUN: llc -verify-regalloc < %s
; PR27275: When enabling remat for vreg defined by PHIs, make sure the update
; of the live range removes dead phi. Otherwise, we may end up with PHIs with ; of the live range removes dead phi. Otherwise, we may end up with PHIs with
; incorrect operands and that will trigger assertions or verifier failures ; incorrect operands and that will trigger assertions or verifier failures
; in later passes. ; in later passes.
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7-apple-ios9.0.0" target triple = "thumbv7-apple-ios9.0.0"
%class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326 = type { %class.MockTransportClientSocketPool.0.225.275.1300.2325, i32 } %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326 = type { %class.MockTransportClientSocketPool.0.225.275.1300.2325, i32 }
Show All 19 Lines
%class.BoundNetLog.20.245.295.1320.2345 = type { i32 } %class.BoundNetLog.20.245.295.1320.2345 = type { i32 }
%struct.MockReadWrite.7.232.282.1307.2332 = type { i32 } %struct.MockReadWrite.7.232.282.1307.2332 = type { i32 }
%"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347" = type { i8 } %"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347" = type { i8 }
%class.ClientSocketHandle.14.239.289.1314.2339 = type { i8 } %class.ClientSocketHandle.14.239.289.1314.2339 = type { i8 }
%"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346" = type { i8 } %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346" = type { i8 }
@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 @.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
define void @_ZN53SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test6m_fn10Ev(ptr %this) align 2 { define void @_ZN53SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test6m_fn10Ev(ptr %this, i1 %c0, i1 %c1, i1 %c2) align 2 {
entry: entry:
%socket_data = alloca %class.StaticSocketDataProvider.6.231.281.1306.2331, align 1 %socket_data = alloca %class.StaticSocketDataProvider.6.231.281.1306.2331, align 1
%agg.tmp = alloca %struct.MockConnect.5.230.280.1305.2330, align 1 %agg.tmp = alloca %struct.MockConnect.5.230.280.1305.2330, align 1
%callback = alloca %class.TestCompletionCallback.9.234.284.1309.2334, align 4 %callback = alloca %class.TestCompletionCallback.9.234.284.1309.2334, align 4
%gtest_ar = alloca %class.AssertionResult.24.249.299.1324.2349, align 4 %gtest_ar = alloca %class.AssertionResult.24.249.299.1324.2349, align 4
%temp.lvalue = alloca %class.AssertHelper.10.235.285.1310.2335, align 1 %temp.lvalue = alloca %class.AssertHelper.10.235.285.1310.2335, align 1
%agg.tmp10 = alloca %class.Message.13.238.288.1313.2338, align 4 %agg.tmp10 = alloca %class.Message.13.238.288.1313.2338, align 4
%ref.tmp = alloca %class.Trans_NS___1_basic_string.18.243.293.1318.2343, align 4 %ref.tmp = alloca %class.Trans_NS___1_basic_string.18.243.293.1318.2343, align 4
%agg.tmp16 = alloca %class.scoped_refptr.19.244.294.1319.2344, align 1 %agg.tmp16 = alloca %class.scoped_refptr.19.244.294.1319.2344, align 1
%agg.tmp18 = alloca %class.BoundNetLog.20.245.295.1320.2345, align 4 %agg.tmp18 = alloca %class.BoundNetLog.20.245.295.1320.2345, align 4
%call2 = call ptr @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(ptr nonnull %socket_data, ptr undef, i32 1, ptr null, i32 0) %call2 = call ptr @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(ptr nonnull %socket_data, ptr undef, i32 1, ptr null, i32 0)
%call3 = call ptr @_ZN11MockConnectC1Ev(ptr nonnull %agg.tmp) %call3 = call ptr @_ZN11MockConnectC1Ev(ptr nonnull %agg.tmp)
call void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(ptr nonnull %socket_data, ptr nonnull %agg.tmp) call void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(ptr nonnull %socket_data, ptr nonnull %agg.tmp)
%call5 = call ptr @_ZN22TestCompletionCallbackC1Ev(ptr nonnull %callback) %call5 = call ptr @_ZN22TestCompletionCallbackC1Ev(ptr nonnull %callback)
%call6 = call i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(ptr %this) %call6 = call i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(ptr %this)
call void @_Z11CmpHelperEQPcS_xx(ptr nonnull sret(%class.AssertionResult.24.249.299.1324.2349) %gtest_ar, ptr @.str, ptr @.str, i64 0, i64 undef) call void @_Z11CmpHelperEQPcS_xx(ptr nonnull sret(%class.AssertionResult.24.249.299.1324.2349) %gtest_ar, ptr @.str, ptr @.str, i64 0, i64 undef)
%tmp = load i8, ptr undef, align 4 %tmp = load i8, ptr undef, align 4
%tobool.i = icmp eq i8 %tmp, 0 %tobool.i = icmp eq i8 %tmp, 0
br i1 %tobool.i, label %if.else, label %if.end br i1 %tobool.i, label %if.else, label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
br i1 undef, label %_ZN15AssertionResult5m_fn6Ev.exit, label %cond.true.i br i1 %c0, label %_ZN15AssertionResult5m_fn6Ev.exit, label %cond.true.i
cond.true.i: ; preds = %if.else cond.true.i: ; preds = %if.else
%call4.i = call ptr @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(ptr nonnull undef) %call4.i = call ptr @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(ptr nonnull undef)
br label %_ZN15AssertionResult5m_fn6Ev.exit br label %_ZN15AssertionResult5m_fn6Ev.exit
_ZN15AssertionResult5m_fn6Ev.exit: ; preds = %cond.true.i, %if.else _ZN15AssertionResult5m_fn6Ev.exit: ; preds = %cond.true.i, %if.else
%cond.i = phi ptr [ %call4.i, %cond.true.i ], [ @.str, %if.else ] %cond.i = phi ptr [ %call4.i, %cond.true.i ], [ @.str, %if.else ]
%call9 = call ptr @_ZN12AssertHelperC1EPKc(ptr nonnull %temp.lvalue, ptr %cond.i) %call9 = call ptr @_ZN12AssertHelperC1EPKc(ptr nonnull %temp.lvalue, ptr %cond.i)
%call11 = call ptr @_ZN7MessageC1Ev(ptr nonnull %agg.tmp10) %call11 = call ptr @_ZN7MessageC1Ev(ptr nonnull %agg.tmp10)
call void @_ZN12AssertHelperaSE7Message(ptr nonnull %temp.lvalue, ptr nonnull %agg.tmp10) call void @_ZN12AssertHelperaSE7Message(ptr nonnull %temp.lvalue, ptr nonnull %agg.tmp10)
%call.i.i.i.i27 = call zeroext i1 @_Z6IsTruev() %call.i.i.i.i27 = call zeroext i1 @_Z6IsTruev()
%brmerge = or i1 false, undef %brmerge = or i1 false, %c1
br i1 %brmerge, label %_ZN7MessageD1Ev.exit33, label %delete.notnull.i.i.i.i32 br i1 %brmerge, label %_ZN7MessageD1Ev.exit33, label %delete.notnull.i.i.i.i32
delete.notnull.i.i.i.i32: ; preds = %_ZN15AssertionResult5m_fn6Ev.exit delete.notnull.i.i.i.i32: ; preds = %_ZN15AssertionResult5m_fn6Ev.exit
%call.i.i.i.i.i.i31 = call ptr @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(ptr undef) %call.i.i.i.i.i.i31 = call ptr @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(ptr undef)
call void @_ZdlPv(ptr undef) call void @_ZdlPv(ptr undef)
br label %_ZN7MessageD1Ev.exit33 br label %_ZN7MessageD1Ev.exit33
_ZN7MessageD1Ev.exit33: ; preds = %delete.notnull.i.i.i.i32, %_ZN15AssertionResult5m_fn6Ev.exit _ZN7MessageD1Ev.exit33: ; preds = %delete.notnull.i.i.i.i32, %_ZN15AssertionResult5m_fn6Ev.exit
%call13 = call ptr @_ZN12AssertHelperD1Ev(ptr nonnull %temp.lvalue) %call13 = call ptr @_ZN12AssertHelperD1Ev(ptr nonnull %temp.lvalue)
br label %if.end br label %if.end
if.end: ; preds = %_ZN7MessageD1Ev.exit33, %entry if.end: ; preds = %_ZN7MessageD1Ev.exit33, %entry
%message_.i.i = getelementptr inbounds %class.AssertionResult.24.249.299.1324.2349, ptr %gtest_ar, i32 0, i32 1 %message_.i.i = getelementptr inbounds %class.AssertionResult.24.249.299.1324.2349, ptr %gtest_ar, i32 0, i32 1
%call.i.i.i = call ptr @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(ptr %message_.i.i) %call.i.i.i = call ptr @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(ptr %message_.i.i)
call void @llvm.memset.p0.i32(ptr align 4 null, i8 0, i32 12, i1 false) call void @llvm.memset.p0.i32(ptr align 4 null, i8 0, i32 12, i1 false)
call void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(ptr nonnull %ref.tmp) call void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(ptr nonnull %ref.tmp)
call void @_Z19CreateSOCKSv5Paramsv(ptr nonnull sret(%class.scoped_refptr.19.244.294.1319.2344) %agg.tmp16) call void @_Z19CreateSOCKSv5Paramsv(ptr nonnull sret(%class.scoped_refptr.19.244.294.1319.2344) %agg.tmp16)
%callback_.i = getelementptr inbounds %class.TestCompletionCallback.9.234.284.1309.2334, ptr %callback, i32 0, i32 1 %callback_.i = getelementptr inbounds %class.TestCompletionCallback.9.234.284.1309.2334, ptr %callback, i32 0, i32 1
%pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, ptr %this, i32 0, i32 1 %pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, ptr %this, i32 0, i32 1
store i32 0, ptr %agg.tmp18, align 4 store i32 0, ptr %agg.tmp18, align 4
call void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(ptr nonnull undef, ptr nonnull dereferenceable(12) %ref.tmp, ptr nonnull %agg.tmp16, i32 0, i32 1, ptr nonnull dereferenceable(4) %callback_.i, ptr %pool_, ptr nonnull %agg.tmp18) call void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(ptr nonnull undef, ptr nonnull dereferenceable(12) %ref.tmp, ptr nonnull %agg.tmp16, i32 0, i32 1, ptr nonnull dereferenceable(4) %callback_.i, ptr %pool_, ptr nonnull %agg.tmp18)
%call19 = call ptr @_ZN11BoundNetLogD1Ev(ptr nonnull %agg.tmp18) %call19 = call ptr @_ZN11BoundNetLogD1Ev(ptr nonnull %agg.tmp18)
call void @_Z11CmpHelperEQPcS_xx(ptr nonnull sret(%class.AssertionResult.24.249.299.1324.2349) undef, ptr @.str, ptr @.str, i64 -1, i64 0) call void @_Z11CmpHelperEQPcS_xx(ptr nonnull sret(%class.AssertionResult.24.249.299.1324.2349) undef, ptr @.str, ptr @.str, i64 -1, i64 0)
br i1 undef, label %if.then.i.i.i.i, label %_ZN7MessageD1Ev.exit br i1 %c2, label %if.then.i.i.i.i, label %_ZN7MessageD1Ev.exit
if.then.i.i.i.i: ; preds = %if.end if.then.i.i.i.i: ; preds = %if.end
%tmp2 = load ptr, ptr undef, align 4 %tmp2 = load ptr, ptr undef, align 4
br label %_ZN7MessageD1Ev.exit br label %_ZN7MessageD1Ev.exit
_ZN7MessageD1Ev.exit: ; preds = %if.then.i.i.i.i, %if.end _ZN7MessageD1Ev.exit: ; preds = %if.then.i.i.i.i, %if.end
%connect_.i.i = getelementptr inbounds %class.StaticSocketDataProvider.6.231.281.1306.2331, ptr %socket_data, i32 0, i32 1 %connect_.i.i = getelementptr inbounds %class.StaticSocketDataProvider.6.231.281.1306.2331, ptr %socket_data, i32 0, i32 1
%call.i.i.i.i.i.i.i.i.i.i = call ptr @_ZN12_GLOBAL__N_113__vector_baseD2Ev(ptr %connect_.i.i) %call.i.i.i.i.i.i.i.i.i.i = call ptr @_ZN12_GLOBAL__N_113__vector_baseD2Ev(ptr %connect_.i.i)
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ldrcppic.ll

; The failure is caused by ARM LDRcp/PICADD pairs. In PIC mode, the constant pool ; The failure is caused by ARM LDRcp/PICADD pairs. In PIC mode, the constant pool
; need a label to do address computation. This label is emitted when backend emits ; need a label to do address computation. This label is emitted when backend emits
; PICADD. When the target becomes dead, PICADD will be deleted. without this patch ; PICADD. When the target becomes dead, PICADD will be deleted. without this patch
; LDRcp is dead but not being deleted. This will cause a dead contant pool entry ; LDRcp is dead but not being deleted. This will cause a dead contant pool entry
; using a non existing label. This will cause an error in MC object emitting pass. ; using a non existing label. This will cause an error in MC object emitting pass.
; RUN: llc -relocation-model=pic -mcpu=cortex-a53 %s -filetype=obj -o - | llvm-nm - | FileCheck %s ; RUN: llc -relocation-model=pic -mcpu=cortex-a53 %s -filetype=obj -o - | llvm-nm - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8-unknown-linux-android" target triple = "armv8-unknown-linux-android"
@_ZN15UsecaseSelector25AllowedImplDefinedFormatsE = external dso_local unnamed_addr constant <{ i32, i32, i32, i32, [12 x i32] }>, align 4 @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE = external dso_local unnamed_addr constant <{ i32, i32, i32, i32, [12 x i32] }>, align 4
; Function Attrs: noinline nounwind optnone sspstrong uwtable ; Function Attrs: noinline nounwind optnone sspstrong uwtable
define dso_local fastcc void @_ZN15UsecaseSelector26IsAllowedImplDefinedFormatE15ChiBufferFormatj() unnamed_addr #1 align 2 { define dso_local fastcc void @_ZN15UsecaseSelector26IsAllowedImplDefinedFormatE15ChiBufferFormatj(i1 %c0, i1 %c1, i1 %c2, i1 %c3) unnamed_addr #1 align 2 {
br label %1 br label %1
; <label>:1: ; preds = %13, %0 ; <label>:1: ; preds = %13, %0
%2 = icmp ult i32 undef, 4 %2 = icmp ult i32 undef, 4
br i1 %2, label %3, label %14 br i1 %2, label %3, label %14
; <label>:3: ; preds = %1 ; <label>:3: ; preds = %1
br i1 undef, label %4, label %13 br i1 %c0, label %4, label %13
; <label>:4: ; preds = %3 ; <label>:4: ; preds = %3
%5 = getelementptr inbounds [16 x i32], ptr bitcast (<{ i32, i32, i32, i32, [12 x i32] }>* @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE to ptr), i32 0, i32 undef %5 = getelementptr inbounds [16 x i32], ptr bitcast (<{ i32, i32, i32, i32, [12 x i32] }>* @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE to ptr), i32 0, i32 undef
%6 = load i32, ptr %5, align 4 %6 = load i32, ptr %5, align 4
%7 = icmp eq i32 10, %6 %7 = icmp eq i32 10, %6
br i1 %7, label %9, label %8 br i1 %7, label %9, label %8
; <label>:8: ; preds = %4 ; <label>:8: ; preds = %4
br i1 undef, label %9, label %12 br i1 %c1, label %9, label %12
; <label>:9: ; preds = %8, %4 ; <label>:9: ; preds = %8, %4
br i1 undef, label %10, label %13 br i1 %c2, label %10, label %13
; <label>:10: ; preds = %9 ; <label>:10: ; preds = %9
br i1 undef, label %11, label %13 br i1 %c3, label %11, label %13
; <label>:11: ; preds = %10 ; <label>:11: ; preds = %10
br label %14 br label %14
; <label>:12: ; preds = %8 ; <label>:12: ; preds = %8
br label %14 br label %14
; <label>:13: ; preds = %10, %9, %3 ; <label>:13: ; preds = %10, %9, %3
Show All 10 Lines

llvm/test/CodeGen/ARM/machine-sink-multidef.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm-none-eabi | FileCheck %s ; RUN: llc < %s -mtriple=arm-none-eabi | FileCheck %s
%struct.anon.1.19.23.27.35.49.55.57.59.61.89.95 = type { i32, i32 } %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95 = type { i32, i32 }
@e = external constant [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], align 4 @e = external constant [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], align 4
@f = external global i32, align 4 @f = external global i32, align 4
define arm_aapcscc void @g() { define arm_aapcscc void @g(i1 %c0, i1 %c1) {
; CHECK-LABEL: g: ; CHECK-LABEL: g:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r11, lr} ; CHECK-NEXT: .save {r11, lr}
; CHECK-NEXT: push {r11, lr} ; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: ldr r0, .LCPI0_0 ; CHECK-NEXT: ldr r0, .LCPI0_0
; CHECK-NEXT: mov r2, #0 ; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: ldr r1, .LCPI0_1 ; CHECK-NEXT: ldr r1, .LCPI0_1
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
Show All 13 Lines
; CHECK-NEXT: .LCPI0_1: ; CHECK-NEXT: .LCPI0_1:
; CHECK-NEXT: .long e ; CHECK-NEXT: .long e
entry: entry:
%0 = load i32, ptr @f, align 4 %0 = load i32, ptr @f, align 4
%c = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], ptr @e, i32 0, i32 %0, i32 0 %c = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], ptr @e, i32 0, i32 %0, i32 0
%1 = load i32, ptr %c, align 4 %1 = load i32, ptr %c, align 4
%d = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], ptr @e, i32 0, i32 %0, i32 1 %d = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], ptr @e, i32 0, i32 %0, i32 1
%2 = load i32, ptr %d, align 4 %2 = load i32, ptr %d, align 4
br i1 undef, label %land.lhs.true, label %if.end br i1 %c0, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
br label %if.end br label %if.end
if.end: ; preds = %land.lhs.true, %entry if.end: ; preds = %land.lhs.true, %entry
%h.0 = phi i32 [ %1, %entry ], [ 0, %land.lhs.true ] %h.0 = phi i32 [ %1, %entry ], [ 0, %land.lhs.true ]
br i1 undef, label %if.end7, label %if.then5 br i1 %c1, label %if.end7, label %if.then5
if.then5: ; preds = %if.end if.then5: ; preds = %if.end
%call6 = call arm_aapcscc i32 @k(i32 %h.0, i32 %2) %call6 = call arm_aapcscc i32 @k(i32 %h.0, i32 %2)
unreachable unreachable
if.end7: ; preds = %if.end if.end7: ; preds = %if.end
ret void ret void
} }
declare arm_aapcscc i32 @k(...) declare arm_aapcscc i32 @k(...)

llvm/test/CodeGen/ARM/pr13249.ll

; RUN: llc < %s -mtriple armv7--linux-gnueabi ; RUN: llc < %s -mtriple armv7--linux-gnueabi
define arm_aapcscc ptr @__strtok_r_1c(ptr %arg, i8 signext %arg1, ptr nocapture %arg2) nounwind { define arm_aapcscc ptr @__strtok_r_1c(ptr %arg, i8 signext %arg1, ptr nocapture %arg2, i1 %c0) nounwind {
bb: bb:
br label %bb3 br label %bb3
bb3: ; preds = %bb3, %bb bb3: ; preds = %bb3, %bb
%tmp = phi ptr [ %tmp5, %bb3 ], [ %arg, %bb ] %tmp = phi ptr [ %tmp5, %bb3 ], [ %arg, %bb ]
%tmp4 = load i8, ptr %tmp, align 1 %tmp4 = load i8, ptr %tmp, align 1
%tmp5 = getelementptr inbounds i8, ptr %tmp, i32 1 %tmp5 = getelementptr inbounds i8, ptr %tmp, i32 1
br i1 undef, label %bb3, label %bb7 br i1 %c0, label %bb3, label %bb7
bb7: ; preds = %bb13, %bb3 bb7: ; preds = %bb13, %bb3
%tmp8 = phi i8 [ %tmp14, %bb13 ], [ %tmp4, %bb3 ] %tmp8 = phi i8 [ %tmp14, %bb13 ], [ %tmp4, %bb3 ]
%tmp9 = phi ptr [ %tmp12, %bb13 ], [ %tmp, %bb3 ] %tmp9 = phi ptr [ %tmp12, %bb13 ], [ %tmp, %bb3 ]
%tmp10 = icmp ne i8 %tmp8, %arg1 %tmp10 = icmp ne i8 %tmp8, %arg1
%tmp12 = getelementptr inbounds i8, ptr %tmp9, i32 1 %tmp12 = getelementptr inbounds i8, ptr %tmp9, i32 1
br i1 %tmp10, label %bb13, label %bb15 br i1 %tmp10, label %bb13, label %bb15
bb13: ; preds = %bb7 bb13: ; preds = %bb7
%tmp14 = load i8, ptr %tmp12, align 1 %tmp14 = load i8, ptr %tmp12, align 1
br label %bb7 br label %bb7
bb15: ; preds = %bb7 bb15: ; preds = %bb7
store ptr %tmp9, ptr %arg2, align 4 store ptr %tmp9, ptr %arg2, align 4
ret ptr %tmp ret ptr %tmp
} }

llvm/test/CodeGen/ARM/pr25838.ll

; RUN: llc -verify-machineinstrs < %s ; RUN: llc -verify-machineinstrs < %s
; PR25838 ; PR25838
target triple = "armv7--linux-android" target triple = "armv7--linux-android"
%0 = type { i32, i32 } %0 = type { i32, i32 }
define i32 @foo(ptr readonly) { define i32 @foo(ptr readonly, i1 %c0, i1 %c1) {
br i1 undef, label %12, label %2 br i1 %c0, label %12, label %2
; <label>:2 ; <label>:2
%3 = trunc i64 undef to i32 %3 = trunc i64 undef to i32
%4 = icmp eq i32 undef, 0 %4 = icmp eq i32 undef, 0
br i1 %4, label %5, label %9 br i1 %4, label %5, label %9
; <label>:5 ; <label>:5
%6 = icmp slt i32 %3, 0 %6 = icmp slt i32 %3, 0
%7 = sub nsw i32 0, %3 %7 = sub nsw i32 0, %3
%8 = select i1 %6, i32 %7, i32 %3 %8 = select i1 %6, i32 %7, i32 %3
br label %12 br label %12
; <label>:9 ; <label>:9
br i1 undef, label %12, label %10 br i1 %c1, label %12, label %10
; <label>:10 ; <label>:10
%11 = tail call i32 @bar(i32 undef) %11 = tail call i32 @bar(i32 undef)
unreachable unreachable
; <label>:12 ; <label>:12
%13 = phi i32 [ %8, %5 ], [ 0, %1 ], [ undef, %9 ] %13 = phi i32 [ %8, %5 ], [ 0, %1 ], [ undef, %9 ]
ret i32 %13 ret i32 %13
} }
declare i32 @bar(i32) declare i32 @bar(i32)

llvm/test/CodeGen/ARM/reg_sequence.ll

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines; CHECK: vst3.8
%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1]
%tmp5 = sub <8 x i8> %tmp3, %tmp4 %tmp5 = sub <8 x i8> %tmp3, %tmp4
%tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1] %tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1]
%tmp7 = mul <8 x i8> %tmp4, %tmp2 %tmp7 = mul <8 x i8> %tmp4, %tmp2
tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1) tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)
ret <8 x i8> %tmp4 ret <8 x i8> %tmp4
} }
define void @t4(ptr %in, ptr %out) nounwind { define void @t4(ptr %in, ptr %out, i1 %c0) nounwind {
entry: entry:
; CHECK-LABEL: t4: ; CHECK-LABEL: t4:
; CHECK: vld2.32 ; CHECK: vld2.32
; CHECK-NOT: vmov ; CHECK-NOT: vmov
; CHECK: vld2.32 ; CHECK: vld2.32
; CHECK-NOT: vmov ; CHECK-NOT: vmov
; CHECK: bne ; CHECK: bne
%tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %in, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %in, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
%tmp3 = getelementptr inbounds i32, ptr %in, i32 8 ; <ptr> [#uses=1] %tmp3 = getelementptr inbounds i32, ptr %in, i32 8 ; <ptr> [#uses=1]
%tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %tmp3, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %tmp3, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
br i1 undef, label %return1, label %return2 br i1 %c0, label %return1, label %return2
return1: return1:
; CHECK: %return1 ; CHECK: %return1
; CHECK-NOT: vmov ; CHECK-NOT: vmov
; CHECK-NEXT: vadd.i32 ; CHECK-NEXT: vadd.i32
; CHECK-NEXT: vadd.i32 ; CHECK-NEXT: vadd.i32
; CHECK-NEXT: vst2.32 ; CHECK-NEXT: vst2.32
%tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] %tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines; CHECK: vst1.32
tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %optr, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1) tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %optr, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)
%1 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr %iptr, i32 1) ; <<4 x i32>> [#uses=1] %1 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr %iptr, i32 1) ; <<4 x i32>> [#uses=1]
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1] %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1]
tail call void @llvm.arm.neon.vst1.p0.v4i32(ptr %optr, <4 x i32> %2, i32 1) tail call void @llvm.arm.neon.vst1.p0.v4i32(ptr %optr, <4 x i32> %2, i32 1)
ret void ret void
} }
; PR7156 ; PR7156
define arm_aapcs_vfpcc i32 @t8() nounwind { define arm_aapcs_vfpcc i32 @t8(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind {
; CHECK-LABEL: t8: ; CHECK-LABEL: t8:
; CHECK: vrsqrte.f32 q8, q8 ; CHECK: vrsqrte.f32 q8, q8
bb.nph55.bb.nph55.split_crit_edge: bb.nph55.bb.nph55.split_crit_edge:
br label %bb3 br label %bb3
bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
br i1 undef, label %bb5, label %bb3 br i1 %c0, label %bb5, label %bb3
bb5: ; preds = %bb3 bb5: ; preds = %bb3
br label %bb.i25 br label %bb.i25
bb.i25: ; preds = %bb.i25, %bb5 bb.i25: ; preds = %bb.i25, %bb5
%0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] %0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
%1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1] %1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1]
%2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=1] %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=1]
%3 = fmul <4 x float> %2, %2 ; <<4 x float>> [#uses=1] %3 = fmul <4 x float> %2, %2 ; <<4 x float>> [#uses=1]
%tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1] %tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1]
%4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1] %4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1]
%5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1] %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1]
%6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1] %6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1]
store float %6, ptr undef, align 4 store float %6, ptr undef, align 4
br i1 undef, label %bb6, label %bb.i25 br i1 %c1, label %bb6, label %bb.i25
bb6: ; preds = %bb.i25 bb6: ; preds = %bb.i25
br i1 undef, label %bb7, label %bb14 br i1 %c2, label %bb7, label %bb14
bb7: ; preds = %bb6 bb7: ; preds = %bb6
br label %bb.i49 br label %bb.i49
bb.i49: ; preds = %bb.i49, %bb7 bb.i49: ; preds = %bb.i49, %bb7
br i1 undef, label %bb.i19, label %bb.i49 br i1 %c3, label %bb.i19, label %bb.i49
bb.i19: ; preds = %bb.i19, %bb.i49 bb.i19: ; preds = %bb.i19, %bb.i49
br i1 undef, label %exit, label %bb.i19 br i1 %c4, label %exit, label %bb.i19
exit: ; preds = %bb.i19 exit: ; preds = %bb.i19
unreachable unreachable
bb14: ; preds = %bb6 bb14: ; preds = %bb6
ret i32 0 ret i32 0
} }
Show All 28 Lines
; <label>:9 ; preds = %8 ; <label>:9 ; preds = %8
ret float undef ret float undef
; <label>:10 ; preds = %6 ; <label>:10 ; preds = %6
ret float 9.990000e+02 ret float 9.990000e+02
} }
; PR7162 ; PR7162
define arm_aapcs_vfpcc i32 @t10(float %x) nounwind { define arm_aapcs_vfpcc i32 @t10(float %x, i1 %c0) nounwind {
; CHECK-LABEL: t10: ; CHECK-LABEL: t10:
; CHECK: vdup.32 [[Q0:q[0-9]+]], d0[0] ; CHECK: vdup.32 [[Q0:q[0-9]+]], d0[0]
; CHECK: vmov.i32 [[Q9:q[0-9]+]], #0x3f000000 ; CHECK: vmov.i32 [[Q9:q[0-9]+]], #0x3f000000
; CHECK: vmul.f32 [[Q8:q[0-9]+]], [[Q0]], [[Q0]] ; CHECK: vmul.f32 [[Q8:q[0-9]+]], [[Q0]], [[Q0]]
; CHECK-NEXT: vadd.f32 [[Q8]], [[Q8]], [[Q8]] ; CHECK-NEXT: vadd.f32 [[Q8]], [[Q8]], [[Q8]]
; CHECK-NEXT: vadd.f32 [[Q1:q[0-9]+]], [[Q8]], [[Q8]] ; CHECK-NEXT: vadd.f32 [[Q1:q[0-9]+]], [[Q8]], [[Q8]]
; CHECK-NEXT: vmul.f32 [[Q8]], [[Q9]], d1[0] ; CHECK-NEXT: vmul.f32 [[Q8]], [[Q9]], d1[0]
; CHECK-NEXT: vmul.f32 [[Q8]], [[Q8]], [[Q8]] ; CHECK-NEXT: vmul.f32 [[Q8]], [[Q8]], [[Q8]]
Show All 22 Linesentry:
%12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] %12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
%13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%14 = fmul <4 x float> %13, %13 %14 = fmul <4 x float> %13, %13
%15 = fadd <4 x float> %14, %14 %15 = fadd <4 x float> %14, %14
%16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1] %16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
%17 = fmul <4 x float> %16, %16 %17 = fmul <4 x float> %16, %16
%18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1] %18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1]
store float %18, ptr undef, align 4 store float %18, ptr undef, align 4
br i1 undef, label %exit, label %bb14 br i1 %c0, label %exit, label %bb14
exit: ; preds = %bb.i19 exit: ; preds = %bb.i19
unreachable unreachable
bb14: ; preds = %bb6 bb14: ; preds = %bb6
ret i32 0 ret i32 0
} }
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llvm/test/CodeGen/ARM/splitkit.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
declare i32 @wobble.58(ptr, [1 x i32], ptr , ptr ) declare i32 @wobble.58(ptr, [1 x i32], ptr , ptr )
declare i32 @widget(ptr, [1 x i32], ptr , ptr ) declare i32 @widget(ptr, [1 x i32], ptr , ptr )
; Just check we didn't crash and did output something... ; Just check we didn't crash and did output something...
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: trap ; CHECK: trap
define internal void @func() section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @quux { define internal void @func(i1 %c0) section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @quux {
%tmp = tail call i32 @__cxa_atexit(ptr @bar, ptr @global.3, ptr @global) #0 %tmp = tail call i32 @__cxa_atexit(ptr @bar, ptr @global.3, ptr @global) #0
%tmp2 = invoke ptr @wobble(ptr undef, ptr @global.9) %tmp2 = invoke ptr @wobble(ptr undef, ptr @global.9)
to label %bb14 unwind label %bbunwind to label %bb14 unwind label %bbunwind
bb14: bb14:
%tmp15 = getelementptr i8, ptr undef, i32 12 %tmp15 = getelementptr i8, ptr undef, i32 12
store i8 0, ptr %tmp15 store i8 0, ptr %tmp15
%tmp16 = icmp eq i8 undef, 0 %tmp16 = icmp eq i8 undef, 0
br i1 %tmp16, label %bb28, label %bb18 br i1 %tmp16, label %bb28, label %bb18
bb18: bb18:
br i1 undef, label %bb21, label %bb29 br i1 %c0, label %bb21, label %bb29
bb21: bb21:
%tmp22 = call ptr @_Znwm(i32 16) %tmp22 = call ptr @_Znwm(i32 16)
store i32 17, ptr @global.10 store i32 17, ptr @global.10
%tmp23 = call ptr @_Znwm(i32 32) %tmp23 = call ptr @_Znwm(i32 32)
call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.2, i32 26, i1 false) call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.2, i32 26, i1 false)
store i32 33, ptr @global.11 store i32 33, ptr @global.11
store i32 23, ptr getelementptr (%struct.ham, ptr @global.11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1) store i32 23, ptr getelementptr (%struct.ham, ptr @global.11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
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llvm/test/CodeGen/ARM/unschedule-first-call.ll

; RUN: llc -verify-machineinstrs < %s ; RUN: llc -verify-machineinstrs < %s
; PR30911 ; PR30911
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv6kz--linux-gnueabihf" target triple = "armv6kz--linux-gnueabihf"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @dradbg(i32, i32, ptr, ptr, ptr, ptr, ptr) #0 { define void @dradbg(i32, i32, ptr, ptr, ptr, ptr, ptr, i1 %c0, i1 %c1, i1 %c2) #0 {
br i1 undef, label %.critedge, label %8 br i1 %c0, label %.critedge, label %8
.critedge: ; preds = %7 .critedge: ; preds = %7
%.mux2 = select i1 undef, i1 undef, i1 true %.mux2 = select i1 undef, i1 undef, i1 true
br label %8 br label %8
; <label>:8: ; preds = %.critedge, %7 ; <label>:8: ; preds = %.critedge, %7
%9 = getelementptr float, ptr %3, i64 undef %9 = getelementptr float, ptr %3, i64 undef
%10 = ptrtoint ptr %9 to i32 %10 = ptrtoint ptr %9 to i32
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines; <label>:8: ; preds = %.critedge, %7
%91 = and i1 %90, undef %91 = and i1 %90, undef
%92 = and i1 %91, undef %92 = and i1 %91, undef
%93 = and i1 %92, undef %93 = and i1 %92, undef
%94 = and i1 %93, undef %94 = and i1 %93, undef
%95 = and i1 %94, undef %95 = and i1 %94, undef
br i1 %95, label %97, label %96 br i1 %95, label %97, label %96
; <label>:96: ; preds = %8 ; <label>:96: ; preds = %8
br i1 undef, label %.critedge122, label %.critedge110 br i1 %c1, label %.critedge122, label %.critedge110
.critedge122: ; preds = %.critedge122, %96 .critedge122: ; preds = %.critedge122, %96
br i1 false, label %.critedge122, label %.critedge110 br i1 false, label %.critedge122, label %.critedge110
.critedge110: ; preds = %.critedge219, %97, %.critedge122, %96 .critedge110: ; preds = %.critedge219, %97, %.critedge122, %96
ret void ret void
; <label>:97: ; preds = %8 ; <label>:97: ; preds = %8
br i1 undef, label %.critedge219, label %.critedge110 br i1 %c2, label %.critedge219, label %.critedge110
.critedge219: ; preds = %.critedge219, %97 .critedge219: ; preds = %.critedge219, %97
%.pr287 = phi i1 [ undef, %.critedge219 ], [ true, %97 ] %.pr287 = phi i1 [ undef, %.critedge219 ], [ true, %97 ]
br i1 %.pr287, label %.critedge219, label %.critedge110 br i1 %.pr287, label %.critedge219, label %.critedge110
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64) #1 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64) #1
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llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -filetype=obj -o /dev/null < %s ; RUN: llc -filetype=obj -o /dev/null < %s
; RUN: llc -filetype=asm %s -o - | FileCheck %s ; RUN: llc -filetype=asm %s -o - | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "bugpoint-output-39ed676.bc" source_filename = "bugpoint-output-39ed676.bc"
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8m.base-arm-none-eabi" target triple = "thumbv8m.base-arm-none-eabi"
@crc32_tab = external unnamed_addr global [256 x i32], align 4 @crc32_tab = external unnamed_addr global [256 x i32], align 4
@g_566 = external global ptr, align 4 @g_566 = external global ptr, align 4
define void @main() { define void @main(i1 %c0, i1 %c1) {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r0, :lower16:g_566 ; CHECK-NEXT: movw r0, :lower16:g_566
; CHECK-NEXT: movt r0, :upper16:g_566 ; CHECK-NEXT: movt r0, :upper16:g_566
; CHECK-NEXT: ldr r0, [r0] ; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: beq .LBB0_8 ; CHECK-NEXT: beq .LBB0_8
Show All 32 Lines
entry: entry:
%0 = load volatile ptr, ptr @g_566, align 4 %0 = load volatile ptr, ptr @g_566, align 4
br label %func_16.exit.i.i.i br label %func_16.exit.i.i.i
lbl_1394.i.i.i.loopexit: ; preds = %for.cond14.preheader.us.i.i.i lbl_1394.i.i.i.loopexit: ; preds = %for.cond14.preheader.us.i.i.i
unreachable unreachable
func_16.exit.i.i.i: ; preds = %entry func_16.exit.i.i.i: ; preds = %entry
br i1 undef, label %for.cond7.preheader.i.lr.ph.i.i, label %for.end476.i.i.i.loopexit br i1 %c0, label %for.cond7.preheader.i.lr.ph.i.i, label %for.end476.i.i.i.loopexit
for.cond7.preheader.i.lr.ph.i.i: ; preds = %func_16.exit.i.i.i for.cond7.preheader.i.lr.ph.i.i: ; preds = %func_16.exit.i.i.i
br i1 undef, label %for.end476.i.i.i.loopexit, label %for.cond7.preheader.i.i.preheader.i br i1 %c1, label %for.end476.i.i.i.loopexit, label %for.cond7.preheader.i.i.preheader.i
for.cond7.preheader.i.i.preheader.i: ; preds = %for.cond7.preheader.i.lr.ph.i.i for.cond7.preheader.i.i.preheader.i: ; preds = %for.cond7.preheader.i.lr.ph.i.i
br label %for.cond14.preheader.us.i.i.i br label %for.cond14.preheader.us.i.i.i
for.cond7.preheader.i.us.i.i: ; preds = %for.cond7.preheader.i.lr.ph.i.i for.cond7.preheader.i.us.i.i: ; preds = %for.cond7.preheader.i.lr.ph.i.i
unreachable unreachable
for.cond14.preheader.us.i.i.i: ; preds = %for.inc459.us.i.i.i, %for.cond7.preheader.i.i.preheader.i for.cond14.preheader.us.i.i.i: ; preds = %for.inc459.us.i.i.i, %for.cond7.preheader.i.i.preheader.i
Show All 17 Lines

llvm/test/CodeGen/ARM/vector-DAGCombine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=armv7-none-eabi | FileCheck %s ; RUN: llc < %s -mtriple=armv7-none-eabi | FileCheck %s
; PR7158 ; PR7158
define i32 @test_pr7158() nounwind { define i32 @test_pr7158(i1 %c0) nounwind {
; CHECK-LABEL: test_pr7158: ; CHECK-LABEL: test_pr7158:
; CHECK: @ %bb.0: @ %bb.nph55.bb.nph55.split_crit_edge ; CHECK: @ %bb.0: @ %bb.nph55.bb.nph55.split_crit_edge
; CHECK-NEXT: .LBB0_1: @ %bb.i19 ; CHECK-NEXT: .LBB0_1: @ %bb.i19
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: b .LBB0_1 ; CHECK-NEXT: b .LBB0_1
bb.nph55.bb.nph55.split_crit_edge: bb.nph55.bb.nph55.split_crit_edge:
br label %bb3 br label %bb3
bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
br i1 undef, label %bb.i19, label %bb3 br i1 %c0, label %bb.i19, label %bb3
bb.i19: ; preds = %bb.i19, %bb3 bb.i19: ; preds = %bb.i19, %bb3
%0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3]
%1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1]
%2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0]
%3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0]
br label %bb.i19 br label %bb.i19
} }
Show All 18 Lines
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
%1 = fptoui <16 x float> undef to <16 x i8> %1 = fptoui <16 x float> undef to <16 x i8>
store <16 x i8> %1, ptr undef store <16 x i8> %1, ptr undef
ret void ret void
} }
; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
; converted back to be used as a vector type. ; converted back to be used as a vector type.
define <4 x i32> @test_vmovrrd_combine() nounwind { define <4 x i32> @test_vmovrrd_combine(i1 %c0, i1 %c1) nounwind {
; CHECK-LABEL: test_vmovrrd_combine: ; CHECK-LABEL: test_vmovrrd_combine:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: @ implicit-def: $q8 ; CHECK-NEXT: @ implicit-def: $q8
; CHECK-NEXT: bne .LBB3_2 ; CHECK-NEXT: bne .LBB3_2
; CHECK-NEXT: @ %bb.1: @ %bb1.preheader ; CHECK-NEXT: @ %bb.1: @ %bb1.preheader
; CHECK-NEXT: vmov.i32 q8, #0x0 ; CHECK-NEXT: vmov.i32 q8, #0x0
; CHECK-NEXT: .LBB3_2: @ %bb2 ; CHECK-NEXT: .LBB3_2: @ %bb2
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
br i1 undef, label %bb1, label %bb2 br i1 %c0, label %bb1, label %bb2
bb1: bb1:
%0 = bitcast <2 x i64> zeroinitializer to <2 x double> %0 = bitcast <2 x i64> zeroinitializer to <2 x double>
%1 = extractelement <2 x double> %0, i32 0 %1 = extractelement <2 x double> %0, i32 0
%2 = bitcast double %1 to i64 %2 = bitcast double %1 to i64
%3 = insertelement <1 x i64> undef, i64 %2, i32 0 %3 = insertelement <1 x i64> undef, i64 %2, i32 0
%4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1> %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8> %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8>
%5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19> %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
%tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32> %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32>
br i1 undef, label %bb2, label %bb1 br i1 %c1, label %bb2, label %bb1
bb2: bb2:
%result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ] %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ]
ret <4 x i32> %result ret <4 x i32> %result
} }
; Test trying to do a ShiftCombine on illegal types. ; Test trying to do a ShiftCombine on illegal types.
; The vector should be split first. ; The vector should be split first.
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llvm/test/CodeGen/ARM/vmul.ll

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%1 = sext <8 x i8> %vec to <8 x i16> %1 = sext <8 x i8> %vec to <8 x i16>
%2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%3 = extractelement <8 x i16> %2, i32 0 %3 = extractelement <8 x i16> %2, i32 0
ret i16 %3 ret i16 %3
} }
; A constant build_vector created for a vmull with half-width elements must ; A constant build_vector created for a vmull with half-width elements must
; not introduce illegal types. <rdar://problem/11324364> ; not introduce illegal types. <rdar://problem/11324364>
define void @vmull_buildvector() nounwind optsize ssp align 2 { define void @vmull_buildvector(i1 %c0, i1 %c1, i1 %c2, i1 %c3) nounwind optsize ssp align 2 {
; CHECK-LABEL: vmull_buildvector: ; CHECK-LABEL: vmull_buildvector:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
entry: entry:
br i1 undef, label %for.end179, label %for.body.lr.ph br i1 %c0, label %for.end179, label %for.body.lr.ph
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
br label %for.body br label %for.body
for.cond.loopexit: ; preds = %for.body33, %for.body for.cond.loopexit: ; preds = %for.body33, %for.body
br i1 undef, label %for.end179, label %for.body br i1 %c1, label %for.end179, label %for.body
for.body: ; preds = %for.cond.loopexit, %for.body.lr.ph for.body: ; preds = %for.cond.loopexit, %for.body.lr.ph
br i1 undef, label %for.cond.loopexit, label %for.body33.lr.ph br i1 %c2, label %for.cond.loopexit, label %for.body33.lr.ph
for.body33.lr.ph: ; preds = %for.body for.body33.lr.ph: ; preds = %for.body
%.sub = select i1 undef, i32 0, i32 undef %.sub = select i1 undef, i32 0, i32 undef
br label %for.body33 br label %for.body33
for.body33: ; preds = %for.body33, %for.body33.lr.ph for.body33: ; preds = %for.body33, %for.body33.lr.ph
%add45 = add i32 undef, undef %add45 = add i32 undef, undef
%vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr undef, i32 1) %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr undef, i32 1)
Show All 33 Linesfor.body33: ; preds = %for.body33, %for.body33.lr.ph
%add.i182 = add <8 x i16> %mul.i181, %mul.i184 %add.i182 = add <8 x i16> %mul.i181, %mul.i184
%vrshr_n170 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i182, <8 x i16> <i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7>) %vrshr_n170 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i182, <8 x i16> <i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7>)
%vqmovn1.i180 = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %vrshr_n170) nounwind %vqmovn1.i180 = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %vrshr_n170) nounwind
%4 = bitcast <8 x i8> %vqmovn1.i180 to <1 x i64> %4 = bitcast <8 x i8> %vqmovn1.i180 to <1 x i64>
%shuffle.i = shufflevector <1 x i64> %4, <1 x i64> undef, <2 x i32> <i32 0, i32 1> %shuffle.i = shufflevector <1 x i64> %4, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%5 = bitcast <2 x i64> %shuffle.i to <16 x i8> %5 = bitcast <2 x i64> %shuffle.i to <16 x i8>
store <16 x i8> %5, ptr undef, align 16 store <16 x i8> %5, ptr undef, align 16
%add177 = add nsw i32 undef, 16 %add177 = add nsw i32 undef, 16
br i1 undef, label %for.body33, label %for.cond.loopexit br i1 %c3, label %for.body33, label %for.cond.loopexit
for.end179: ; preds = %for.cond.loopexit, %entry for.end179: ; preds = %for.cond.loopexit, %entry
ret void ret void
} }
declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
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llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll

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; ;
; See PR13375 for details. ; See PR13375 for details.
%values = type { i16, [2 x i8], [40 x i32], [0 x i8] } %values = type { i16, [2 x i8], [40 x i32], [0 x i8] }
@POW10TO128 = external constant [14 x i32], align 4 @POW10TO128 = external constant [14 x i32], align 4
; CHECK: core_num_flt2dec_strategy_dragon ; CHECK: core_num_flt2dec_strategy_dragon
define nonnull dereferenceable(164) %values* @core_num_flt2dec_strategy_dragon(%values* returned dereferenceable(164) %arg, i16 %arg1) unnamed_addr { define nonnull dereferenceable(164) %values* @core_num_flt2dec_strategy_dragon(%values* returned dereferenceable(164) %arg, i16 %arg1, i1 %c0) unnamed_addr {
start: start:
%ret.i = alloca [40 x i32], align 4 %ret.i = alloca [40 x i32], align 4
%tmp = icmp eq i16 undef, 0 %tmp = icmp eq i16 undef, 0
br i1 %tmp, label %bb5, label %bb1 br i1 %tmp, label %bb5, label %bb1
bb1: bb1:
unreachable unreachable
bb5: bb5:
br i1 undef, label %bb14, label %bb11 br i1 %c0, label %bb14, label %bb11
bb11: bb11:
unreachable unreachable
bb14: bb14:
%tmp2 = bitcast [40 x i32]* %ret.i to i8* %tmp2 = bitcast [40 x i32]* %ret.i to i8*
call void @llvm.memset.p0i8.i16(i8* align 4 %tmp2, i8 0, i16 160, i1 false) call void @llvm.memset.p0i8.i16(i8* align 4 %tmp2, i8 0, i16 160, i1 false)
%tmp3 = getelementptr inbounds %values, %values* %arg, i16 0, i32 0 %tmp3 = getelementptr inbounds %values, %values* %arg, i16 0, i32 0
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llvm/test/CodeGen/AVR/pre-schedule.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
target triple = "avr-unknown-unknown" target triple = "avr-unknown-unknown"
; The case illustrate DAG schedular may pre-schedule the node has ; The case illustrate DAG schedular may pre-schedule the node has
; ADJCALLSTACKDOWN parent, so ADJCALLSTACKUP may hold CallResource too long ; ADJCALLSTACKDOWN parent, so ADJCALLSTACKUP may hold CallResource too long
; and make other calls can't be scheduled. If there's no other available node ; and make other calls can't be scheduled. If there's no other available node
; to schedule, the scheduler will try to rename the register by creating the ; to schedule, the scheduler will try to rename the register by creating the
; copy to avoid the conflict which will fail because CallResource is not a real ; copy to avoid the conflict which will fail because CallResource is not a real
; physical register. ; physical register.
; ;
; The issue is found by Tim on https://github.com/avr-rust/rust/issues/111 and ; The issue is found by Tim on https://github.com/avr-rust/rust/issues/111 and
; discuss in http://lists.llvm.org/pipermail/llvm-dev/2018-October/127083.html. ; discuss in http://lists.llvm.org/pipermail/llvm-dev/2018-October/127083.html.
define void @"main"() addrspace(1) { define void @"main"() addrspace(1, i1 %c0) {
start: start:
%0 = or i64 undef, undef %0 = or i64 undef, undef
br i1 undef, label %mul_and_call, label %fail br i1 %c0, label %mul_and_call, label %fail
mul_and_call: mul_and_call:
%1 = mul i64 %0, %0 %1 = mul i64 %0, %0
call addrspace(1) void @"three_ints"(i64 undef, i64 %1, i64 %0) call addrspace(1) void @"three_ints"(i64 undef, i64 %1, i64 %0)
; The CHECK line only want to make sure the following assertion message ; The CHECK line only want to make sure the following assertion message
; won't trigger due to create copy of artificial CallResource register. ; won't trigger due to create copy of artificial CallResource register.
; llc: llvm/lib/CodeGen/TargetRegisterInfo.cpp:203: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::MVT) const: Assertion `BestRC && "Couldn't find the register class"' failed. ; llc: llvm/lib/CodeGen/TargetRegisterInfo.cpp:203: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::MVT) const: Assertion `BestRC && "Couldn't find the register class"' failed.
; CHECK: call __muldi3 ; CHECK: call __muldi3
ret void ret void
fail: fail:
ret void ret void
} }
declare void @"three_ints"(i64, i64, i64) addrspace(1) declare void @"three_ints"(i64, i64, i64) addrspace(1)

llvm/test/CodeGen/AVR/rust-avr-bug-112.ll

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; Assertion failed: ((isImpReg || Op.isRegMask() || MCID->isVariadic() || ; Assertion failed: ((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
; OpNo < MCID->getNumOperands() || isMetaDataOp) && ; OpNo < MCID->getNumOperands() || isMetaDataOp) &&
; "Trying to add an operand to a machine instr that is already done!"), ; "Trying to add an operand to a machine instr that is already done!"),
; function addOperand, file llvm/lib/CodeGen/MachineInstr.cpp ; function addOperand, file llvm/lib/CodeGen/MachineInstr.cpp
; ;
; The logic has since been fixed. ; The logic has since been fixed.
; CHECK-LABEL: "core::str::slice_error_fail" ; CHECK-LABEL: "core::str::slice_error_fail"
define void @"core::str::slice_error_fail"(i16 %arg) personality i32 (...) addrspace(1)* @rust_eh_personality { define void @"core::str::slice_error_fail"(i16 %arg) personality i32 (...) addrspace(1, i1 %c0)* @rust_eh_personality {
start: start:
%char_range = alloca { i16, i16 }, align 1 %char_range = alloca { i16, i16 }, align 1
br i1 undef, label %"<core::option::Option<T>>::unwrap.exit.thread", label %bb11.i.i br i1 %c0, label %"<core::option::Option<T>>::unwrap.exit.thread", label %bb11.i.i
"<core::option::Option<T>>::unwrap.exit.thread": "<core::option::Option<T>>::unwrap.exit.thread":
br label %"core::char::methods::<impl char>::len_utf8.exit" br label %"core::char::methods::<impl char>::len_utf8.exit"
bb11.i.i: bb11.i.i:
%tmp = bitcast { i16, i16 }* %char_range to i8* %tmp = bitcast { i16, i16 }* %char_range to i8*
%tmp1 = icmp ult i32 undef, 65536 %tmp1 = icmp ult i32 undef, 65536
%..i = select i1 %tmp1, i16 3, i16 4 %..i = select i1 %tmp1, i16 3, i16 4
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llvm/test/CodeGen/AVR/rust-avr-bug-99.ll

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%struct.quux.1 = type { [0 x i8], %struct.wombat, [0 x i8], i64, [0 x i8], i64, [0 x i8], i16, [0 x i8], %struct.quux, [0 x i8], i64, [0 x i8], i16, [0 x i8] } %struct.quux.1 = type { [0 x i8], %struct.wombat, [0 x i8], i64, [0 x i8], i64, [0 x i8], i16, [0 x i8], %struct.quux, [0 x i8], i64, [0 x i8], i16, [0 x i8] }
%struct.wombat = type {} %struct.wombat = type {}
declare zeroext i1 @zot(%struct.quux*, %struct.foo*) declare zeroext i1 @zot(%struct.quux*, %struct.foo*)
declare void @wibble(i16, i16) declare void @wibble(i16, i16)
; CHECK-LABEL: main ; CHECK-LABEL: main
define zeroext i1 @main(%struct.quux.1* %arg, %struct.foo* %arg62) { define zeroext i1 @main(%struct.quux.1* %arg, %struct.foo* %arg62, i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) {
bb: bb:
%tmp63 = alloca [128 x i8], align 1 %tmp63 = alloca [128 x i8], align 1
%tmp = getelementptr inbounds %struct.quux.1, %struct.quux.1* %arg, i16 0, i32 5 %tmp = getelementptr inbounds %struct.quux.1, %struct.quux.1* %arg, i16 0, i32 5
%tmp64 = getelementptr inbounds %struct.quux.1, %struct.quux.1* %arg, i16 0, i32 13 %tmp64 = getelementptr inbounds %struct.quux.1, %struct.quux.1* %arg, i16 0, i32 13
%tmp65 = bitcast %struct.foo* %arg62 to i32* %tmp65 = bitcast %struct.foo* %arg62 to i32*
%tmp66 = icmp eq i32 undef, 0 %tmp66 = icmp eq i32 undef, 0
br i1 undef, label %bb92, label %bb67 br i1 %c0, label %bb92, label %bb67
bb67: bb67:
br i1 %tmp66, label %bb83, label %bb68 br i1 %tmp66, label %bb83, label %bb68
bb68: bb68:
%tmp69 = load i64, i64* null, align 1 %tmp69 = load i64, i64* null, align 1
br label %bb70 br label %bb70
Show All 32 Linesbb88:
%tmp90 = udiv i64 %tmp89, 10000 %tmp90 = udiv i64 %tmp89, 10000
%tmp91 = icmp ugt i64 %tmp89, 99999999 %tmp91 = icmp ugt i64 %tmp89, 99999999
br label %bb88 br label %bb88
bb92: bb92:
br label %bb93 br label %bb93
bb93: bb93:
br i1 undef, label %bb95, label %bb94 br i1 %c1, label %bb95, label %bb94
bb94: bb94:
unreachable unreachable
bb95: bb95:
br label %bb96 br label %bb96
bb96: bb96:
%tmp97 = phi i64 [ %tmp98, %bb96 ], [ undef, %bb95 ] %tmp97 = phi i64 [ %tmp98, %bb96 ], [ undef, %bb95 ]
%tmp98 = udiv i64 %tmp97, 10000 %tmp98 = udiv i64 %tmp97, 10000
%tmp99 = icmp ugt i64 %tmp97, 99999999 %tmp99 = icmp ugt i64 %tmp97, 99999999
br i1 %tmp99, label %bb96, label %bb100 br i1 %tmp99, label %bb96, label %bb100
bb100: bb100:
br label %bb101 br label %bb101
bb101: bb101:
%tmp102 = and i32 undef, 16 %tmp102 = and i32 undef, 16
%tmp103 = icmp eq i32 %tmp102, 0 %tmp103 = icmp eq i32 %tmp102, 0
br i1 undef, label %bb130, label %bb104 br i1 %c2, label %bb130, label %bb104
bb104: bb104:
br i1 %tmp103, label %bb117, label %bb105 br i1 %tmp103, label %bb117, label %bb105
bb105: bb105:
br label %bb106 br label %bb106
bb106: bb106:
Show All 9 Linesbb106:
br i1 %tmp115, label %bb116, label %bb106 br i1 %tmp115, label %bb116, label %bb106
bb116: bb116:
call void @wibble(i16 %tmp113, i16 128) call void @wibble(i16 %tmp113, i16 128)
unreachable unreachable
bb117: bb117:
%tmp118 = load i64, i64* %tmp, align 1 %tmp118 = load i64, i64* %tmp, align 1
br i1 undef, label %bb120, label %bb119 br i1 %c3, label %bb120, label %bb119
bb119: bb119:
unreachable unreachable
bb120: bb120:
%tmp121 = icmp ugt i64 %tmp118, 9999 %tmp121 = icmp ugt i64 %tmp118, 9999
br i1 %tmp121, label %bb122, label %bb127 br i1 %tmp121, label %bb122, label %bb127
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bb168: bb168:
br label %bb168 br label %bb168
bb169: bb169:
br label %bb170 br label %bb170
bb170: bb170:
br i1 undef, label %bb172, label %bb171 br i1 %c4, label %bb172, label %bb171
bb171: bb171:
store i32 0, i32* undef, align 1 store i32 0, i32* undef, align 1
call void @llvm.memcpy.p0i8.p0i8.i16(i8* align 1 undef, i8* align 1 null, i16 3, i1 false) call void @llvm.memcpy.p0i8.p0i8.i16(i8* align 1 undef, i8* align 1 null, i16 3, i1 false)
call void @llvm.memcpy.p0i8.p0i8.i16(i8* align 1 undef, i8* align 1 null, i16 3, i1 false) call void @llvm.memcpy.p0i8.p0i8.i16(i8* align 1 undef, i8* align 1 null, i16 3, i1 false)
br label %bb214 br label %bb214
bb172: bb172:
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%tmp199 = or i1 %tmp198, undef %tmp199 = or i1 %tmp198, undef
br i1 %tmp199, label %bb200, label %bb194 br i1 %tmp199, label %bb200, label %bb194
bb200: bb200:
call void @wibble(i16 %tmp197, i16 128) call void @wibble(i16 %tmp197, i16 128)
unreachable unreachable
bb201: bb201:
br i1 undef, label %bb202, label %bb207 br i1 %c5, label %bb202, label %bb207
bb202: bb202:
br label %bb203 br label %bb203
bb203: bb203:
%tmp204 = phi i64 [ %tmp205, %bb203 ], [ 0, %bb202 ] %tmp204 = phi i64 [ %tmp205, %bb203 ], [ 0, %bb202 ]
%tmp205 = udiv i64 %tmp204, 10000 %tmp205 = udiv i64 %tmp204, 10000
%tmp206 = icmp ugt i64 %tmp204, 99999999 %tmp206 = icmp ugt i64 %tmp204, 99999999
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bb215: bb215:
br i1 %tmp212, label %bb220, label %bb216 br i1 %tmp212, label %bb220, label %bb216
bb216: bb216:
br label %bb217 br label %bb217
bb217: bb217:
br i1 undef, label %bb218, label %bb219 br i1 %c6, label %bb218, label %bb219
bb218: bb218:
unreachable unreachable
bb219: bb219:
br label %bb221 br label %bb221
bb220: bb220:
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