This is an archive of the discontinued LLVM Phabricator instance.

Differential D145334

[InstCombine] Add tests for transform `(shift X,(Or Y, BitWidth-1))`; NFC
ClosedPublic

Authored by goldstein.w.n on Mar 5 2023, 2:40 PM.

Details

Reviewers
spatel
nikic
majnemer
Commits
rG9bb409ff1d0c: [InstCombine] Add tests for transform `(shift X,(Or Y, BitWidth-1))`; NFC

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,060 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test
60,050 msx64 debian > libFuzzer.libFuzzer::value-profile-load.test

Event Timeline

goldstein.w.n created this revision.Mar 5 2023, 2:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 5 2023, 2:40 PM
goldstein.w.n requested review of this revision.Mar 5 2023, 2:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 5 2023, 2:40 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
goldstein.w.n added reviewers: spatel, nikic, majnemer.Mar 5 2023, 2:42 PM
Herald added a subscriber: StephenFan. · View Herald TranscriptMar 5 2023, 2:42 PM
goldstein.w.n added a child revision: D145326: [InstCombine] Transform `(shift X,Or(Y,BitWidth-1))` -> `(shift X,BitWidth-1)`.Mar 5 2023, 2:42 PM
Harbormaster completed remote builds in B217459: Diff 502478.Mar 5 2023, 3:29 PM
Mztea928 added a child revision: D145351: [cmake] Export component info needed to determine which libraries are in libLLVM.so..Mar 5 2023, 10:16 PM
nikic accepted this revision.Mar 6 2023, 1:33 AM

LG

llvm/test/Transforms/InstCombine/shift.ll
2079

propagate

This revision is now accepted and ready to land.Mar 6 2023, 1:33 AM
goldstein.w.n removed a child revision: D145351: [cmake] Export component info needed to determine which libraries are in libLLVM.so..Mar 6 2023, 10:24 AM
goldstein.w.n marked an inline comment as done.Mar 6 2023, 10:32 AM
goldstein.w.n updated this revision to Diff 502706.Mar 6 2023, 10:32 AM

Fix misspell

Harbormaster completed remote builds in B217626: Diff 502706.Mar 6 2023, 1:51 PM
Closed by commit rG9bb409ff1d0c: [InstCombine] Add tests for transform `(shift X,(Or Y, BitWidth-1))`; NFC (authored by goldstein.w.n). · Explain WhyMar 6 2023, 6:31 PM
This revision was automatically updated to reflect the committed changes.
goldstein.w.n added a commit: rG9bb409ff1d0c: [InstCombine] Add tests for transform `(shift X,(Or Y, BitWidth-1))`; NFC.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
48 lines

Diff 502478

llvm/test/Transforms/InstCombine/shift.ll

Show First 20 Lines • Show All 2,061 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] ; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, [[TZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, [[TZ]]
; CHECK-NEXT: ret i32 [[SHL]] ; CHECK-NEXT: ret i32 [[SHL]]
; ;
%tz = call i32 @llvm.cttz.i32(i32 %x, i1 true) %tz = call i32 @llvm.cttz.i32(i32 %x, i1 true)
%shl = shl i32 2, %tz %shl = shl i32 2, %tz
ret i32 %shl ret i32 %shl
} }
; shift (X, amt | bitwidth - 1) -> shift (X, bitwidth - 1)
define i6 @shl_or7_eq_shl7(i6 %x, i6 %c) {
; CHECK-LABEL: @shl_or7_eq_shl7(
; CHECK-NEXT: [[AMT:%.*]] = or i6 [[C:%.*]], 5
; CHECK-NEXT: [[Y:%.*]] = shl nsw i6 [[X:%.*]], [[AMT]]
; CHECK-NEXT: ret i6 [[Y]]
;
%amt = or i6 %c, 5
;; nsw not needed for transform, just check that we propegate.
nikicUnsubmitted
Done
ReplyInline Actions

propagate

nikic: propagate
%y = shl nsw i6 %x, %amt
ret i6 %y
}
define <2 x i8> @lshr_vec_or7_eq_shl7(<2 x i8> %x, <2 x i8> %c) {
; CHECK-LABEL: @lshr_vec_or7_eq_shl7(
; CHECK-NEXT: [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
; CHECK-NEXT: [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], [[AMT]]
; CHECK-NEXT: ret <2 x i8> [[Y]]
;
%amt = or <2 x i8> %c, <i8 7, i8 7>
;; exact not needed for transform, just check that we propegate.
%y = lshr exact <2 x i8> %x, %amt
ret <2 x i8> %y
}
define <2 x i8> @ashr_vec_or7_eq_ashr7(<2 x i8> %x, <2 x i8> %c) {
; CHECK-LABEL: @ashr_vec_or7_eq_ashr7(
; CHECK-NEXT: [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
; CHECK-NEXT: [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]]
; CHECK-NEXT: ret <2 x i8> [[Y]]
;
%amt = or <2 x i8> %c, <i8 7, i8 7>
%y = ashr <2 x i8> %x, %amt
ret <2 x i8> %y
}
; Negative test not bitwidth - 1
define <2 x i8> @ashr_vec_or6_fail(<2 x i8> %x, <2 x i8> %c) {
; CHECK-LABEL: @ashr_vec_or6_fail(
; CHECK-NEXT: [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 6, i8 6>
; CHECK-NEXT: [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]]
; CHECK-NEXT: ret <2 x i8> [[Y]]
;
%amt = or <2 x i8> %c, <i8 6, i8 6>
%y = ashr <2 x i8> %x, %amt
ret <2 x i8> %y
}