[X86] Add tests for replacing `{v}permilps` -> `{v}shufps/{v}pshufd`; NFC

[RKSimon]

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll

3

CHECK-AV? Maybe CHECK-AVX and CHECK-AVX1 ?

[goldstein.w.n]

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

Also would you prefer the same for the unpckpd tests (added masked versions for them as well).

[goldstein.w.n]

CHECK-AV -> CHECK-AVX

[RKSimon]

In D144779#4152876, @goldstein.w.n wrote:

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

The 512-bit and masked predicate cases - I'm also concerned whether the Z128/Z256 cases are being correctly tested or the evex-vec pass has already converted them to the regular xmm/ymm variants

[RKSimon]

In D144779#4153376, @RKSimon wrote:

In D144779#4152876, @goldstein.w.n wrote:

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

The 512-bit and masked predicate cases - I'm also concerned whether the Z128/Z256 cases are being correctly tested or the evex-vec pass has already converted them to the regular xmm/ymm variants

The tuning pass is before evex-vex so we should be OK - it might be worth adding to the avx512 file a single additional RUN for "-mcpu=x86-86-v4 --show-mc-encoding" that greps that we have no "EVEX TO VEX Compression" strings

[goldstein.w.n]

In D144779#4153399, @RKSimon wrote:

In D144779#4153376, @RKSimon wrote:

In D144779#4152876, @goldstein.w.n wrote:

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

The 512-bit and masked predicate cases - I'm also concerned whether the Z128/Z256 cases are being correctly tested or the evex-vec pass has already converted them to the regular xmm/ymm variants

The tuning pass is before evex-vex so we should be OK - it might be worth adding to the avx512 file a single additional RUN for "-mcpu=x86-86-v4 --show-mc-encoding" that greps that we have no "EVEX TO VEX Compression" strings

How do I add check-not for a grep? Any example test you can point me at?
Figures it out although it's in output.

[goldstein.w.n]

In D144779#4153399, @RKSimon wrote:

In D144779#4153376, @RKSimon wrote:

In D144779#4152876, @goldstein.w.n wrote:

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

The 512-bit and masked predicate cases - I'm also concerned whether the Z128/Z256 cases are being correctly tested or the evex-vec pass has already converted them to the regular xmm/ymm variants

The tuning pass is before evex-vex so we should be OK - it might be worth adding to the avx512 file a single additional RUN for "-mcpu=x86-86-v4 --show-mc-encoding" that greps that we have no "EVEX TO VEX Compression" strings

I don't think this works. Even if x86fixupinsttuning runs first, even to vex compression will eventually run and be in the output.

[RKSimon]

In D144779#4153866, @goldstein.w.n wrote:

In D144779#4153399, @RKSimon wrote:

In D144779#4153376, @RKSimon wrote:

In D144779#4152876, @goldstein.w.n wrote:

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

The 512-bit and masked predicate cases - I'm also concerned whether the Z128/Z256 cases are being correctly tested or the evex-vec pass has already converted them to the regular xmm/ymm variants

The tuning pass is before evex-vex so we should be OK - it might be worth adding to the avx512 file a single additional RUN for "-mcpu=x86-86-v4 --show-mc-encoding" that greps that we have no "EVEX TO VEX Compression" strings

I don't think this works. Even if x86fixupinsttuning runs first, even to vex compression will eventually run and be in the output.

What about -stop-before=x86-evex-to-vex-compress ? (Sorry I haven't used this much before)

[goldstein.w.n]

In D144779#4153888, @RKSimon wrote:

In D144779#4153866, @goldstein.w.n wrote:

In D144779#4153399, @RKSimon wrote:

In D144779#4153376, @RKSimon wrote:

In D144779#4152876, @goldstein.w.n wrote:

In D144779#4152616, @RKSimon wrote:

You might be better off splitting this into tuning-shuffle-permilps.ll (although keep AVX512 test coverage here as well) and tuning-shuffle-permilps-avx512.ll

What do you mean? As in move the masked-predicate versions to a seperate test file and keep avx512 targets? Or something else?

The 512-bit and masked predicate cases - I'm also concerned whether the Z128/Z256 cases are being correctly tested or the evex-vec pass has already converted them to the regular xmm/ymm variants

The tuning pass is before evex-vex so we should be OK - it might be worth adding to the avx512 file a single additional RUN for "-mcpu=x86-86-v4 --show-mc-encoding" that greps that we have no "EVEX TO VEX Compression" strings

I don't think this works. Even if x86fixupinsttuning runs first, even to vex compression will eventually run and be in the output.

What about -stop-before=x86-evex-to-vex-compress ? (Sorry I haven't used this much before)

In D143787 we assert the order of passes in llvm/test/CodeGen/X86/opt-pipeline.ll and we have:

...
; CHECK-NEXT:       X86 Fixup Inst Tuning
; CHECK-NEXT:       Compressing EVEX instrs to VEX encoding when possible
...

So that should be sufficient for ordering no?

[goldstein.w.n]

Split avx/avx512 tests

[RKSimon]

llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll

5

Add a CHECK-AVX1-DELAY variant as well

15

Remove the VPERMILPSZ 512-bit cases - they are handled in the -avx512 file

[goldstein.w.n]

Add AVX1 + DELAY and remove avx512 tests for avx file

[RKSimon]

LGTM

[goldstein.w.n]

Rebase (after D144832, no dep on D143786)

llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server  | FileCheck %s --check-prefixes=CHECK,CHECK-ICX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4  | FileCheck %s --check-prefixes=CHECK,CHECK-V4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq  | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4  | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4
+
+define <16 x float> @transform_VPERMILPSZrr(<16 x float> %a) nounwind {
+; CHECK-LABEL: transform_VPERMILPSZrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} zmm0 = zmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  ret <16 x float> %shufp
+}
+
+define <8 x float> @transform_VPERMILPSYrr(<8 x float> %a) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x float> %shufp
+}
+
+define <4 x float> @transform_VPERMILPSrr(<4 x float> %a) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x float> %shufp
+}
+
+define <16 x float> @transform_VPERMILPSZrrkz(<16 x float> %a, i16 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSZrrkz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %edi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} zmm0 {%k1} {z} = zmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-NEXT:    retq
+  %mask = bitcast i16 %mask_int to <16 x i1>
+  %shufp = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> zeroinitializer
+  ret <16 x float> %res
+}
+
+define <8 x float> @transform_VPERMILPSYrrkz(<8 x float> %a, i8 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrrkz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %edi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 {%k1} {z} = ymm0[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %mask = bitcast i8 %mask_int to <8 x i1>
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> zeroinitializer
+  ret <8 x float> %res
+}
+
+define <4 x float> @transform_VPERMILPSrrkz(<4 x float> %a, i4 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrrkz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %edi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 {%k1} {z} = xmm0[3,2,1,0]
+; CHECK-NEXT:    retq
+  %mask = bitcast i4 %mask_int to <4 x i1>
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> zeroinitializer
+  ret <4 x float> %res
+}
+
+define <16 x float> @transform_VPERMILPSZrrk(<16 x float> %a, <16 x float> %b, i16 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSZrrk:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %edi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} zmm1 {%k1} = zmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-NEXT:    vmovaps %zmm1, %zmm0
+; CHECK-NEXT:    retq
+  %mask = bitcast i16 %mask_int to <16 x i1>
+  %shufp = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> %b
+  ret <16 x float> %res
+}
+
+define <8 x float> @transform_VPERMILPSYrrk(<8 x float> %a, <8 x float> %b, i8 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrrk:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %edi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm1 {%k1} = ymm0[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    vmovaps %ymm1, %ymm0
+; CHECK-NEXT:    retq
+  %mask = bitcast i8 %mask_int to <8 x i1>
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> %b
+  ret <8 x float> %res
+}
+
+define <4 x float> @transform_VPERMILPSrrk(<4 x float> %a, <4 x float> %b, i4 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrrk:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %edi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm1 {%k1} = xmm0[3,2,1,0]
+; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %mask = bitcast i4 %mask_int to <4 x i1>
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> %b
+  ret <4 x float> %res
+}
+
+define <16 x float> @transform_VPERMILPSZrm(ptr %ap) nounwind {
+; CHECK-LABEL: transform_VPERMILPSZrm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} zmm0 = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-NEXT:    retq
+  %a = load <16 x float>, ptr %ap
+  %shufp = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  ret <16 x float> %shufp
+}
+
+define <8 x float> @transform_VPERMILPSYrm(ptr %ap) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 = mem[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %a = load <8 x float>, ptr %ap
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x float> %shufp
+}
+
+define <4 x float> @transform_VPERMILPSrm(ptr %ap) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = mem[3,2,1,0]
+; CHECK-NEXT:    retq
+  %a = load <4 x float>, ptr %ap
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x float> %shufp
+}
+
+define <16 x float> @transform_VPERMILPSZrmkz(ptr %ap, i16 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSZrmkz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %esi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} zmm0 {%k1} {z} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-NEXT:    retq
+  %mask = bitcast i16 %mask_int to <16 x i1>
+  %a = load <16 x float>, ptr %ap
+  %shufp = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> zeroinitializer
+  ret <16 x float> %res
+}
+
+define <8 x float> @transform_VPERMILPSYrmkz(ptr %ap, i8 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrmkz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %esi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 {%k1} {z} = mem[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %mask = bitcast i8 %mask_int to <8 x i1>
+  %a = load <8 x float>, ptr %ap
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> zeroinitializer
+  ret <8 x float> %res
+}
+
+define <4 x float> @transform_VPERMILPSrmkz(ptr %ap, i4 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrmkz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %esi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 {%k1} {z} = mem[3,2,1,0]
+; CHECK-NEXT:    retq
+  %mask = bitcast i4 %mask_int to <4 x i1>
+  %a = load <4 x float>, ptr %ap
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> zeroinitializer
+  ret <4 x float> %res
+}
+
+define <16 x float> @transform_VPERMILPSZrmk(ptr %ap, <16 x float> %b, i16 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSZrmk:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %esi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} zmm0 {%k1} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
+; CHECK-NEXT:    retq
+  %mask = bitcast i16 %mask_int to <16 x i1>
+  %a = load <16 x float>, ptr %ap
+  %shufp = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> %b
+  ret <16 x float> %res
+}
+
+define <8 x float> @transform_VPERMILPSYrmk(ptr %ap, <8 x float> %b, i8 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrmk:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %esi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 {%k1} = mem[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %mask = bitcast i8 %mask_int to <8 x i1>
+  %a = load <8 x float>, ptr %ap
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> %b
+  ret <8 x float> %res
+}
+
+define <4 x float> @transform_VPERMILPSrmk(ptr %ap, <4 x float> %b, i4 %mask_int) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrmk:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    kmovd %esi, %k1
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 {%k1} = mem[3,2,1,0]
+; CHECK-NEXT:    retq
+  %mask = bitcast i4 %mask_int to <4 x i1>
+  %a = load <4 x float>, ptr %ap
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> %b
+  ret <4 x float> %res
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-AVX512: {{.*}}
+; CHECK-ICX: {{.*}}
+; CHECK-V4: {{.*}}
+; CHECK-ZNVER4: {{.*}}

llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx,+no-bypass-delay-shuffle  | FileCheck %s --check-prefixes=CHECK,CHECK-AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx  | FileCheck %s --check-prefixes=CHECK,CHECK-AVX1-DELAY
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx2,+no-bypass-delay-shuffle  | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx2  | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2-DELAY
+
+define <8 x float> @transform_VPERMILPSYrr(<8 x float> %a) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x float> %shufp
+}
+
+define <4 x float> @transform_VPERMILPSrr(<4 x float> %a) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x float> %shufp
+}
+
+define <8 x float> @transform_VPERMILPSYrm(ptr %ap) nounwind {
+; CHECK-LABEL: transform_VPERMILPSYrm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} ymm0 = mem[3,2,1,0,7,6,5,4]
+; CHECK-NEXT:    retq
+  %a = load <8 x float>, ptr %ap
+  %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x float> %shufp
+}
+
+define <4 x float> @transform_VPERMILPSrm(ptr %ap) nounwind {
+; CHECK-LABEL: transform_VPERMILPSrm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = mem[3,2,1,0]
+; CHECK-NEXT:    retq
+  %a = load <4 x float>, ptr %ap
+  %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x float> %shufp
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-AVX1: {{.*}}
+; CHECK-AVX1-DELAY: {{.*}}
+; CHECK-AVX2: {{.*}}
+; CHECK-AVX2-DELAY: {{.*}}