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Differential D143788

[X86] Add more tests for promoting `blendw` -> `blendd`; NFC
ClosedPublic

Authored by goldstein.w.n on Feb 10 2023, 3:32 PM.

Details

Reviewers
pengfei
RKSimon
Commits
rG7ae071f98186: Add more tests for promoting `blendw` -> `blendd`; NFC

Diff Detail

Event Timeline

goldstein.w.n created this revision.Feb 10 2023, 3:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2023, 3:32 PM
Herald added a subscriber: pengfei. · View Herald Transcript
goldstein.w.n requested review of this revision.Feb 10 2023, 3:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2023, 3:32 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
goldstein.w.n added a parent revision: D143787: [X86] Add new pass `X86FixupInstTuning` for fixing up machine-instruction selection..Feb 10 2023, 3:33 PM
goldstein.w.n added a child revision: D143789: [X86] Widen i16 shuffle masks if vector width < 512 even with BWI.
goldstein.w.n added reviewers: pengfei, RKSimon.
Harbormaster completed remote builds in B213163: Diff 496617.Feb 10 2023, 4:26 PM
goldstein.w.n updated this revision to Diff 496798.Feb 12 2023, 2:15 PM

Move logic to cancombinemask

Harbormaster completed remote builds in B213308: Diff 496798.Feb 12 2023, 2:18 PM
RKSimon accepted this revision.Feb 13 2023, 6:46 AM

LGTM with a couple of minors

llvm/test/CodeGen/X86/shuffle-blendw.ll
3

You can probably reduce the number of check lines by adding common prefixes:

; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41,X86-SSE41
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41,X64-SSE41
...
9

Add targets with AVX512 but not AVX512BW test coverage?

This revision is now accepted and ready to land.Feb 13 2023, 6:46 AM
goldstein.w.n added inline comments.Feb 13 2023, 8:42 AM
llvm/test/CodeGen/X86/shuffle-blendw.ll
9

Think some knl targets have avx512f w.o bw

goldstein.w.n updated this revision to Diff 497561.Feb 14 2023, 11:16 PM

Rebase

Harbormaster completed remote builds in B213816: Diff 497561.Feb 15 2023, 12:28 AM
goldstein.w.n updated this revision to Diff 497900.Feb 15 2023, 11:55 PM

Rebase

goldstein.w.n updated this revision to Diff 497909.Feb 16 2023, 12:32 AM

Rebase

Harbormaster completed remote builds in B214077: Diff 497909.Feb 16 2023, 2:39 AM
goldstein.w.n updated this revision to Diff 498073.Feb 16 2023, 10:30 AM

Rebase

Harbormaster completed remote builds in B214199: Diff 498073.Feb 16 2023, 12:32 PM
goldstein.w.n updated this revision to Diff 499001.Feb 20 2023, 6:10 PM

Rebase

goldstein.w.n updated this revision to Diff 499026.Feb 20 2023, 7:53 PM

Rebase

Harbormaster completed remote builds in B214915: Diff 499026.Feb 20 2023, 10:29 PM
goldstein.w.n updated this revision to Diff 499385.Feb 21 2023, 11:41 PM

Rebase

Harbormaster completed remote builds in B215174: Diff 499385.Feb 22 2023, 1:06 AM
goldstein.w.n updated this revision to Diff 499547.Feb 22 2023, 9:14 AM

Rebase

goldstein.w.n added a parent revision: D144570: [X86] Add support for using Sched/Codesize information to `X86FixupInstTuning` Pass..Feb 22 2023, 9:15 AM
goldstein.w.n removed a parent revision: D143787: [X86] Add new pass `X86FixupInstTuning` for fixing up machine-instruction selection..
Harbormaster completed remote builds in B215288: Diff 499547.Feb 22 2023, 11:58 AM
goldstein.w.n updated this revision to Diff 499697.Feb 22 2023, 5:43 PM

Rebase

Harbormaster completed remote builds in B215405: Diff 499697.Feb 22 2023, 8:13 PM
goldstein.w.n updated this revision to Diff 500064.Feb 23 2023, 8:10 PM

Rebase

Harbormaster completed remote builds in B215665: Diff 500064.Feb 23 2023, 10:46 PM
goldstein.w.n updated this revision to Diff 500308.Feb 24 2023, 3:10 PM

Rebase

goldstein.w.n updated this revision to Diff 500377.Feb 24 2023, 11:31 PM

Rebase

Harbormaster completed remote builds in B215896: Diff 500377.Feb 24 2023, 11:32 PM
goldstein.w.n updated this revision to Diff 500478.Feb 25 2023, 5:00 PM

Rebase

Harbormaster completed remote builds in B215980: Diff 500478.Feb 25 2023, 6:53 PM
RKSimon added a comment.Feb 26 2023, 2:46 AM

@goldstein.w.n Why is this still dependent on D143787? It looks like its ready to be committed now

Closed by commit rG7ae071f98186: Add more tests for promoting `blendw` -> `blendd`; NFC (authored by goldstein.w.n). · Explain WhyFeb 26 2023, 10:12 AM
This revision was automatically updated to reflect the committed changes.
goldstein.w.n added a commit: rG7ae071f98186: Add more tests for promoting `blendw` -> `blendd`; NFC.
goldstein.w.n added a comment.Feb 26 2023, 10:26 AM
In D143788#4153336, @RKSimon wrote:

@goldstein.w.n Why is this still dependent on D143787? It looks like its ready to be committed now

Pushed the unrelated patches that have been approved.

goldstein.w.n removed a parent revision: D144570: [X86] Add support for using Sched/Codesize information to `X86FixupInstTuning` Pass..Feb 26 2023, 10:41 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
265 lines

Diff 496798

llvm/test/CodeGen/X86/shuffle-blendw.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X86-SSE41
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64-SSE41
RKSimonUnsubmitted
Not Done
ReplyInline Actions

You can probably reduce the number of check lines by adding common prefixes:

; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41,X86-SSE41
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41,X64-SSE41
...
RKSimon: You can probably reduce the number of check lines by adding common prefixes: ``` ; RUN: llc <…
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X86-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64-AVX2
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X86-AVX512
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64-AVX512
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Add targets with AVX512 but not AVX512BW test coverage?

RKSimon: Add targets with AVX512 but not AVX512BW test coverage?
goldstein.w.nAuthorUnsubmitted
Done
ReplyInline Actions

Think some knl targets have avx512f w.o bw

goldstein.w.n: Think some knl targets have avx512f w.o bw
define <16 x i16> @blendw_to_blendd_32(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) nounwind {
; X86-SSE41-LABEL: blendw_to_blendd_32:
; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: pushl %ebp
; X86-SSE41-NEXT: movl %esp, %ebp
; X86-SSE41-NEXT: andl $-16, %esp
; X86-SSE41-NEXT: subl $16, %esp
; X86-SSE41-NEXT: paddw 40(%ebp), %xmm1
; X86-SSE41-NEXT: paddw 24(%ebp), %xmm0
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],mem[2,3],xmm1[4,5],mem[6,7]
; X86-SSE41-NEXT: movl %ebp, %esp
; X86-SSE41-NEXT: popl %ebp
; X86-SSE41-NEXT: retl
;
; X64-SSE41-LABEL: blendw_to_blendd_32:
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: paddw %xmm5, %xmm1
; X64-SSE41-NEXT: paddw %xmm4, %xmm0
; X64-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; X64-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; X64-SSE41-NEXT: retq
;
; X86-AVX-LABEL: blendw_to_blendd_32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm4
; X86-AVX-NEXT: vpaddw %xmm3, %xmm4, %xmm3
; X86-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; X86-AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; X86-AVX-NEXT: retl
;
; X64-AVX-LABEL: blendw_to_blendd_32:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
; X64-AVX-NEXT: vextractf128 $1, %ymm0, %xmm4
; X64-AVX-NEXT: vpaddw %xmm3, %xmm4, %xmm3
; X64-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; X64-AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; X64-AVX-NEXT: retq
;
; X86-AVX2-LABEL: blendw_to_blendd_32:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; X86-AVX2-NEXT: retl
;
; X64-AVX2-LABEL: blendw_to_blendd_32:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X64-AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; X64-AVX2-NEXT: retq
;
; X86-AVX512-LABEL: blendw_to_blendd_32:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X86-AVX512-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7],ymm0[8,9],ymm1[10,11],ymm0[12,13],ymm1[14,15]
; X86-AVX512-NEXT: retl
;
; X64-AVX512-LABEL: blendw_to_blendd_32:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X64-AVX512-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7],ymm0[8,9],ymm1[10,11],ymm0[12,13],ymm1[14,15]
; X64-AVX512-NEXT: retq
%x1 = add <16 x i16> %x, %z
%shuffle = shufflevector <16 x i16> %x1, <16 x i16> %y, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 4, i32 5, i32 22, i32 23, i32 8, i32 9, i32 26, i32 27, i32 12, i32 13, i32 30, i32 31>
ret <16 x i16> %shuffle
}
define <8 x i16> @blendw_to_blendd_16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z) nounwind {
; X86-SSE41-LABEL: blendw_to_blendd_16:
; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: paddw %xmm2, %xmm0
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; X86-SSE41-NEXT: retl
;
; X64-SSE41-LABEL: blendw_to_blendd_16:
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: paddw %xmm2, %xmm0
; X64-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; X64-SSE41-NEXT: retq
;
; X86-AVX-LABEL: blendw_to_blendd_16:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; X86-AVX-NEXT: retl
;
; X64-AVX-LABEL: blendw_to_blendd_16:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; X64-AVX-NEXT: retq
;
; X86-AVX2-LABEL: blendw_to_blendd_16:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; X86-AVX2-NEXT: retl
;
; X64-AVX2-LABEL: blendw_to_blendd_16:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; X64-AVX2-NEXT: retq
;
; X86-AVX512-LABEL: blendw_to_blendd_16:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX512-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; X86-AVX512-NEXT: retl
;
; X64-AVX512-LABEL: blendw_to_blendd_16:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX512-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; X64-AVX512-NEXT: retq
%x1 = add <8 x i16> %x, %z
%shuffle = shufflevector <8 x i16> %x1, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
ret <8 x i16> %shuffle
}
define <16 x i16> @blendw_to_blendd_fail_32(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) nounwind {
; X86-SSE41-LABEL: blendw_to_blendd_fail_32:
; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: pushl %ebp
; X86-SSE41-NEXT: movl %esp, %ebp
; X86-SSE41-NEXT: andl $-16, %esp
; X86-SSE41-NEXT: subl $16, %esp
; X86-SSE41-NEXT: paddw 40(%ebp), %xmm1
; X86-SSE41-NEXT: paddw 24(%ebp), %xmm0
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3],xmm0[4,5],xmm2[6,7]
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2],mem[3],xmm1[4,5],mem[6,7]
; X86-SSE41-NEXT: movl %ebp, %esp
; X86-SSE41-NEXT: popl %ebp
; X86-SSE41-NEXT: retl
;
; X64-SSE41-LABEL: blendw_to_blendd_fail_32:
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: paddw %xmm5, %xmm1
; X64-SSE41-NEXT: paddw %xmm4, %xmm0
; X64-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3],xmm0[4,5],xmm2[6,7]
; X64-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[3],xmm1[4,5],xmm3[6,7]
; X64-SSE41-NEXT: retq
;
; X86-AVX-LABEL: blendw_to_blendd_fail_32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm4
; X86-AVX-NEXT: vpaddw %xmm3, %xmm4, %xmm3
; X86-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; X86-AVX-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [65535,65535,65535,0,65535,65535,0,0,65535,65535,65535,0,65535,65535,0,0]
; X86-AVX-NEXT: # ymm2 = mem[0,1,0,1]
; X86-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; X86-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1
; X86-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
; X86-AVX-NEXT: retl
;
; X64-AVX-LABEL: blendw_to_blendd_fail_32:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
; X64-AVX-NEXT: vextractf128 $1, %ymm0, %xmm4
; X64-AVX-NEXT: vpaddw %xmm3, %xmm4, %xmm3
; X64-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; X64-AVX-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [65535,65535,65535,0,65535,65535,0,0,65535,65535,65535,0,65535,65535,0,0]
; X64-AVX-NEXT: # ymm2 = mem[0,1,0,1]
; X64-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; X64-AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1
; X64-AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
; X64-AVX-NEXT: retq
;
; X86-AVX2-LABEL: blendw_to_blendd_fail_32:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6,7],ymm0[8,9,10],ymm1[11],ymm0[12,13],ymm1[14,15]
; X86-AVX2-NEXT: retl
;
; X64-AVX2-LABEL: blendw_to_blendd_fail_32:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X64-AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6,7],ymm0[8,9,10],ymm1[11],ymm0[12,13],ymm1[14,15]
; X64-AVX2-NEXT: retq
;
; X86-AVX512-LABEL: blendw_to_blendd_fail_32:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X86-AVX512-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6,7],ymm0[8,9,10],ymm1[11],ymm0[12,13],ymm1[14,15]
; X86-AVX512-NEXT: retl
;
; X64-AVX512-LABEL: blendw_to_blendd_fail_32:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; X64-AVX512-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5],ymm1[6,7],ymm0[8,9,10],ymm1[11],ymm0[12,13],ymm1[14,15]
; X64-AVX512-NEXT: retq
%x1 = add <16 x i16> %x, %z
%shuffle = shufflevector <16 x i16> %x1, <16 x i16> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 4, i32 5, i32 22, i32 23, i32 8, i32 9, i32 10, i32 27, i32 12, i32 13, i32 30, i32 31>
ret <16 x i16> %shuffle
}
define <8 x i16> @blendw_to_blendd_fail_16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z) nounwind {
; X86-SSE41-LABEL: blendw_to_blendd_fail_16:
; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: paddw %xmm2, %xmm0
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X86-SSE41-NEXT: retl
;
; X64-SSE41-LABEL: blendw_to_blendd_fail_16:
; X64-SSE41: # %bb.0:
; X64-SSE41-NEXT: paddw %xmm2, %xmm0
; X64-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-SSE41-NEXT: retq
;
; X86-AVX-LABEL: blendw_to_blendd_fail_16:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X86-AVX-NEXT: retl
;
; X64-AVX-LABEL: blendw_to_blendd_fail_16:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-AVX-NEXT: retq
;
; X86-AVX2-LABEL: blendw_to_blendd_fail_16:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X86-AVX2-NEXT: retl
;
; X64-AVX2-LABEL: blendw_to_blendd_fail_16:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-AVX2-NEXT: retq
;
; X86-AVX512-LABEL: blendw_to_blendd_fail_16:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X86-AVX512-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X86-AVX512-NEXT: retl
;
; X64-AVX512-LABEL: blendw_to_blendd_fail_16:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; X64-AVX512-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-AVX512-NEXT: retq
%x1 = add <8 x i16> %x, %z
%shuffle = shufflevector <8 x i16> %x1, <8 x i16> %y, <8 x i32> <i32 8, i32 1, i32 10, i32 11, i32 4, i32 5, i32 14, i32 15>
ret <8 x i16> %shuffle
}