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Differential D143721

[InstCombine] precommit tests for D143720
Needs ReviewPublic

Authored by inclyc on Feb 10 2023, 3:22 AM.

Details

Reviewers
nikic
spatel
bcl5980

Diff Detail

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
267 lines

Diff 496399

llvm/test/Transforms/InstCombine/simple_phi_condition.ll

Show All 29 Lines
; CHECK-LABEL: @test_inverted_implication( ; CHECK-LABEL: @test_inverted_implication(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK: if.true: ; CHECK: if.true:
; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false: ; CHECK: if.false:
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge: ; CHECK: merge:
; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND]], true ; CHECK-NEXT: [[RET:%.*]] = xor i1 [[COND]], true
; CHECK-NEXT: ret i1 [[TMP0]] ; CHECK-NEXT: ret i1 [[RET]]
; ;
entry: entry:
br i1 %cond, label %if.true, label %if.false br i1 %cond, label %if.true, label %if.false
if.true: if.true:
br label %merge br label %merge
if.false: if.false:
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[IV1_NEXT]] = add i32 [[IV1]], 1 ; CHECK-NEXT: [[IV1_NEXT]] = add i32 [[IV1]], 1
; CHECK-NEXT: [[LOOP_COND_1:%.*]] = icmp slt i32 [[IV1_NEXT]], [[CNT1:%.*]] ; CHECK-NEXT: [[LOOP_COND_1:%.*]] = icmp slt i32 [[IV1_NEXT]], [[CNT1:%.*]]
; CHECK-NEXT: br i1 [[LOOP_COND_1]], label [[LOOP1]], label [[IF_TRUE_END:%.*]] ; CHECK-NEXT: br i1 [[LOOP_COND_1]], label [[LOOP1]], label [[IF_TRUE_END:%.*]]
; CHECK: if.true.end: ; CHECK: if.true.end:
; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false: ; CHECK: if.false:
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge: ; CHECK: merge:
; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND]], true ; CHECK-NEXT: [[RET:%.*]] = xor i1 [[COND]], true
; CHECK-NEXT: ret i1 [[TMP0]] ; CHECK-NEXT: ret i1 [[RET]]
; ;
entry: entry:
br i1 %cond, label %if.true, label %if.false br i1 %cond, label %if.true, label %if.false
if.true: if.true:
br label %loop1 br label %loop1
loop1: loop1:
▲ Show 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: sw.1: ; CHECK: sw.1:
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: sw.2: ; CHECK: sw.2:
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: default: ; CHECK: default:
; CHECK-NEXT: ret i8 42 ; CHECK-NEXT: ret i8 42
; CHECK: merge: ; CHECK: merge:
; CHECK-NEXT: [[TMP0:%.*]] = xor i8 [[COND]], -1 ; CHECK-NEXT: [[RET:%.*]] = xor i8 [[COND]], -1
; CHECK-NEXT: ret i8 [[TMP0]] ; CHECK-NEXT: ret i8 [[RET]]
; ;
entry: entry:
switch i8 %cond, label %default [ switch i8 %cond, label %default [
i8 0, label %sw.0 i8 0, label %sw.0
i8 1, label %sw.1 i8 1, label %sw.1
i8 2, label %sw.2 i8 2, label %sw.2
] ]
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
sw.7: sw.7:
br label %merge br label %merge
sw.19: sw.19:
br label %merge br label %merge
merge: merge:
%ret = phi i8 [ 1, %sw.1 ], [ 7, %sw.7 ], [ 19, %sw.19 ] %ret = phi i8 [ 1, %sw.1 ], [ 7, %sw.7 ], [ 19, %sw.19 ]
ret i8 %ret ret i8 %ret
} }
define i32 @switch_to_sext(i8 noundef %0) {
; CHECK-LABEL: @switch_to_sext(
; CHECK-NEXT: switch i8 [[TMP0:%.*]], label [[BB2:%.*]] [
; CHECK-NEXT: i8 -1, label [[BB3:%.*]]
; CHECK-NEXT: i8 0, label [[BB4:%.*]]
; CHECK-NEXT: i8 1, label [[BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: unreachable
; CHECK: bb3:
; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb4:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOT0:%.*]] = phi i32 [ 1, [[BB1]] ], [ 0, [[BB4]] ], [ -1, [[BB3]] ]
; CHECK-NEXT: ret i32 [[DOT0]]
;
switch i8 %0, label %bb2 [
i8 -1, label %bb3
i8 0, label %bb4
i8 1, label %bb1
]
bb2: ; preds = %start
unreachable
bb3: ; preds = %start
br label %bb5
bb4: ; preds = %start
br label %bb5
bb1: ; preds = %start
br label %bb5
bb5: ; preds = %bb1, %bb4, %bb3
%.0 = phi i32 [ 1, %bb1 ], [ 0, %bb4 ], [ -1, %bb3 ]
ret i32 %.0
}
define i32 @switch_to_zext(i8 noundef %0) {
; CHECK-LABEL: @switch_to_zext(
; CHECK-NEXT: switch i8 [[TMP0:%.*]], label [[BB2:%.*]] [
; CHECK-NEXT: i8 -1, label [[BB3:%.*]]
; CHECK-NEXT: i8 0, label [[BB4:%.*]]
; CHECK-NEXT: i8 1, label [[BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: unreachable
; CHECK: bb3:
; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb4:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOT0:%.*]] = phi i32 [ 1, [[BB1]] ], [ 0, [[BB4]] ], [ 255, [[BB3]] ]
; CHECK-NEXT: ret i32 [[DOT0]]
;
switch i8 %0, label %bb2 [
i8 -1, label %bb3
i8 0, label %bb4
i8 1, label %bb1
]
bb2: ; preds = %start
unreachable
bb3: ; preds = %start
br label %bb5
bb4: ; preds = %start
br label %bb5
bb1: ; preds = %start
br label %bb5
bb5: ; preds = %bb1, %bb4, %bb3
%.0 = phi i32 [ 1, %bb1 ], [ 0, %bb4 ], [ 255, %bb3 ]
ret i32 %.0
}
define i8 @switch_to_trunc(i32 noundef %0) {
; CHECK-LABEL: @switch_to_trunc(
; CHECK-NEXT: switch i32 [[TMP0:%.*]], label [[BB2:%.*]] [
; CHECK-NEXT: i32 -1, label [[BB3:%.*]]
; CHECK-NEXT: i32 0, label [[BB4:%.*]]
; CHECK-NEXT: i32 1, label [[BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: unreachable
; CHECK: bb3:
; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb4:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOT0:%.*]] = phi i8 [ 1, [[BB1]] ], [ 0, [[BB4]] ], [ -1, [[BB3]] ]
; CHECK-NEXT: ret i8 [[DOT0]]
;
switch i32 %0, label %bb2 [
i32 -1, label %bb3
i32 0, label %bb4
i32 1, label %bb1
]
bb2: ; preds = %start
unreachable
bb3: ; preds = %start
br label %bb5
bb4: ; preds = %start
br label %bb5
bb1: ; preds = %start
br label %bb5
bb5: ; preds = %bb1, %bb4, %bb3
%.0 = phi i8 [ 1, %bb1 ], [ 0, %bb4 ], [ -1, %bb3 ]
ret i8 %.0
}
define i32 @switch_to_sext_invert(i8 noundef %0) {
; CHECK-LABEL: @switch_to_sext_invert(
; CHECK-NEXT: switch i8 [[TMP0:%.*]], label [[BB2:%.*]] [
; CHECK-NEXT: i8 -1, label [[BB3:%.*]]
; CHECK-NEXT: i8 0, label [[BB4:%.*]]
; CHECK-NEXT: i8 1, label [[BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: unreachable
; CHECK: bb3:
; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb4:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOT0:%.*]] = phi i32 [ -2, [[BB1]] ], [ -1, [[BB4]] ], [ 0, [[BB3]] ]
; CHECK-NEXT: ret i32 [[DOT0]]
;
switch i8 %0, label %bb2 [
i8 -1, label %bb3
i8 0, label %bb4
i8 1, label %bb1
]
bb2: ; preds = %start
unreachable
bb3: ; preds = %start
br label %bb5
bb4: ; preds = %start
br label %bb5
bb1: ; preds = %start
br label %bb5
bb5: ; preds = %bb1, %bb4, %bb3
%.0 = phi i32 [ -2, %bb1 ], [ -1, %bb4 ], [ 0, %bb3 ]
ret i32 %.0
}
define i32 @switch_to_zext_invert(i8 noundef %0) {
; CHECK-LABEL: @switch_to_zext_invert(
; CHECK-NEXT: switch i8 [[TMP0:%.*]], label [[BB2:%.*]] [
; CHECK-NEXT: i8 -1, label [[BB3:%.*]]
; CHECK-NEXT: i8 0, label [[BB4:%.*]]
; CHECK-NEXT: i8 1, label [[BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: unreachable
; CHECK: bb3:
; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb4:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOT0:%.*]] = phi i32 [ -2, [[BB1]] ], [ -1, [[BB4]] ], [ -256, [[BB3]] ]
; CHECK-NEXT: ret i32 [[DOT0]]
;
switch i8 %0, label %bb2 [
i8 -1, label %bb3
i8 0, label %bb4
i8 1, label %bb1
]
bb2: ; preds = %start
unreachable
bb3: ; preds = %start
br label %bb5
bb4: ; preds = %start
br label %bb5
bb1: ; preds = %start
br label %bb5
bb5: ; preds = %bb1, %bb4, %bb3
%.0 = phi i32 [ -2, %bb1 ], [ -1, %bb4 ], [ -256, %bb3 ]
ret i32 %.0
}
define i8 @switch_to_trunc_invert(i32 noundef %0) {
; CHECK-LABEL: @switch_to_trunc_invert(
; CHECK-NEXT: switch i32 [[TMP0:%.*]], label [[BB2:%.*]] [
; CHECK-NEXT: i32 -1, label [[BB3:%.*]]
; CHECK-NEXT: i32 0, label [[BB4:%.*]]
; CHECK-NEXT: i32 1, label [[BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: unreachable
; CHECK: bb3:
; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb4:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb1:
; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5:
; CHECK-NEXT: [[DOT0:%.*]] = phi i8 [ -2, [[BB1]] ], [ -1, [[BB4]] ], [ 0, [[BB3]] ]
; CHECK-NEXT: ret i8 [[DOT0]]
;
switch i32 %0, label %bb2 [
i32 -1, label %bb3
i32 0, label %bb4
i32 1, label %bb1
]
bb2: ; preds = %start
unreachable
bb3: ; preds = %start
br label %bb5
bb4: ; preds = %start
br label %bb5
bb1: ; preds = %start
br label %bb5
bb5: ; preds = %bb1, %bb4, %bb3
%.0 = phi i8 [ -2, %bb1 ], [ -1, %bb4 ], [ 0, %bb3 ]
ret i8 %.0
}