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Differential D142428

[InstCombine] Add tests that patterns for knownbits of and/or/xor apply in `SimplifyDemandedUseBits`; NFC
AbandonedPublic

Authored by goldstein.w.n on Jan 23 2023, 5:39 PM.

Details

Reviewers
nikic
majnemer

Diff Detail

Unit TestsFailed

TimeTest
60,060 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,060 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test
60,080 msx64 debian > libFuzzer.libFuzzer::out-of-process-fuzz.test
60,050 msx64 debian > libFuzzer.libFuzzer::value-profile-load.test

Event Timeline

goldstein.w.n created this revision.Jan 23 2023, 5:39 PM
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goldstein.w.n requested review of this revision.Jan 23 2023, 5:39 PM
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goldstein.w.n added a parent revision: D142427: [ValueTracking] Add logic for tracking lowbit of (and/xor/or X, (add/sub X, Odd)).Jan 23 2023, 5:40 PM
goldstein.w.n added a child revision: D142429: [InstCombine] Use `analyzeKnownBitsFromAndXorOr` in `SimplifyDemandedUseBits` for and/xor/or.
goldstein.w.n added reviewers: nikic, majnemer.
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Harbormaster completed remote builds in B209520: Diff 491576.Jan 23 2023, 7:19 PM
goldstein.w.n updated this revision to Diff 491969.Jan 24 2023, 5:12 PM

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Harbormaster completed remote builds in B209790: Diff 491969.Jan 24 2023, 6:57 PM
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Remove 1/3 of tests

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Harbormaster completed remote builds in B214806: Diff 498904.Feb 20 2023, 11:49 AM
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Harbormaster completed remote builds in B214848: Diff 498952.Feb 20 2023, 2:38 PM
nikic added a comment.Feb 22 2023, 2:13 PM

Hm, do we actually need these tests? It looks like the ValueTracking/knownbits-and-or-xor-lowbit.ll tests already demonstrate that the low bit patterns fold via demanded bits, and ValueTracking/knownbits-bmi-pattern.ll that the bmi patterns do as well, which covers all the relevant special cases, right?

goldstein.w.n added a comment.Feb 22 2023, 2:20 PM
In D142428#4145782, @nikic wrote:

Hm, do we actually need these tests? It looks like the ValueTracking/knownbits-and-or-xor-lowbit.ll tests already demonstrate that the low bit patterns fold via demanded bits, and ValueTracking/knownbits-bmi-pattern.ll that the bmi patterns do as well, which covers all the relevant special cases, right?

I think for the most part they are redundant (given the other files). LMK if you want me to drop (added mostly b.c policy is tests come with any patch).

nikic added a comment.Feb 23 2023, 12:13 AM
In D142428#4145793, @goldstein.w.n wrote:
In D142428#4145782, @nikic wrote:

Hm, do we actually need these tests? It looks like the ValueTracking/knownbits-and-or-xor-lowbit.ll tests already demonstrate that the low bit patterns fold via demanded bits, and ValueTracking/knownbits-bmi-pattern.ll that the bmi patterns do as well, which covers all the relevant special cases, right?

I think for the most part they are redundant (given the other files). LMK if you want me to drop (added mostly b.c policy is tests come with any patch).

I think it's fine to drop -- we do still have test coverage from previous test additions, so that's okay.

goldstein.w.n abandoned this revision.Feb 23 2023, 11:49 AM
In D142428#4146577, @nikic wrote:
In D142428#4145793, @goldstein.w.n wrote:
In D142428#4145782, @nikic wrote:

Hm, do we actually need these tests? It looks like the ValueTracking/knownbits-and-or-xor-lowbit.ll tests already demonstrate that the low bit patterns fold via demanded bits, and ValueTracking/knownbits-bmi-pattern.ll that the bmi patterns do as well, which covers all the relevant special cases, right?

I think for the most part they are redundant (given the other files). LMK if you want me to drop (added mostly b.c policy is tests come with any patch).

I think it's fine to drop -- we do still have test coverage from previous test additions, so that's okay.

Okay.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
345 lines

Diff 498952

llvm/test/Transforms/InstCombine/and-or-xor-lowbit-simplified.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
define i1 @cmp_ugt_0_sub_and_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_ugt_0_sub_and_eval(
; CHECK-NEXT: [[Y:%.*]] = add i32 [[X:%.*]], 1
; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp ne i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 129
%y = sub i32 %x, %C1
%z = and i32 %x, %y
%b = and i32 %z, 1
%e = icmp ugt i32 %b, 0
ret i1 %e
}
define i1 @cmp_eq_0_sub2_and_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_and_eval(
; CHECK-NEXT: ret i1 true
;
%C1 = or i32 %C, 19
%y = sub i32 %C1, %x
%z = and i32 %x, %y
%b = and i32 %z, 1
%e = icmp eq i32 %b, 0
ret i1 %e
}
define i1 @cmp_ne_0_sub_xor_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_ne_0_sub_xor_eval(
; CHECK-NEXT: ret i1 true
;
%C1 = or i32 %C, 13
%y = sub i32 %x, %C1
%z = xor i32 %x, %y
%b = and i32 %z, 1
%e = icmp ne i32 %b, 0
ret i1 %e
}
define i1 @cmp_sgt_0_add_or_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_sgt_0_add_or_eval(
; CHECK-NEXT: ret i1 true
;
%C1 = or i32 %C, 9
%y = add i32 %x, %C1
%z = or i32 %x, %y
%b = and i32 %z, 1
%e = icmp sgt i32 %b, 0
ret i1 %e
}
define i1 @cmp_ne_0_sub_or_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_ne_0_sub_or_eval(
; CHECK-NEXT: ret i1 true
;
%C1 = or i32 %C, 5
%y = sub i32 %x, %C1
%z = or i32 %x, %y
%b = and i32 %z, 1
%e = icmp ne i32 %b, 0
ret i1 %e
}
define i1 @cmp_eq_0_sub2_or_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_or_eval(
; CHECK-NEXT: ret i1 false
;
%C1 = or i32 %C, 3
%y = sub i32 %C1, %x
%z = or i32 %x, %y
%b = and i32 %z, 1
%e = icmp eq i32 %b, 0
ret i1 %e
}
define i1 @cmp_ne_0_add_and_no_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_ne_0_add_and_no_eval(
; CHECK-NEXT: [[Y:%.*]] = add i32 [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp ne i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 132
%y = add i32 %C1, %x
%z = and i32 %x, %y
%b = and i32 %z, 1
%e = icmp ne i32 %b, 0
ret i1 %e
}
define i1 @cmp_eq_0_sub2_and_no_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_and_no_eval(
; CHECK-NEXT: [[Y:%.*]] = sub i32 [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp eq i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 8
%y = sub i32 %C1, %x
%z = and i32 %x, %y
%b = and i32 %z, 1
%e = icmp eq i32 %b, 0
ret i1 %e
}
define i1 @cmp_ne_0_sub_xor_no_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_ne_0_sub_xor_no_eval(
; CHECK-NEXT: [[Y:%.*]] = sub i32 [[X:%.*]], [[C:%.*]]
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp ne i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 2
%y = sub i32 %x, %C1
%z = xor i32 %x, %y
%b = and i32 %z, 1
%e = icmp ne i32 %b, 0
ret i1 %e
}
define i1 @cmp_sgt_0_sub2_xor_no_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_sgt_0_sub2_xor_no_eval(
; CHECK-NEXT: [[Y:%.*]] = sub i32 [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp ne i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 24
%y = sub i32 %C1, %x
%z = xor i32 %x, %y
%b = and i32 %z, 1
%e = icmp sgt i32 %b, 0
ret i1 %e
}
define i1 @cmp_ne_0_sub_or_no_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_ne_0_sub_or_no_eval(
; CHECK-NEXT: [[Y:%.*]] = sub i32 [[X:%.*]], [[C:%.*]]
; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp ne i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 4
%y = sub i32 %x, %C1
%z = or i32 %x, %y
%b = and i32 %z, 1
%e = icmp ne i32 %b, 0
ret i1 %e
}
define i1 @cmp_eq_0_sub2_or_no_eval(i32 %x, i32 %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_or_no_eval(
; CHECK-NEXT: [[Y:%.*]] = sub i32 [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and i32 [[Z]], 1
; CHECK-NEXT: [[E:%.*]] = icmp eq i32 [[B]], 0
; CHECK-NEXT: ret i1 [[E]]
;
%C1 = or i32 %C, 128
%y = sub i32 %C1, %x
%z = or i32 %x, %y
%b = and i32 %z, 1
%e = icmp eq i32 %b, 0
ret i1 %e
}
define <2 x i1> @cmp_ne_0_add_and_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_ne_0_add_and_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = add <2 x i32> [[X:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[E:%.*]] = trunc <2 x i32> [[Z]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 131, i32 131>
%y = add <2 x i32> %C1, %x
%z = and <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp ne <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_eq_0_sub2_and_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_and_eval_vec(
; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
;
%C1 = or <2 x i32> %C, <i32 19, i32 19>
%y = sub <2 x i32> %C1, %x
%z = and <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp eq <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_ne_0_sub_xor_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_ne_0_sub_xor_eval_vec(
; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
;
%C1 = or <2 x i32> %C, <i32 13, i32 13>
%y = sub <2 x i32> %x, %C1
%z = xor <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp ne <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_sgt_0_sub2_xor_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_sgt_0_sub2_xor_eval_vec(
; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
;
%C1 = or <2 x i32> %C, <i32 1, i32 1>
%y = sub <2 x i32> %C1, %x
%z = xor <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp sgt <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_sgt_0_add_or_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_sgt_0_add_or_eval_vec(
; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
;
%C1 = or <2 x i32> %C, <i32 9, i32 9>
%y = add <2 x i32> %x, %C1
%z = or <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp sgt <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_eq_0_sub2_or_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_or_eval_vec(
; CHECK-NEXT: ret <2 x i1> zeroinitializer
;
%C1 = or <2 x i32> %C, <i32 3, i32 3>
%y = sub <2 x i32> %C1, %x
%z = or <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp eq <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_ne_0_add_and_no_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_ne_0_add_and_no_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = add <2 x i32> [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[E:%.*]] = trunc <2 x i32> [[Z]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 132, i32 132>
%y = add <2 x i32> %C1, %x
%z = and <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp ne <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_ugt_0_sub_and_no_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_ugt_0_sub_and_no_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = sub <2 x i32> [[X:%.*]], [[C:%.*]]
; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[E:%.*]] = trunc <2 x i32> [[Z]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 2, i32 2>
%y = sub <2 x i32> %x, %C1
%z = and <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp ugt <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_eq_0_add_xor_no_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_eq_0_add_xor_no_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = add <2 x i32> [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = xor <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[Z]], <i32 1, i32 1>
; CHECK-NEXT: [[E:%.*]] = icmp eq <2 x i32> [[B]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 4, i32 4>
%y = add <2 x i32> %x, %C1
%z = xor <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp eq <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_ne_0_sub_xor_no_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_ne_0_sub_xor_no_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = sub <2 x i32> [[X:%.*]], [[C:%.*]]
; CHECK-NEXT: [[Z:%.*]] = xor <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[E:%.*]] = trunc <2 x i32> [[Z]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 2, i32 2>
%y = sub <2 x i32> %x, %C1
%z = xor <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp ne <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_sgt_0_add_or_no_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_sgt_0_add_or_no_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = add <2 x i32> [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = or <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[E:%.*]] = trunc <2 x i32> [[Z]] to <2 x i1>
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 6, i32 6>
%y = add <2 x i32> %x, %C1
%z = or <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp sgt <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}
define <2 x i1> @cmp_eq_0_sub2_or_no_eval_vec(<2 x i32> %x, <2 x i32> %C) {
; CHECK-LABEL: @cmp_eq_0_sub2_or_no_eval_vec(
; CHECK-NEXT: [[Y:%.*]] = sub <2 x i32> [[C:%.*]], [[X:%.*]]
; CHECK-NEXT: [[Z:%.*]] = or <2 x i32> [[Y]], [[X]]
; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[Z]], <i32 1, i32 1>
; CHECK-NEXT: [[E:%.*]] = icmp eq <2 x i32> [[B]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[E]]
;
%C1 = or <2 x i32> %C, <i32 128, i32 128>
%y = sub <2 x i32> %C1, %x
%z = or <2 x i32> %x, %y
%b = and <2 x i32> %z, <i32 1, i32 1>
%e = icmp eq <2 x i32> %b, <i32 0, i32 0>
ret <2 x i1> %e
}