[mips][ias] Range check uimmz operands.

[vkalintiris]

LGTM. Added two minor nits.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3241–3242

Const-ify Operands and avoid passing-by-ref of ErrorInfo.

3244

We don't need the cast if we use ->.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
 
   void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
     clearFeatureBits(Feature, FeatureString);
     AssemblerOptions.front()->setFeatures(STI.getFeatureBits());
   }
 
 public:
   enum MipsMatchResultTy {
-    Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY
+    Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "MipsGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
 
   };
 
   MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII, const MCTargetOptions &Options)
void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::createReg(getCCRReg()));
   }
 
   void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getHWRegsReg()));
   }
 
+  template <unsigned Bits>
+  void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    uint64_t Imm = getConstantImm() & ((1 << Bits) - 1);
+    Inst.addOperand(MCOperand::createImm(Imm));
+  }
+
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCExpr *Expr = getImm();
     addExpr(Inst, Expr);
   }
 
   void addMemOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
bool isReg() const override {
 
     return Kind == k_PhysRegister;
   }
   bool isRegIdx() const { return Kind == k_RegisterIndex; }
   bool isImm() const override { return Kind == k_Immediate; }
   bool isConstantImm() const {
     return isImm() && dyn_cast<MCConstantExpr>(getImm());
   }
+  bool isConstantImmz() const {
+    return isConstantImm() && getConstantImm() == 0;
+  }
   template <unsigned Bits> bool isUImm() const {
     return isImm() && isConstantImm() && isUInt<Bits>(getConstantImm());
   }
   bool isToken() const override {
     // Note: It's not possible to pretend that other operand kinds are tokens.
     // The matcher emitter checks tokens first.
     return Kind == k_Token;
   }
unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   if (Opcode == Mips::JALR_HB &&
       (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
     return Match_RequiresDifferentSrcAndDst;
 
   return Match_Success;
 }
 
+static SMLoc RefineErrorLoc(SMLoc Loc, OperandVector &Operands,
+                            uint64_t &ErrorInfo) {
+  if (ErrorInfo != ~0ULL && ErrorInfo < Operands.size()) {
+    SMLoc ErrorLoc = ((MipsOperand &)*Operands[ErrorInfo]).getStartLoc();
+    if (ErrorLoc == SMLoc())
+      return Loc;
+    return ErrorLoc;
+  }
+  return Loc;
+}
+
 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                             OperandVector &Operands,
                                             MCStreamer &Out,
                                             uint64_t &ErrorInfo,
                                             bool MatchingInlineAsm) {
 
   MCInst Inst;
   SmallVector<MCInst, 8> Instructions;
case Match_InvalidOperand: {
     }
 
     return Error(ErrorLoc, "invalid operand for instruction");
   }
   case Match_MnemonicFail:
     return Error(IDLoc, "invalid instruction");
   case Match_RequiresDifferentSrcAndDst:
     return Error(IDLoc, "source and destination must be different");
+  case Match_Immz:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'");
   }
 
   llvm_unreachable("Implement any new match types added!");
 }
 
 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) {
   if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex)
     Warning(Loc, "used $at (currently $" + Twine(RegIndex) +

lib/Target/Mips/MipsInstrInfo.td

 //===----------------------------------------------------------------------===//
 
 include "MipsInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Mips Operand, Complex Patterns and Transformations Definitions.
 //===----------------------------------------------------------------------===//
 
+def ConstantImmzAsmOperandClass : AsmOperandClass {
+  let Name = "ConstantImmz";
+  let RenderMethod = "addConstantUImmOperands<1>";
+  let PredicateMethod = "isConstantImmz";
+  let SuperClasses = [];
+  let DiagnosticType = "Immz";
+}
+
 def MipsJumpTargetAsmOperand : AsmOperandClass {
   let Name = "JumpTarget";
   let ParserMethod = "parseJumpTarget";
   let PredicateMethod = "isImm";
   let RenderMethod = "addImmOperands";
 }
 
 // Instruction operand types

 
 def simm16_64   : Operand<i64> {
   let DecoderMethod = "DecodeSimm16";
 }
 
 // Zero
 def uimmz       : Operand<i32> {
   let PrintMethod = "printUnsignedImm";
+  let ParserMatchClass = ConstantImmzAsmOperandClass;
 }
 
 // Unsigned Operand
 def uimm2 : Operand<i32> {
   let PrintMethod = "printUnsignedImm";
 }
 
 def uimm3 : Operand<i32> {

test/MC/Mips/msa/invalid-64.s

+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa \
+# RUN:     -show-encoding 2>%t1
+# RUN: FileCheck %s < %t1
+
+    .set noat
+    insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0'
+    insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
+    insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
+    insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0'

test/MC/Mips/msa/invalid.s

+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa \
+# RUN:     -show-encoding 2>%t1
+# RUN: FileCheck %s < %t1
+
+    .set noat
+    insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0'
+    insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
+    insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
+    insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0'