[TableGen] Let -register-info-debug dump Offset/Size for each SubRegIndex

[bjope]

Summary

This patch adds dumping of the Offset and Size info for each
SubRegIndex printed when using

llvm-tblgen -gen-register-info -register-info-debug

It also updates the ConcatenatedSubregs.td to check those printouts,
including some new subreg definitions that show short-comings in
how the size is calculated when concatenating subregisters and at
least one has an incomplete size (-1). Today TableGen will just add
sizes together, resulting in MCRegisterInfo::getSubRegIdxSize()
returning a value that isn't -1 even if the combined subregister size
is unknown.

[arsenm]

LGTM

llvm/test/TableGen/ConcatenatedSubregs.td

 //       \            \- S1 (ssub1)
 //        \ D1 (sub1) -- S2 (ssub2)
 //                    \- S3 (ssub3)
 
 def sub0 : SubRegIndex<32>;
 def sub1 : SubRegIndex<32, 32>;
 def sub2 : SubRegIndex<32, 64>;
 
-def ssub0 : SubRegIndex<16>;
+def ssub0 : SubRegIndex<-1>;
 def ssub1 : SubRegIndex<16, 16>;
 def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
 def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
 def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
 
 def S0 : MyReg<"s0">;
 def S1 : MyReg<"s1">;
 def S2 : MyReg<"s2">;

 def D1 : MyReg<"d1", [S2, S3]>;
 def D2 : MyReg<"d2", [S4, S5]>;
 def D3 : MyReg<"d3", [S6, S7]>;
 def D4 : MyReg<"d4", [S8, S9]>;
 def D5 : MyReg<"d5", [S10, S11]>;
 def D6 : MyReg<"d6", [S12, S13]>;
 def D7 : MyReg<"d7", [S14, S15]>;
 }
+
 def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 7)>;
 
 def Dtup2regs : RegisterTuples<[sub0, sub1],
                            [(shl DRegs, 0), (shl DRegs, 1)]>;
 def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>;
 
 def Stup2_odds_regs : RegisterTuples<[ssub0, ssub1],
                                      [(decimate (shl SRegs, 1), 2),

 // CHECK: CoveredBySubRegs: 1
 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
 
 // CHECK-LABEL: RegisterClass Stup2:
 // CHECK: CoveredBySubRegs: 1
 // CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
 // CHECK-LABEL: RegisterClass DRegs:
 
+// CHECK-LABEL: SubRegIndex ssub1:
+// CHECK:        Offset, Size: 16, 16
 // CHECK-LABEL: SubRegIndex sub0:
 // CHECK-LABEL: SubRegIndex sub1:
 // CHECK-LABEL: SubRegIndex sub2:
 // Check inferred indexes:
-// CHECK: SubRegIndex ssub1_ssub2:
-// CHECK: SubRegIndex ssub3_ssub4:
-// CHECK: SubRegIndex ssub0_ssub1_ssub2_ssub3:
-// CHECK: SubRegIndex ssub1_ssub2_ssub3_ssub4:
+// CHECK-LABEL: SubRegIndex ssub1_ssub2:
+// FIXME: Size should be unknown (65535).
+// CHECK:         Offset, Size: 16, 15
+// CHECK-LABEL: SubRegIndex ssub3_ssub4:
+// CHECK-LABEL: SubRegIndex ssub0_ssub1_ssub2_ssub3:
+// FIXME: Size should be unknown (65535).
+// CHECK:         Offset, Size: 65535, 30
+// CHECK-LABEL: SubRegIndex ssub1_ssub2_ssub3_ssub4:
 
 // Check that all subregs are generated on some examples
 // CHECK-LABEL: Register D0:
 // CHECK: HasDisjunctSubRegs: 1
 // CHECK-NEXT: SubReg ssub0 = S0
 // CHECK-NEXT: SubReg ssub1 = S1
 
 // CHECK-LABEL: Register S9_S10_S11_S12_S13:

llvm/utils/TableGen/RegisterInfoEmitter.cpp

for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
     }
     OS << '\n';
   }
 
   for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
     OS << "SubRegIndex " << SRI.getName() << ":\n";
     OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';
     OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';
+    OS << "\tOffset, Size: " << SRI.Offset << ", " << SRI.Size << '\n';
   }
 
   for (const CodeGenRegister &R : RegBank.getRegisters()) {
     OS << "Register " << R.getName() << ":\n";
     OS << "\tCostPerUse: ";
     for (const auto &Cost : R.CostPerUse)
       OS << Cost << " ";
     OS << '\n';