AMDGPU: Fold llvm.amdgcn.sqrt(undef)

[arsenm]

Attach correct patch

[foad]

llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

355

Just merge with the amdgcn_rsq case?

[arsenm]

Merge. I was hoping to get some real constant folding here but that probably won't happen anytime soon

[arsenm]

a58541f14d2d3e7d65f2e9b341bf2321b312c615

llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

bool GCNTTIImpl::canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1,
   }
   return false;
 }
 
 Optional<Instruction *>
 GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
   Intrinsic::ID IID = II.getIntrinsicID();
   switch (IID) {
   case Intrinsic::amdgcn_rcp: {
     Value *Src = II.getArgOperand(0);
 
     // TODO: Move to ConstantFolding/InstSimplify?
     if (isa<UndefValue>(Src)) {
       Type *Ty = II.getType();
       auto *QNaN = ConstantFP::get(Ty, APFloat::getQNaN(Ty->getFltSemantics()));
       return IC.replaceInstUsesWith(II, QNaN);
     }
if (const ConstantFP *C = dyn_cast<ConstantFP>(Src)) {
       //
       // TODO: The instruction always flushes denormal results (except for f16),
       // should this also?
       return IC.replaceInstUsesWith(II, ConstantFP::get(II.getContext(), Val));
     }
 
     break;
   }
+  case Intrinsic::amdgcn_sqrt:
   case Intrinsic::amdgcn_rsq: {
     Value *Src = II.getArgOperand(0);
 
     // TODO: Move to ConstantFolding/InstSimplify?
     if (isa<UndefValue>(Src)) {
       Type *Ty = II.getType();
       auto *QNaN = ConstantFP::get(Ty, APFloat::getQNaN(Ty->getFltSemantics()));
       return IC.replaceInstUsesWith(II, QNaN);

llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll

 ; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #[[ATTR14:[0-9]+]]
 ; CHECK-NEXT:    ret float [[VAL]]
 ;
   %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) strictfp nounwind readnone
   ret float %val
 }
 
 ; --------------------------------------------------------------------
+; llvm.amdgcn.sqrt
+; --------------------------------------------------------------------
+
+declare half @llvm.amdgcn.sqrt.f16(half) nounwind readnone
+declare float @llvm.amdgcn.sqrt.f32(float) nounwind readnone
+declare double @llvm.amdgcn.sqrt.f64(double) nounwind readnone
+
+define half @test_constant_fold_sqrt_f16_undef() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f16_undef(
+; CHECK-NEXT:    ret half 0xH7E00
+;
+  %val = call half @llvm.amdgcn.sqrt.f16(half undef) nounwind readnone
+  ret half %val
+}
+
+define float @test_constant_fold_sqrt_f32_undef() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f32_undef(
+; CHECK-NEXT:    ret float 0x7FF8000000000000
+;
+  %val = call float @llvm.amdgcn.sqrt.f32(float undef) nounwind readnone
+  ret float %val
+}
+
+define double @test_constant_fold_sqrt_f64_undef() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f64_undef(
+; CHECK-NEXT:    ret double 0x7FF8000000000000
+;
+  %val = call double @llvm.amdgcn.sqrt.f64(double undef) nounwind readnone
+  ret double %val
+}
+
+define half @test_constant_fold_sqrt_f16_0() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f16_0(
+; CHECK-NEXT:    [[VAL:%.*]] = call half @llvm.amdgcn.sqrt.f16(half 0xH0000) #[[ATTR15:[0-9]+]]
+; CHECK-NEXT:    ret half [[VAL]]
+;
+  %val = call half @llvm.amdgcn.sqrt.f16(half 0.0) nounwind readnone
+  ret half %val
+}
+
+define float @test_constant_fold_sqrt_f32_0() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f32_0(
+; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float 0.000000e+00) #[[ATTR15]]
+; CHECK-NEXT:    ret float [[VAL]]
+;
+  %val = call float @llvm.amdgcn.sqrt.f32(float 0.0) nounwind readnone
+  ret float %val
+}
+
+define double @test_constant_fold_sqrt_f64_0() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f64_0(
+; CHECK-NEXT:    [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0.000000e+00) #[[ATTR15]]
+; CHECK-NEXT:    ret double [[VAL]]
+;
+  %val = call double @llvm.amdgcn.sqrt.f64(double 0.0) nounwind readnone
+  ret double %val
+}
+
+define half @test_constant_fold_sqrt_f16_neg0() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f16_neg0(
+; CHECK-NEXT:    [[VAL:%.*]] = call half @llvm.amdgcn.sqrt.f16(half 0xH8000) #[[ATTR15]]
+; CHECK-NEXT:    ret half [[VAL]]
+;
+  %val = call half @llvm.amdgcn.sqrt.f16(half -0.0) nounwind readnone
+  ret half %val
+}
+
+define float @test_constant_fold_sqrt_f32_neg0() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f32_neg0(
+; CHECK-NEXT:    [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float -0.000000e+00) #[[ATTR15]]
+; CHECK-NEXT:    ret float [[VAL]]
+;
+  %val = call float @llvm.amdgcn.sqrt.f32(float -0.0) nounwind readnone
+  ret float %val
+}
+
+define double @test_constant_fold_sqrt_f64_neg0() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_f64_neg0(
+; CHECK-NEXT:    [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double -0.000000e+00) #[[ATTR15]]
+; CHECK-NEXT:    ret double [[VAL]]
+;
+  %val = call double @llvm.amdgcn.sqrt.f64(double -0.0) nounwind readnone
+  ret double %val
+}
+
+define double @test_constant_fold_sqrt_snan_f64() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_snan_f64(
+; CHECK-NEXT:    [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0x7FF0000000000001)
+; CHECK-NEXT:    ret double [[VAL]]
+;
+  %val = call double @llvm.amdgcn.sqrt.f64(double 0x7FF0000000000001)
+  ret double %val
+}
+
+define double @test_constant_fold_sqrt_qnan_f64() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_qnan_f64(
+; CHECK-NEXT:    [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0x7FF8000000000000)
+; CHECK-NEXT:    ret double [[VAL]]
+;
+  %val = call double @llvm.amdgcn.sqrt.f64(double 0x7FF8000000000000)
+  ret double %val
+}
+
+define double @test_constant_fold_sqrt_neg1() nounwind {
+; CHECK-LABEL: @test_constant_fold_sqrt_neg1(
+; CHECK-NEXT:    [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double -1.000000e+00)
+; CHECK-NEXT:    ret double [[VAL]]
+;
+  %val = call double @llvm.amdgcn.sqrt.f64(double -1.0)
+  ret double %val
+}
+
+; --------------------------------------------------------------------
 ; llvm.amdgcn.rsq
 ; --------------------------------------------------------------------
 
 declare float @llvm.amdgcn.rsq.f32(float) nounwind readnone
 
 define float @test_constant_fold_rsq_f32_undef() nounwind {
 ; CHECK-LABEL: @test_constant_fold_rsq_f32_undef(
 ; CHECK-NEXT:    ret float 0x7FF8000000000000

 ; CHECK-NEXT:    ret i64 0
 ;
   %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32)
   ret i64 %result
 }
 
 define i64 @icmp_constant_inputs_true() {
 ; CHECK-LABEL: @icmp_constant_inputs_true(
-; CHECK-NEXT:    [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR15:[0-9]+]]
+; CHECK-NEXT:    [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR16:[0-9]+]]
 ; CHECK-NEXT:    ret i64 [[RESULT]]
 ;
   %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34)
   ret i64 %result
 }
 
 define i64 @icmp_constant_to_rhs_slt(i32 %x) {
 ; CHECK-LABEL: @icmp_constant_to_rhs_slt(

 ; CHECK-NEXT:    ret i64 0
 ;
   %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1)
   ret i64 %result
 }
 
 define i64 @fcmp_constant_inputs_true() {
 ; CHECK-LABEL: @fcmp_constant_inputs_true(
-; CHECK-NEXT:    [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR15]]
+; CHECK-NEXT:    [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR16]]
 ; CHECK-NEXT:    ret i64 [[RESULT]]
 ;
   %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4)
   ret i64 %result
 }
 
 define i64 @fcmp_constant_to_rhs_olt(float %x) {
 ; CHECK-LABEL: @fcmp_constant_to_rhs_olt(

 ; CHECK-NEXT:    ret i64 0
 ;
   %b = call i64 @llvm.amdgcn.ballot.i64(i1 0)
   ret i64 %b
 }
 
 define i64 @ballot_one_64() {
 ; CHECK-LABEL: @ballot_one_64(
-; CHECK-NEXT:    [[B:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR15]]
+; CHECK-NEXT:    [[B:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR16]]
 ; CHECK-NEXT:    ret i64 [[B]]
 ;
   %b = call i64 @llvm.amdgcn.ballot.i64(i1 1)
   ret i64 %b
 }
 
 define i32 @ballot_nocombine_32(i1 %i) {
 ; CHECK-LABEL: @ballot_nocombine_32(

 ; CHECK-NEXT:    ret i32 0
 ;
   %b = call i32 @llvm.amdgcn.ballot.i32(i1 0)
   ret i32 %b
 }
 
 define i32 @ballot_one_32() {
 ; CHECK-LABEL: @ballot_one_32(
-; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.read_register.i32(metadata [[META1:![0-9]+]]) #[[ATTR15]]
+; CHECK-NEXT:    [[B:%.*]] = call i32 @llvm.read_register.i32(metadata [[META1:![0-9]+]]) #[[ATTR16]]
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %b = call i32 @llvm.amdgcn.ballot.i32(i1 1)
   ret i32 %b
 }
 
 ; --------------------------------------------------------------------
 ; llvm.amdgcn.wqm.vote