[ValueTracking] Fix CannotBeOrderedLessThanZero() for fdiv (PR58046)

[nikic]

Summary

When checking the RHS of fdiv, we should set the SignBitOnly flag, because a negative zero can become -Inf, which is ordered less than zero.

Fixes https://github.com/llvm/llvm-project/issues/58046.

[arsenm]

LGTM

[spatel]

LGTM

llvm/test/Transforms/InstSimplify/floating-point-compare.ll

1002

This wasn't just wrong...it was really, really wrong. :)
https://alive2.llvm.org/ce/z/p4D5Bo

Worth a TODO; some missing analysis of int-to-FP casts?

[nikic]

llvm/test/Transforms/InstSimplify/floating-point-compare.ll

1002

It looks like our fmul zero folds currently only support FMF folds, not anything ValueTracking based: https://github.com/llvm/llvm-project/blob/8b38a2c0a55a9140115a91959326918d99bea435/llvm/lib/Analysis/InstructionSimplify.cpp#L5313-L5319

llvm/lib/Analysis/ValueTracking.cpp

if (!I)
     return false;
 
   switch (I->getOpcode()) {
   default:
     break;
   // Unsigned integers are always nonnegative.
   case Instruction::UIToFP:
     return true;
-  case Instruction::FMul:
   case Instruction::FDiv:
-    // X * X is always non-negative or a NaN.
     // X / X is always exactly 1.0 or a NaN.
     if (I->getOperand(0) == I->getOperand(1) &&
         (!SignBitOnly || cast<FPMathOperator>(I)->hasNoNaNs()))
       return true;
 
+    // Set SignBitOnly for RHS, because X / -0.0 is -Inf (or NaN).
+    return cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
+                                           Depth + 1) &&
+           cannotBeOrderedLessThanZeroImpl(I->getOperand(1), TLI,
+                                           /*SignBitOnly*/ true, Depth + 1);
+  case Instruction::FMul:
+    // X * X is always non-negative or a NaN.
+    if (I->getOperand(0) == I->getOperand(1) &&
+        (!SignBitOnly || cast<FPMathOperator>(I)->hasNoNaNs()))
+      return true;
+
     [[fallthrough]];
   case Instruction::FAdd:
   case Instruction::FRem:
     return cannotBeOrderedLessThanZeroImpl(I->getOperand(0), TLI, SignBitOnly,
                                            Depth + 1) &&
            cannotBeOrderedLessThanZeroImpl(I->getOperand(1), TLI, SignBitOnly,
                                            Depth + 1);
   case Instruction::Select:

llvm/test/Transforms/InstSimplify/floating-point-compare.ll

 ; CHECK-LABEL: @known_positive_une_with_negative_constant_splat_vec(
 ; CHECK-NEXT:    ret <2 x i1> <i1 true, i1 true>
 ;
   %call = uitofp <2 x i32> %a to <2 x half>
   %cmp = fcmp une <2 x half> %call, <half -6.0, half -6.0>
   ret <2 x i1> %cmp
 }
 
-; FIXME: Miscompile.
+; TODO: This could fold to true.
 define i1 @pr58046(i64 %arg) {
 ; CHECK-LABEL: @pr58046(
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    [[FP:%.*]] = uitofp i64 [[ARG:%.*]] to double
+; CHECK-NEXT:    [[MUL:%.*]] = fmul double -0.000000e+00, [[FP]]
+; CHECK-NEXT:    [[DIV:%.*]] = fdiv double 1.000000e+00, [[MUL]]
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq double [[DIV]], 0xFFF0000000000000
+; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %fp = uitofp i64 %arg to double
   %mul = fmul double -0.000000e+00, %fp
   %div = fdiv double 1.000000e+00, %mul
   %cmp = fcmp oeq double %div, 0xFFF0000000000000
   ret i1 %cmp
 }