[lld-macho] Simplify linker optimization hint processing

[BertalanD]

Summary

This commit removes the relocTargets vector, and instead makes the
code reconstruct the referent addresses from the relocated instructions.
This will allow us to move applyOptimizationHints from
ConcatInputSection::writeTo to a separate pass that parses and applies
LOHs at the same time, on a per-file basis. This will improve
performance, as parsing is currently done serially in ObjFile::parse.

I opted to remove the sanity check that ensures that all relocations
within a LOH point to the same symbol. This completely removes the need
to search through relocations. Mismatched referents should not be
present in valid object files, so it's unlikely that the removal will
lead to mislinks.

[int3]

Neat! I assume you'll add perf numbers in the diff that parallelizes this :)

[BertalanD]

Rebased in order to re-run precommit checks before I push.

lld/MachO/Arch/ARM64.cpp

struct ARM64 : ARM64Common {
   void writeStubHelperEntry(uint8_t *buf, const Symbol &,
                             uint64_t entryAddr) const override;
 
   void writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, uint64_t stubsAddr,
                             uint64_t stubOffset, uint64_t selrefsVA,
                             uint64_t selectorIndex, uint64_t gotAddr,
                             uint64_t msgSendIndex) const override;
   void populateThunk(InputSection *thunk, Symbol *funcSym) override;
-  void applyOptimizationHints(uint8_t *, const ConcatInputSection *,
-                              ArrayRef<uint64_t>) const override;
+  void applyOptimizationHints(uint8_t *,
+                              const ConcatInputSection *) const override;
 };
 
 } // namespace
 
 // Random notes on reloc types:
 // ADDEND always pairs with BRANCH26, PAGE21, or PAGEOFF12
 // POINTER_TO_GOT: ld64 supports a 4-byte pc-relative form as well as an 8-byte
 // absolute version of this relocation. The semantics of the absolute relocation
ARM64::ARM64() : ARM64Common(LP64()) {
   stubHelperEntrySize = sizeof(stubHelperEntryCode);
 
   relocAttrs = {relocAttrsArray.data(), relocAttrsArray.size()};
 }
 
 namespace {
 struct Adrp {
   uint32_t destRegister;
+  int64_t addend;
 };
 
 struct Add {
   uint8_t destRegister;
   uint8_t srcRegister;
   uint32_t addend;
 };
 
 enum ExtendType { ZeroExtend = 1, Sign64 = 2, Sign32 = 3 };
 
 struct Ldr {
   uint8_t destRegister;
   uint8_t baseRegister;
   uint8_t p2Size;
   bool isFloat;
   ExtendType extendType;
   int64_t offset;
 };
 
-struct PerformedReloc {
-  const Reloc &rel;
-  uint64_t referentVA;
-};
-
 class OptimizationHintContext {
 public:
-  OptimizationHintContext(uint8_t *buf, const ConcatInputSection *isec,
-                          ArrayRef<uint64_t> relocTargets)
-      : buf(buf), isec(isec), relocTargets(relocTargets),
-        relocIt(isec->relocs.rbegin()) {}
-
-  void applyAdrpAdd(const OptimizationHint &);
-  void applyAdrpAdrp(const OptimizationHint &);
-  void applyAdrpLdr(const OptimizationHint &);
-  void applyAdrpLdrGot(const OptimizationHint &);
-  void applyAdrpAddLdr(const OptimizationHint &);
-  void applyAdrpLdrGotLdr(const OptimizationHint &);
+  OptimizationHintContext(uint8_t *buf, const ConcatInputSection *isec)
+      : buf(buf), isec(isec) {}
+
+  void applyAdrpAdd(uint64_t, uint64_t);
+  void applyAdrpAdrp(uint64_t, uint64_t);
+  void applyAdrpLdr(uint64_t, uint64_t);
+  void applyAdrpLdrGot(uint64_t, uint64_t);
+  void applyAdrpAddLdr(uint64_t, uint64_t, uint64_t);
+  void applyAdrpLdrGotLdr(uint64_t, uint64_t, uint64_t);
 
 private:
   uint8_t *buf;
   const ConcatInputSection *isec;
-  ArrayRef<uint64_t> relocTargets;
-  std::vector<Reloc>::const_reverse_iterator relocIt;
-
-  uint64_t getRelocTarget(const Reloc &);
-
-  Optional<PerformedReloc> findPrimaryReloc(uint64_t offset);
-  Optional<PerformedReloc> findReloc(uint64_t offset);
 };
 } // namespace
 
 static bool parseAdrp(uint32_t insn, Adrp &adrp) {
   if ((insn & 0x9f000000) != 0x90000000)
     return false;
   adrp.destRegister = insn & 0x1f;
+  uint64_t immHi = (insn >> 5) & 0x7ffff;
+  uint64_t immLo = (insn >> 29) & 0x3;
+  adrp.addend = SignExtend64<21>(immLo | (immHi << 2)) * 4096;
   return true;
 }
 
 static bool parseAdd(uint32_t insn, Add &add) {
   if ((insn & 0xffc00000) != 0x91000000)
     return false;
   add.destRegister = insn & 0x1f;
   add.srcRegister = (insn >> 5) & 0x1f;
static void writeImmediateLdr(void *loc, const Ldr &ldr) {
   } else {
     opc = ldr.extendType;
     size = ldr.p2Size;
   }
   uint32_t immBits = ldr.offset >> ldr.p2Size;
   write32le(loc, opcode | (immBits << 10) | (opc << 22) | (size << 30));
 }
 
-uint64_t OptimizationHintContext::getRelocTarget(const Reloc &reloc) {
-  size_t relocIdx = &reloc - isec->relocs.data();
-  return relocTargets[relocIdx];
-}
-
-// Optimization hints are sorted in a monotonically increasing order by their
-// first address as are relocations (albeit in decreasing order), so if we keep
-// a pointer around to the last found relocation, we don't have to do a full
-// binary search every time.
-Optional<PerformedReloc>
-OptimizationHintContext::findPrimaryReloc(uint64_t offset) {
-  const auto end = isec->relocs.rend();
-  while (relocIt != end && relocIt->offset < offset)
-    ++relocIt;
-  if (relocIt == end || relocIt->offset != offset)
-    return None;
-  return PerformedReloc{*relocIt, getRelocTarget(*relocIt)};
-}
-
-// The second and third addresses of optimization hints have no such
-// monotonicity as the first, so we search the entire range of relocations.
-Optional<PerformedReloc> OptimizationHintContext::findReloc(uint64_t offset) {
-  // Optimization hints often apply to successive relocations, so we check for
-  // that first before doing a full binary search.
-  auto end = isec->relocs.rend();
-  if (relocIt < end - 1 && (relocIt + 1)->offset == offset)
-    return PerformedReloc{*(relocIt + 1), getRelocTarget(*(relocIt + 1))};
-
-  auto reloc = lower_bound(isec->relocs, offset,
-                           [](const Reloc &reloc, uint64_t offset) {
-                             return offset < reloc.offset;
-                           });
-
-  if (reloc == isec->relocs.end() || reloc->offset != offset)
-    return None;
-  return PerformedReloc{*reloc, getRelocTarget(*reloc)};
-}
-
 // Transforms a pair of adrp+add instructions into an adr instruction if the
 // target is within the +/- 1 MiB range allowed by the adr's 21 bit signed
 // immediate offset.
 //
 //   adrp xN, _foo@PAGE
 //   add  xM, xN, _foo@PAGEOFF
 // ->
 //   adr  xM, _foo
 //   nop
-void OptimizationHintContext::applyAdrpAdd(const OptimizationHint &hint) {
-  uint32_t ins1 = read32le(buf + hint.offset0);
-  uint32_t ins2 = read32le(buf + hint.offset0 + hint.delta[0]);
+void OptimizationHintContext::applyAdrpAdd(uint64_t offset1, uint64_t offset2) {
+  uint32_t ins1 = read32le(buf + offset1);
+  uint32_t ins2 = read32le(buf + offset2);
   Adrp adrp;
-  if (!parseAdrp(ins1, adrp))
-    return;
   Add add;
-  if (!parseAdd(ins2, add))
+  if (!parseAdrp(ins1, adrp) || !parseAdd(ins2, add))
     return;
   if (adrp.destRegister != add.srcRegister)
     return;
 
-  Optional<PerformedReloc> rel1 = findPrimaryReloc(hint.offset0);
-  Optional<PerformedReloc> rel2 = findReloc(hint.offset0 + hint.delta[0]);
-  if (!rel1 || !rel2)
-    return;
-  if (rel1->referentVA != rel2->referentVA)
-    return;
-  int64_t delta = rel1->referentVA - rel1->rel.offset - isec->getVA();
+  uint64_t addr1 = isec->getVA() + offset1;
+  uint64_t referent = pageBits(addr1) + adrp.addend + add.addend;
+  int64_t delta = referent - addr1;
   if (!isValidAdrOffset(delta))
     return;
 
-  writeAdr(buf + hint.offset0, add.destRegister, delta);
-  writeNop(buf + hint.offset0 + hint.delta[0]);
+  writeAdr(buf + offset1, add.destRegister, delta);
+  writeNop(buf + offset2);
 }
 
 // Transforms two adrp instructions into a single adrp if their referent
 // addresses are located on the same 4096 byte page.
 //
 //   adrp xN, _foo@PAGE
 //   adrp xN, _bar@PAGE
 // ->
 //   adrp xN, _foo@PAGE
 //   nop
-void OptimizationHintContext::applyAdrpAdrp(const OptimizationHint &hint) {
-  uint32_t ins1 = read32le(buf + hint.offset0);
-  uint32_t ins2 = read32le(buf + hint.offset0 + hint.delta[0]);
+void OptimizationHintContext::applyAdrpAdrp(uint64_t offset1,
+                                            uint64_t offset2) {
+  uint32_t ins1 = read32le(buf + offset1);
+  uint32_t ins2 = read32le(buf + offset2);
   Adrp adrp1, adrp2;
   if (!parseAdrp(ins1, adrp1) || !parseAdrp(ins2, adrp2))
     return;
   if (adrp1.destRegister != adrp2.destRegister)
     return;
 
-  Optional<PerformedReloc> rel1 = findPrimaryReloc(hint.offset0);
-  Optional<PerformedReloc> rel2 = findReloc(hint.offset0 + hint.delta[0]);
-  if (!rel1 || !rel2)
-    return;
-  if ((rel1->referentVA & ~0xfffULL) != (rel2->referentVA & ~0xfffULL))
+  uint64_t page1 = pageBits(offset1 + isec->getVA()) + adrp1.addend;
+  uint64_t page2 = pageBits(offset2 + isec->getVA()) + adrp2.addend;
+  if (page1 != page2)
     return;
 
-  writeNop(buf + hint.offset0 + hint.delta[0]);
+  writeNop(buf + offset2);
 }
 
 // Transforms a pair of adrp+ldr (immediate) instructions into an ldr (literal)
 // load from a PC-relative address if it is 4-byte aligned and within +/- 1 MiB,
 // as ldr can encode a signed 19-bit offset that gets multiplied by 4.
 //
 //   adrp xN, _foo@PAGE
 //   ldr  xM, [xN, _foo@PAGEOFF]
 // ->
 //   nop
 //   ldr  xM, _foo
-void OptimizationHintContext::applyAdrpLdr(const OptimizationHint &hint) {
-  uint32_t ins1 = read32le(buf + hint.offset0);
-  uint32_t ins2 = read32le(buf + hint.offset0 + hint.delta[0]);
+void OptimizationHintContext::applyAdrpLdr(uint64_t offset1, uint64_t offset2) {
+  uint32_t ins1 = read32le(buf + offset1);
+  uint32_t ins2 = read32le(buf + offset2);
   Adrp adrp;
-  if (!parseAdrp(ins1, adrp))
-    return;
   Ldr ldr;
-  if (!parseLdr(ins2, ldr))
+  if (!parseAdrp(ins1, adrp) || !parseLdr(ins2, ldr))
     return;
   if (adrp.destRegister != ldr.baseRegister)
     return;
 
-  Optional<PerformedReloc> rel1 = findPrimaryReloc(hint.offset0);
-  Optional<PerformedReloc> rel2 = findReloc(hint.offset0 + hint.delta[0]);
-  if (!rel1 || !rel2)
-    return;
-  if (ldr.offset != static_cast<int64_t>(rel1->referentVA & 0xfff))
-    return;
-  ldr.offset = rel1->referentVA - rel2->rel.offset - isec->getVA();
+  uint64_t addr1 = isec->getVA() + offset1;
+  uint64_t addr2 = isec->getVA() + offset2;
+  uint64_t referent = pageBits(addr1) + adrp.addend + ldr.offset;
+  ldr.offset = referent - addr2;
   if (!isLiteralLdrEligible(ldr))
     return;
 
-  writeNop(buf + hint.offset0);
-  writeLiteralLdr(buf + hint.offset0 + hint.delta[0], ldr);
+  writeNop(buf + offset1);
+  writeLiteralLdr(buf + offset2, ldr);
 }
 
 // GOT loads are emitted by the compiler as a pair of adrp and ldr instructions,
 // but they may be changed to adrp+add by relaxGotLoad(). This hint performs
 // the AdrpLdr or AdrpAdd transformation depending on whether it was relaxed.
-void OptimizationHintContext::applyAdrpLdrGot(const OptimizationHint &hint) {
-  uint32_t ins2 = read32le(buf + hint.offset0 + hint.delta[0]);
+void OptimizationHintContext::applyAdrpLdrGot(uint64_t offset1,
+                                              uint64_t offset2) {
+  uint32_t ins2 = read32le(buf + offset2);
   Add add;
   Ldr ldr;
   if (parseAdd(ins2, add))
-    applyAdrpAdd(hint);
+    applyAdrpAdd(offset1, offset2);
   else if (parseLdr(ins2, ldr))
-    applyAdrpLdr(hint);
+    applyAdrpLdr(offset1, offset2);
 }
 
 // Optimizes an adrp+add+ldr sequence used for loading from a local symbol's
 // address by loading directly if it's close enough, or to an adrp(p)+ldr
 // sequence if it's not.
 //
 //   adrp x0, _foo@PAGE
 //   add  x1, x0, _foo@PAGEOFF
 //   ldr  x2, [x1, #off]
-void OptimizationHintContext::applyAdrpAddLdr(const OptimizationHint &hint) {
-  uint32_t ins1 = read32le(buf + hint.offset0);
+void OptimizationHintContext::applyAdrpAddLdr(uint64_t offset1,
+                                              uint64_t offset2,
+                                              uint64_t offset3) {
+  uint32_t ins1 = read32le(buf + offset1);
   Adrp adrp;
   if (!parseAdrp(ins1, adrp))
     return;
-  uint32_t ins2 = read32le(buf + hint.offset0 + hint.delta[0]);
+  uint32_t ins2 = read32le(buf + offset2);
   Add add;
   if (!parseAdd(ins2, add))
     return;
-  uint32_t ins3 = read32le(buf + hint.offset0 + hint.delta[1]);
+  uint32_t ins3 = read32le(buf + offset3);
   Ldr ldr;
   if (!parseLdr(ins3, ldr))
     return;
-
-  Optional<PerformedReloc> rel1 = findPrimaryReloc(hint.offset0);
-  Optional<PerformedReloc> rel2 = findReloc(hint.offset0 + hint.delta[0]);
-  if (!rel1 || !rel2)
-    return;
-
   if (adrp.destRegister != add.srcRegister)
     return;
   if (add.destRegister != ldr.baseRegister)
     return;
 
   // Load from the target address directly.
   //   nop
   //   nop
   //   ldr x2, [_foo + #off]
-  uint64_t rel3VA = hint.offset0 + hint.delta[1] + isec->getVA();
+  uint64_t addr1 = isec->getVA() + offset1;
+  uint64_t addr3 = isec->getVA() + offset3;
+  uint64_t referent = pageBits(addr1) + adrp.addend + add.addend;
   Ldr literalLdr = ldr;
-  literalLdr.offset += rel1->referentVA - rel3VA;
+  literalLdr.offset += referent - addr3;
   if (isLiteralLdrEligible(literalLdr)) {
-    writeNop(buf + hint.offset0);
-    writeNop(buf + hint.offset0 + hint.delta[0]);
-    writeLiteralLdr(buf + hint.offset0 + hint.delta[1], literalLdr);
+    writeNop(buf + offset1);
+    writeNop(buf + offset2);
+    writeLiteralLdr(buf + offset3, literalLdr);
     return;
   }
 
   // Load the target address into a register and load from there indirectly.
   //   adr x1, _foo
   //   nop
   //   ldr x2, [x1, #off]
-  int64_t adrOffset = rel1->referentVA - rel1->rel.offset - isec->getVA();
+  int64_t adrOffset = referent - addr1;
   if (isValidAdrOffset(adrOffset)) {
-    writeAdr(buf + hint.offset0, ldr.baseRegister, adrOffset);
+    writeAdr(buf + offset1, ldr.baseRegister, adrOffset);
     // Note: ld64 moves the offset into the adr instruction for AdrpAddLdr, but
     // not for AdrpLdrGotLdr. Its effect is the same either way.
-    writeNop(buf + hint.offset0 + hint.delta[0]);
+    writeNop(buf + offset2);
     return;
   }
 
   // Move the target's page offset into the ldr's immediate offset.
   //   adrp x0, _foo@PAGE
   //   nop
   //   ldr x2, [x0, _foo@PAGEOFF + #off]
   Ldr immediateLdr = ldr;
   immediateLdr.baseRegister = adrp.destRegister;
   immediateLdr.offset += add.addend;
   if (isImmediateLdrEligible(immediateLdr)) {
-    writeNop(buf + hint.offset0 + hint.delta[0]);
-    writeImmediateLdr(buf + hint.offset0 + hint.delta[1], immediateLdr);
+    writeNop(buf + offset2);
+    writeImmediateLdr(buf + offset3, immediateLdr);
     return;
   }
 }
 
 // Relaxes a GOT-indirect load.
 // If the referenced symbol is external and its GOT entry is within +/- 1 MiB,
 // the GOT entry can be loaded with a single literal ldr instruction.
 // If the referenced symbol is local and thus has been relaxed to adrp+add+ldr,
 // we perform the AdrpAddLdr transformation.
-void OptimizationHintContext::applyAdrpLdrGotLdr(const OptimizationHint &hint) {
-  uint32_t ins2 = read32le(buf + hint.offset0 + hint.delta[0]);
+void OptimizationHintContext::applyAdrpLdrGotLdr(uint64_t offset1,
+                                                 uint64_t offset2,
+                                                 uint64_t offset3) {
+  uint32_t ins2 = read32le(buf + offset2);
   Add add;
   Ldr ldr2;
 
   if (parseAdd(ins2, add)) {
-    applyAdrpAddLdr(hint);
+    applyAdrpAddLdr(offset1, offset2, offset3);
   } else if (parseLdr(ins2, ldr2)) {
     // adrp x1, _foo@GOTPAGE
     // ldr  x2, [x1, _foo@GOTPAGEOFF]
     // ldr  x3, [x2, #off]
 
-    uint32_t ins1 = read32le(buf + hint.offset0);
+    uint32_t ins1 = read32le(buf + offset1);
     Adrp adrp;
     if (!parseAdrp(ins1, adrp))
       return;
-    uint32_t ins3 = read32le(buf + hint.offset0 + hint.delta[1]);
+    uint32_t ins3 = read32le(buf + offset3);
     Ldr ldr3;
     if (!parseLdr(ins3, ldr3))
       return;
 
-    Optional<PerformedReloc> rel1 = findPrimaryReloc(hint.offset0);
-    Optional<PerformedReloc> rel2 = findReloc(hint.offset0 + hint.delta[0]);
-    if (!rel1 || !rel2)
-      return;
-
     if (ldr2.baseRegister != adrp.destRegister)
       return;
     if (ldr3.baseRegister != ldr2.destRegister)
       return;
     // Loads from the GOT must be pointer sized.
     if (ldr2.p2Size != 3 || ldr2.isFloat)
       return;
 
+    uint64_t addr1 = isec->getVA() + offset1;
+    uint64_t addr2 = isec->getVA() + offset2;
+    uint64_t referent = pageBits(addr1) + adrp.addend + ldr2.offset;
     // Load the GOT entry's address directly.
     //   nop
     //   ldr x2, _foo@GOTPAGE + _foo@GOTPAGEOFF
     //   ldr x3, [x2, #off]
     Ldr literalLdr = ldr2;
-    literalLdr.offset = rel1->referentVA - rel2->rel.offset - isec->getVA();
+    literalLdr.offset = referent - addr2;
     if (isLiteralLdrEligible(literalLdr)) {
-      writeNop(buf + hint.offset0);
-      writeLiteralLdr(buf + hint.offset0 + hint.delta[0], literalLdr);
+      writeNop(buf + offset1);
+      writeLiteralLdr(buf + offset2, literalLdr);
     }
   }
 }
 
-void ARM64::applyOptimizationHints(uint8_t *buf, const ConcatInputSection *isec,
-                                   ArrayRef<uint64_t> relocTargets) const {
+void ARM64::applyOptimizationHints(uint8_t *buf,
+                                   const ConcatInputSection *isec) const {
   assert(isec);
-  assert(relocTargets.size() == isec->relocs.size());
 
   // Note: Some of these optimizations might not be valid when shared regions
   // are in use. Will need to revisit this if splitSegInfo is added.
 
-  OptimizationHintContext ctx1(buf, isec, relocTargets);
+  OptimizationHintContext ctx(buf, isec);
   for (const OptimizationHint &hint : isec->optimizationHints) {
     switch (hint.type) {
     case LOH_ARM64_ADRP_ADRP:
       // This is done in another pass because the other optimization hints
       // might cause its targets to be turned into NOPs.
       break;
     case LOH_ARM64_ADRP_LDR:
-      ctx1.applyAdrpLdr(hint);
+      ctx.applyAdrpLdr(hint.offset0, hint.offset0 + hint.delta[0]);
       break;
     case LOH_ARM64_ADRP_ADD_LDR:
-      ctx1.applyAdrpAddLdr(hint);
+      ctx.applyAdrpAddLdr(hint.offset0, hint.offset0 + hint.delta[0],
+                          hint.offset0 + hint.delta[1]);
       break;
     case LOH_ARM64_ADRP_LDR_GOT_LDR:
-      ctx1.applyAdrpLdrGotLdr(hint);
+      ctx.applyAdrpLdrGotLdr(hint.offset0, hint.offset0 + hint.delta[0],
+                             hint.offset0 + hint.delta[1]);
       break;
     case LOH_ARM64_ADRP_ADD_STR:
     case LOH_ARM64_ADRP_LDR_GOT_STR:
       // TODO: Implement these
       break;
     case LOH_ARM64_ADRP_ADD:
-      ctx1.applyAdrpAdd(hint);
+      ctx.applyAdrpAdd(hint.offset0, hint.offset0 + hint.delta[0]);
       break;
     case LOH_ARM64_ADRP_LDR_GOT:
-      ctx1.applyAdrpLdrGot(hint);
+      ctx.applyAdrpLdrGot(hint.offset0, hint.offset0 + hint.delta[0]);
       break;
     }
   }
 
-  OptimizationHintContext ctx2(buf, isec, relocTargets);
   for (const OptimizationHint &hint : isec->optimizationHints)
     if (hint.type == LOH_ARM64_ADRP_ADRP)
-      ctx2.applyAdrpAdrp(hint);
+      ctx.applyAdrpAdrp(hint.offset0, hint.offset0 + hint.delta[0]);
 }
 
 TargetInfo *macho::createARM64TargetInfo() {
   static ARM64 t;
   return &t;
 }

lld/MachO/InputSection.cpp

 void ConcatInputSection::writeTo(uint8_t *buf) {
   assert(!shouldOmitFromOutput());
 
   if (getFileSize() == 0)
     return;
 
   memcpy(buf, data.data(), data.size());
 
-  std::vector<uint64_t> relocTargets;
-  if (!optimizationHints.empty())
-    relocTargets.reserve(relocs.size());
-
   for (size_t i = 0; i < relocs.size(); i++) {
     const Reloc &r = relocs[i];
     uint8_t *loc = buf + r.offset;
     uint64_t referentVA = 0;
     if (target->hasAttr(r.type, RelocAttrBits::SUBTRAHEND)) {
       const Symbol *fromSym = r.referent.get<Symbol *>();
       const Reloc &minuend = relocs[++i];
       uint64_t minuendVA;
if (target->hasAttr(r.type, RelocAttrBits::SUBTRAHEND)) {
         if (isa<Defined>(referentSym))
           referentVA -= firstTLVDataSection->addr;
       }
     } else if (auto *referentIsec = r.referent.dyn_cast<InputSection *>()) {
       assert(!::shouldOmitFromOutput(referentIsec));
       referentVA = referentIsec->getVA(r.addend);
     }
     target->relocateOne(loc, r, referentVA, getVA() + r.offset);
-
-    if (!optimizationHints.empty())
-      relocTargets.push_back(referentVA);
   }
 
-  if (!optimizationHints.empty())
-    target->applyOptimizationHints(buf, this, relocTargets);
+  target->applyOptimizationHints(buf, this);
 }
 
 ConcatInputSection *macho::makeSyntheticInputSection(StringRef segName,
                                                      StringRef sectName,
                                                      uint32_t flags,
                                                      ArrayRef<uint8_t> data,
                                                      uint32_t align) {
   Section &section =

lld/MachO/Target.h

public:
   // For now, handleDtraceReloc only implements -no_dtrace_dof, and ensures
   // that the linking would not fail even when there are user-provided dtrace
   // symbols. However, unlike ld64, lld currently does not emit __dof sections.
   virtual void handleDtraceReloc(const Symbol *sym, const Reloc &r,
                                  uint8_t *loc) const {
     llvm_unreachable("Unsupported architecture for dtrace symbols");
   }
 
-
-  virtual void applyOptimizationHints(uint8_t *buf, const ConcatInputSection *,
-                                      llvm::ArrayRef<uint64_t>) const {};
+  virtual void applyOptimizationHints(uint8_t *buf,
+                                      const ConcatInputSection *) const {};
 
   uint32_t magic;
   llvm::MachO::CPUType cpuType;
   uint32_t cpuSubtype;
 
   uint64_t pageZeroSize;
   size_t headerSize;
   size_t stubSize;

lld/test/MachO/loh-adrp-add.s

 # REQUIRES: aarch64
 
 # RUN: llvm-mc -filetype=obj -triple=arm64-apple-darwin %s -o %t.o
 # RUN: %lld -arch arm64 %t.o -o %t
 # RUN: llvm-objdump -d --macho %t | FileCheck %s
 
 # CHECK-LABEL: _main:
 ## Out of range, before
 # CHECK-NEXT: adrp x0
 # CHECK-NEXT: add x0, x0
 ## In range, before
 # CHECK-NEXT: adr x1
 # CHECK-NEXT: nop
 ## Registers don't match (invalid input)
 # CHECK-NEXT: adrp x2
 # CHECK-NEXT: add x0
-## Targets don't match (invalid input)
-# CHECK-NEXT: adrp x3
-# CHECK-NEXT: add x3
 ## Not an adrp instruction (invalid input)
 # CHECK-NEXT: nop
 # CHECK-NEXT: add x4
 ## In range, after
 # CHECK-NEXT: adr x5
 # CHECK-NEXT: nop
 ## In range, add's destination register is not the same as its source
 # CHECK-NEXT: adr x7

 L3:
   adrp x1, _before_near@PAGE
 L4:
   add  x1, x1, _before_near@PAGEOFF
 L5:
   adrp x2, _before_near@PAGE
 L6:
   add  x0, x0, _before_near@PAGEOFF
-L7:
-  adrp x3, _before_near@PAGE
-L8:
-  add  x3, x3, _after_near@PAGEOFF
 L9:
   nop
 L10:
   add  x4, x4, _after_near@PAGEOFF
 L11:
   adrp x5, _after_near@PAGE
 L12:
   add  x5, x5, _after_near@PAGEOFF
_after_near:
   .space 1048576
 
 _after_far:
   nop
 
 .loh AdrpAdd L1, L2
 .loh AdrpAdd L3, L4
 .loh AdrpAdd L5, L6
-.loh AdrpAdd L7, L8
 .loh AdrpAdd L9, L10
 .loh AdrpAdd L11, L12
 .loh AdrpAdd L13, L14
 .loh AdrpAdd L15, L18
 .loh AdrpAdd L16, L17

lld/test/MachO/loh-adrp-ldr.s

 # CHECK-NEXT: ldr x1, #-20
 
 ## Registers don't match (invalid input)
 L5:  adrp  x2, _before_near@PAGE
 L6:  ldr   x3, [x3, _before_near@PAGEOFF]
 # CHECK-NEXT: adrp x2
 # CHECK-NEXT: ldr x3
 
-## Targets don't match (invalid input)
-L7:  adrp  x4, _before_near@PAGE
-L8:  ldr   x4, [x4, _after_near@PAGEOFF]
-# CHECK-NEXT: adrp x4
-# CHECK-NEXT: ldr x4
-
 ## Not an adrp instruction
 L9:  udf   0
 L10: ldr   x5, [x5, _after_near@PAGEOFF]
 # CHECK-NEXT: udf
 # CHECK-NEXT: ldr x5
 
 ## Not an ldr with an immediate offset
 L11: adrp  x6, _after_near@PAGE

 .space 1048576
 
 _after_far:
   .quad 0
 
 .loh AdrpLdr L1, L2
 .loh AdrpLdr L3, L4
 .loh AdrpLdr L5, L6
-.loh AdrpLdr L7, L8
 .loh AdrpLdr L9, L10
 .loh AdrpLdr L11, L12
 .loh AdrpLdr L15, L16
 .loh AdrpLdr L17, L18
 .loh AdrpLdr L19, L20
 .loh AdrpLdr L21, L22
 .loh AdrpLdr L23, L24
 .loh AdrpLdr L25, L26
 .loh AdrpLdr L27, L28
 .loh AdrpLdr L29, L30
 .loh AdrpLdr L31, L32
 .loh AdrpLdr L33, L34