This is an archive of the discontinued LLVM Phabricator instance.

llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
6	The cost of bonus instructions depends on the target triple and processor (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/Utils/SimplifyCFG.cpp#L3676). Certain processors have high costs than others, causing the branch not to be folded. For example, if I replace the target triple of this lit test with `x86_64` and remove the target processor. This lit test still passes since `x86_64` behaves similarly as amdgcn gfx906. However, if I replace the target triple with `x86`, this lit test will fail since the branches are never folded even without my patch. How about I make the IR in this lit test target independent, and use `-mtriple` to test a few triples which are relevant to the test?

yaxunl marked an inline comment as done.Sep 14 2022, 2:15 PM

yaxunl added inline comments.

llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
6	The cost of bonus instructions depends on the target triple and processor (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/Utils/SimplifyCFG.cpp#L3676). Certain processors have high costs than others, causing the branch not to be folded. For example, if I replace the target triple of this lit test with `x86_64` and remove the target processor. This lit test still passes since `x86_64` behaves similarly as amdgcn gfx906. However, if I replace the target triple with `x86`, this lit test will fail since the branches are never folded even without my patch. How about I make the IR in this lit test target independent, and use `-mtriple` to test a few triples which are relevant to the test? The drawback of the above approach is that it requires multiple registered targets, which can make it less tested on bots. Another way is to use the existing option for bonus insts threshold. Increase it so that the lit test behaves the same on all targets. Then this lit test will be target independent.

make the test target independent

Harbormaster completed remote builds in B186885: Diff 460439.Sep 15 2022, 9:20 AM

LGTM, thanks!

llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
2	please use the newpm syntax: `-passes=simplifycfg`
6	Certain processors have high costs than others, causing the branch not to be folded. Right,
10	nit: drop unneeded `zero ext` `unnamed_addr align 2`
56	nit: `basi -> basic`
97	nit: of 1.

This revision is now accepted and ready to land.Sep 15 2022, 12:51 PM

yaxunl marked 5 inline comments as done.Sep 17 2022, 2:55 PM

yaxunl added inline comments.

llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll
2	will do
10	will do
56	will do
97	will do

This revision was landed with ongoing or failed builds.Sep 17 2022, 6:19 PM

Closed by commit rG97b5736975f3: [SimplifyCFG] add a test for branch folding multiple BB (authored by yaxunl). · Explain Why

This revision was automatically updated to reflect the committed changes.

yaxunl marked 4 inline comments as done.

yaxunl added a commit: rG97b5736975f3: [SimplifyCFG] add a test for branch folding multiple BB.

Revision Contents

Path

Size

llvm/

test/

Transforms/

SimplifyCFG/

branch-fold-multiple.ll

151 lines

Diff 460439

llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll

This file was added.

				; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
				; RUN: opt %s -S -o - -simplifycfg \| FileCheck %s
				fhahnUnsubmitted Done Reply Inline Actions please use the newpm syntax: `-passes=simplifycfg` fhahn: please use the newpm syntax: `-passes=simplifycfg`
				yaxunlAuthorUnsubmitted Done Reply Inline Actions will do yaxunl: will do

				%struct.S = type { [4 x i32] }

				; Check the second, third, and fourth basic blocks are folded into
				fhahnUnsubmitted Done Reply Inline Actions Does this need to be target specific? We should definitely have at least some target-independent tests here. fhahn: Does this need to be target specific? We should definitely have at least some target…
				yaxunlAuthorUnsubmitted Done Reply Inline Actions The cost of bonus instructions depends on the target triple and processor (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/Utils/SimplifyCFG.cpp#L3676). Certain processors have high costs than others, causing the branch not to be folded. For example, if I replace the target triple of this lit test with `x86_64` and remove the target processor. This lit test still passes since `x86_64` behaves similarly as amdgcn gfx906. However, if I replace the target triple with `x86`, this lit test will fail since the branches are never folded even without my patch. How about I make the IR in this lit test target independent, and use `-mtriple` to test a few triples which are relevant to the test? yaxunl: The cost of bonus instructions depends on the target triple and processor (https://github.
				yaxunlAuthorUnsubmitted Done Reply Inline Actions The cost of bonus instructions depends on the target triple and processor (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/Utils/SimplifyCFG.cpp#L3676). Certain processors have high costs than others, causing the branch not to be folded. For example, if I replace the target triple of this lit test with `x86_64` and remove the target processor. This lit test still passes since `x86_64` behaves similarly as amdgcn gfx906. However, if I replace the target triple with `x86`, this lit test will fail since the branches are never folded even without my patch. How about I make the IR in this lit test target independent, and use `-mtriple` to test a few triples which are relevant to the test? The drawback of the above approach is that it requires multiple registered targets, which can make it less tested on bots. Another way is to use the existing option for bonus insts threshold. Increase it so that the lit test behaves the same on all targets. Then this lit test will be target independent. yaxunl: > The cost of bonus instructions depends on the target triple and processor (https://github.
				fhahnUnsubmitted Done Reply Inline Actions Certain processors have high costs than others, causing the branch not to be folded. Right, fhahn: > Certain processors have high costs than others, causing the branch not to be folded. Right,
				; the first basic block since each has one bonus intruction, which
				; does not exceed the default bouns instruction threshold 1.

				define zeroext i1 @test1(i32 %0, i32 %1, i32 %2, i32 %3) unnamed_addr align 2 {
				fhahnUnsubmitted Done Reply Inline Actions nit: drop unneeded `zero ext` `unnamed_addr align 2` fhahn: nit: drop unneeded `zero ext` `unnamed_addr align 2`
				yaxunlAuthorUnsubmitted Done Reply Inline Actions will do yaxunl: will do
				; CHECK-LABEL: @test1(
				; CHECK-NEXT: entry:
				; CHECK-NEXT: [[MUL0:%.]] = mul i32 [[TMP0:%.]], [[TMP0]]
				; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[MUL0]], 0
				; CHECK-NEXT: [[MUL1:%.]] = mul i32 [[TMP1:%.]], [[TMP1]]
				; CHECK-NEXT: [[CMP2_1:%.*]] = icmp sgt i32 [[MUL1]], 0
				; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP2]], i1 true, i1 [[CMP2_1]]
				; CHECK-NEXT: [[MUL2:%.]] = mul i32 [[TMP2:%.]], [[TMP2]]
				; CHECK-NEXT: [[CMP2_2:%.*]] = icmp sgt i32 [[MUL2]], 0
				; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP2_2]]
				; CHECK-NEXT: [[MUL3:%.]] = mul i32 [[TMP3:%.]], [[TMP3]]
				; CHECK-NEXT: [[CMP2_3:%.*]] = icmp sgt i32 [[MUL3]], 0
				; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[CMP2_3]]
				; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[OR_COND2]], i1 false, i1 true
				; CHECK-NEXT: ret i1 [[SPEC_SELECT]]
				;
				entry:
				%mul0 = mul i32 %0, %0
				%cmp2 = icmp sgt i32 %mul0, 0
				br i1 %cmp2, label %cleanup, label %for.cond

				for.cond:
				%mul1 = mul i32 %1, %1
				%cmp2.1 = icmp sgt i32 %mul1, 0
				br i1 %cmp2.1, label %cleanup, label %for.cond.1

				for.cond.1:
				%mul2 = mul i32 %2, %2
				%cmp2.2 = icmp sgt i32 %mul2, 0
				br i1 %cmp2.2, label %cleanup, label %for.cond.2

				for.cond.2:
				%mul3 = mul i32 %3, %3
				%cmp2.3 = icmp sgt i32 %mul3, 0
				br i1 %cmp2.3, label %cleanup, label %for.cond.3

				for.cond.3:
				br label %cleanup

				cleanup:
				%cmp = phi i1 [ false, %entry ], [ false, %for.cond ], [ false, %for.cond.1 ], [ false, %for.cond.2 ], [ true, %for.cond.3 ]
				ret i1 %cmp
				}

				; Check the second, third, and forth basic blocks are folded into the first
				; basi block since each has no bonus instruction.
				fhahnUnsubmitted Done Reply Inline Actions nit: `basi -> basic` fhahn: nit: `basi -> basic`
				yaxunlAuthorUnsubmitted Done Reply Inline Actions will do yaxunl: will do

				define zeroext i1 @test2(i32 %0, i32 %1, i32 %2, i32 %3) unnamed_addr align 2 {
				; CHECK-LABEL: @test2(
				; CHECK-NEXT: entry:
				; CHECK-NEXT: [[CMP2:%.]] = icmp sgt i32 [[TMP0:%.]], 0
				; CHECK-NEXT: [[CMP2_1:%.]] = icmp sgt i32 [[TMP1:%.]], 0
				; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP2]], i1 true, i1 [[CMP2_1]]
				; CHECK-NEXT: [[CMP2_2:%.]] = icmp sgt i32 [[TMP2:%.]], 0
				; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP2_2]]
				; CHECK-NEXT: [[CMP2_3:%.]] = icmp sgt i32 [[TMP3:%.]], 0
				; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[CMP2_3]]
				; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[OR_COND2]], i1 false, i1 true
				; CHECK-NEXT: ret i1 [[SPEC_SELECT]]
				;
				entry:
				%cmp2 = icmp sgt i32 %0, 0
				br i1 %cmp2, label %cleanup, label %for.cond

				for.cond:
				%cmp2.1 = icmp sgt i32 %1, 0
				br i1 %cmp2.1, label %cleanup, label %for.cond.1

				for.cond.1:
				%cmp2.2 = icmp sgt i32 %2, 0
				br i1 %cmp2.2, label %cleanup, label %for.cond.2

				for.cond.2:
				%cmp2.3 = icmp sgt i32 %3, 0
				br i1 %cmp2.3, label %cleanup, label %for.cond.3

				for.cond.3:
				br label %cleanup

				cleanup:
				%cmp = phi i1 [ false, %entry ], [ false, %for.cond ], [ false, %for.cond.1 ], [ false, %for.cond.2 ], [ true, %for.cond.3 ]
				ret i1 %cmp
				}

				; Check the second basic block is not folded into the first basic block
				; since it has three bonus instructions, which exceeds the default bonus
				; instruction threshold 1. The third and fourth basic blocks are folded
				fhahnUnsubmitted Done Reply Inline Actions nit: of 1. fhahn: nit: of 1.
				yaxunlAuthorUnsubmitted Done Reply Inline Actions will do yaxunl: will do
				; into the second basic block since they do not have bonus instruction.

				define zeroext i1 @test3(i32 %0, i32 %1, i32 %2, i32 %3) unnamed_addr align 2 {
				; CHECK-LABEL: @test3(
				; CHECK-NEXT: entry:
				; CHECK-NEXT: [[CMP2:%.]] = icmp sgt i32 [[TMP0:%.]], 0
				; CHECK-NEXT: br i1 [[CMP2]], label [[CLEANUP:%.]], label [[FOR_COND:%.]]
				; CHECK: for.cond:
				; CHECK-NEXT: [[MUL1:%.]] = mul i32 [[TMP0]], [[TMP1:%.]]
				; CHECK-NEXT: [[MUL2:%.]] = mul i32 [[MUL1]], [[TMP2:%.]]
				; CHECK-NEXT: [[MUL3:%.]] = mul i32 [[MUL2]], [[TMP3:%.]]
				; CHECK-NEXT: [[MUL4:%.*]] = mul i32 [[MUL3]], [[TMP3]]
				; CHECK-NEXT: [[MUL5:%.*]] = mul i32 [[MUL4]], [[TMP3]]
				; CHECK-NEXT: [[MUL6:%.*]] = mul i32 [[MUL5]], [[TMP3]]
				; CHECK-NEXT: [[CMP2_1:%.*]] = icmp sgt i32 [[MUL5]], 0
				; CHECK-NEXT: [[CMP2_2:%.*]] = icmp sgt i32 [[TMP2]], 0
				; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP2_1]], i1 true, i1 [[CMP2_2]]
				; CHECK-NEXT: [[CMP2_3:%.*]] = icmp sgt i32 [[TMP3]], 0
				; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP2_3]]
				; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[OR_COND1]], i1 false, i1 true
				; CHECK-NEXT: br label [[CLEANUP]]
				; CHECK: cleanup:
				; CHECK-NEXT: [[CMP:%.]] = phi i1 [ false, [[ENTRY:%.]] ], [ [[SPEC_SELECT]], [[FOR_COND]] ]
				; CHECK-NEXT: ret i1 [[CMP]]
				;
				entry:
				%cmp2 = icmp sgt i32 %0, 0
				br i1 %cmp2, label %cleanup, label %for.cond

				for.cond:
				%mul1 = mul i32 %0, %1
				%mul2 = mul i32 %mul1, %2
				%mul3 = mul i32 %mul2, %3
				%mul4 = mul i32 %mul3, %3
				%mul5 = mul i32 %mul4, %3
				%mul6 = mul i32 %mul5, %3
				%cmp2.1 = icmp sgt i32 %mul5, 0
				br i1 %cmp2.1, label %cleanup, label %for.cond.1

				for.cond.1:
				%cmp2.2 = icmp sgt i32 %2, 0
				br i1 %cmp2.2, label %cleanup, label %for.cond.2

				for.cond.2:
				%cmp2.3 = icmp sgt i32 %3, 0
				br i1 %cmp2.3, label %cleanup, label %for.cond.3

				for.cond.3:
				br label %cleanup

				cleanup:
				%cmp = phi i1 [ false, %entry ], [ false, %for.cond ], [ false, %for.cond.1 ], [ false, %for.cond.2 ], [ true, %for.cond.3 ]
				ret i1 %cmp
				}

This is an archive of the discontinued LLVM Phabricator instance.

[SimplifyCFG] add a test for branch folding multiple BBClosedPublic

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Diff 460439

llvm/test/Transforms/SimplifyCFG/branch-fold-multiple.ll

[SimplifyCFG] add a test for branch folding multiple BB
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