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[tests] precommit tests for D132658
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Authored by Allen on Aug 28 2022, 8:26 PM.

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rGeb438c80dfc4: [tests] precommit tests for D132658

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Unit TestsFailed

	Time	Test
	60,030 ms	x64 debian > MLIR.Examples/standalone::test.toy
	60,030 ms	x64 debian > libFuzzer.libFuzzer::fuzzer-leak.test

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Allen created this revision.Aug 28 2022, 8:26 PM

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Allen mentioned this in D132658: [InstCombine] Distributive or+mul with const operand.Aug 28 2022, 8:32 PM

It is better to have a case test the haveNoCommonBitsSet(X, C1, DL, &AC, &I, &DT) with context or assume like:

define i32 @src(i32 %a) {
  %combits = and i32 %a , 3
  %nocombits = icmp eq i32 %combits, 0
  call void @llvm.assume(i1 %nocombits)

  %add = or i32 %a, 3
  %mul = mul i32 %add, 5
  ret i32 %mul
}

declare void @llvm.assume(i1)

Add a new case PR57278_mul_assume

In D132820#3754532, @bcl5980 wrote:
It is better to have a case test the haveNoCommonBitsSet(X, C1, DL, &AC, &I, &DT) with context or assume like:
define i32 @src(i32 %a) {
  %combits = and i32 %a , 3
  %nocombits = icmp eq i32 %combits, 0
  call void @llvm.assume(i1 %nocombits)

  %add = or i32 %a, 3
  %mul = mul i32 %add, 5
  ret i32 %mul
}

declare void @llvm.assume(i1)

Done, thanks

LGTM

This revision is now accepted and ready to land.Aug 28 2022, 10:13 PM

This revision was landed with ongoing or failed builds.Aug 28 2022, 11:20 PM

Closed by commit rGeb438c80dfc4: [tests] precommit tests for D132658 (authored by Allen). · Explain Why

This revision was automatically updated to reflect the committed changes.

Allen added a commit: rGeb438c80dfc4: [tests] precommit tests for D132658.

Harbormaster completed remote builds in B183849: Diff 456247.Aug 28 2022, 11:26 PM

Revision Contents

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llvm/

test/

Transforms/

InstCombine/

mul.ll

104 lines

Diff 456247

llvm/test/Transforms/InstCombine/mul.ll

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	; CHECK-NEXT: [[MUL:%.*]] = add i32 [[TMP1]], 9			; CHECK-NEXT: [[MUL:%.*]] = add i32 [[TMP1]], 9
	; CHECK-NEXT: ret i32 [[MUL]]			; CHECK-NEXT: ret i32 [[MUL]]
	;			;
	%add = add i32 %a, 3			%add = add i32 %a, 3
	%mul = mul nuw i32 %add, 3			%mul = mul nuw i32 %add, 3
	ret i32 %mul			ret i32 %mul
	}			}

				; https://alive2.llvm.org/ce/z/jJ8rZd
				define i32 @PR57278_shl(i32 %a) {
				; CHECK-LABEL: @PR57278_shl(
				; CHECK-NEXT: [[SHL:%.]] = shl nsw i32 [[A:%.]], 2
				; CHECK-NEXT: [[ADD:%.*]] = or i32 [[SHL]], 3
				; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[ADD]], 3
				; CHECK-NEXT: ret i32 [[MUL]]
				;
				%shl = shl nsw i32 %a, 2
				%add = or i32 %shl, 3
				%mul = mul nsw i32 %add, 3
				ret i32 %mul
				}

				; Negative test: Have common bits set
				define i32 @PR57278_shl_1(i32 %a) {
				; CHECK-LABEL: @PR57278_shl_1(
				; CHECK-NEXT: [[SHL:%.]] = shl nsw i32 [[A:%.]], 2
				; CHECK-NEXT: [[ADD:%.*]] = or i32 [[SHL]], 4
				; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[ADD]], 3
				; CHECK-NEXT: ret i32 [[MUL]]
				;
				%shl = shl nsw i32 %a, 2
				%add = or i32 %shl, 4
				%mul = mul nsw i32 %add, 3
				ret i32 %mul
				}

				; Keep nuw flag in this change, https://alive2.llvm.org/ce/z/awsQrx
				define i32 @PR57278_mul(i32 %a) {
				; CHECK-LABEL: @PR57278_mul(
				; CHECK-NEXT: [[MUL0:%.]] = mul nuw i32 [[A:%.]], 12
				; CHECK-NEXT: [[ADD:%.*]] = or i32 [[MUL0]], 3
				; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[ADD]], 3
				; CHECK-NEXT: ret i32 [[MUL]]
				;
				%mul0 = mul nuw i32 %a, 12
				%add = or i32 %mul0, 3
				%mul = mul nuw i32 %add, 3
				ret i32 %mul
				}

				; Negative test: Have common bits set
				define i32 @PR57278_mul_1(i32 %a) {
				; CHECK-LABEL: @PR57278_mul_1(
				; CHECK-NEXT: [[MUL0:%.]] = mul nuw i32 [[A:%.]], 12
				; CHECK-NEXT: [[ADD:%.*]] = or i32 [[MUL0]], 4
				; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[ADD]], 3
				; CHECK-NEXT: ret i32 [[MUL]]
				;
				%mul0 = mul nuw i32 %a, 12
				%add = or i32 %mul0, 4
				%mul = mul nuw i32 %add, 3
				ret i32 %mul
				}

				; https://alive2.llvm.org/ce/z/AXKBjK
				define i32 @PR57278_mul_assume(i32 %a) {
				; CHECK-LABEL: @PR57278_mul_assume(
				; CHECK-NEXT: [[COMBITS:%.]] = and i32 [[A:%.]], 3
				; CHECK-NEXT: [[NOCOMBITS:%.*]] = icmp eq i32 [[COMBITS]], 0
				; CHECK-NEXT: call void @llvm.assume(i1 [[NOCOMBITS]])
				; CHECK-NEXT: [[ADD:%.*]] = or i32 [[A]], 3
				; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ADD]], 5
				; CHECK-NEXT: ret i32 [[MUL]]
				;
				%combits = and i32 %a , 3
				%nocombits = icmp eq i32 %combits, 0
				call void @llvm.assume(i1 %nocombits)

				%add = or i32 %a, 3
				%mul = mul i32 %add, 5
				ret i32 %mul
				}

				declare void @llvm.assume(i1)

				; https://alive2.llvm.org/ce/z/XYpv9q
				define <2 x i32> @PR57278_shl_vec(<2 x i32> %v1) {
				; CHECK-LABEL: @PR57278_shl_vec(
				; CHECK-NEXT: [[SHL:%.]] = shl nuw <2 x i32> [[V1:%.]], <i32 2, i32 3>
				; CHECK-NEXT: [[ADD:%.*]] = or <2 x i32> [[SHL]], <i32 3, i32 3>
				; CHECK-NEXT: [[MUL:%.*]] = mul nuw <2 x i32> [[ADD]], <i32 3, i32 3>
				; CHECK-NEXT: ret <2 x i32> [[MUL]]
				;
				%shl = shl nuw <2 x i32> %v1, <i32 2, i32 3>
				%add = or <2 x i32> %shl, <i32 3, i32 3>
				%mul = mul nuw <2 x i32> %add, <i32 3, i32 3>
				ret <2 x i32> %mul
				}

				define <2 x i32> @PR57278_shl_vec_poison(<2 x i32> %v1) {
				; CHECK-LABEL: @PR57278_shl_vec_poison(
				; CHECK-NEXT: [[SHL:%.]] = shl nuw <2 x i32> [[V1:%.]], <i32 2, i32 poison>
				; CHECK-NEXT: [[ADD:%.*]] = or <2 x i32> [[SHL]], <i32 3, i32 poison>
				; CHECK-NEXT: [[MUL:%.*]] = mul nuw <2 x i32> [[ADD]], <i32 3, i32 poison>
				; CHECK-NEXT: ret <2 x i32> [[MUL]]
				;
				%shl = shl nuw <2 x i32> %v1, <i32 2, i32 poison>
				%add = or <2 x i32> %shl, <i32 3, i32 poison>
				%mul = mul nuw <2 x i32> %add, <i32 3, i32 poison>
				ret <2 x i32> %mul
				}

	define <2 x i1> @test21(<2 x i1> %A, <2 x i1> %B) {			define <2 x i1> @test21(<2 x i1> %A, <2 x i1> %B) {
	; CHECK-LABEL: @test21(			; CHECK-LABEL: @test21(
	; CHECK-NEXT: [[C:%.]] = and <2 x i1> [[A:%.]], [[B:%.*]]			; CHECK-NEXT: [[C:%.]] = and <2 x i1> [[A:%.]], [[B:%.*]]
	; CHECK-NEXT: ret <2 x i1> [[C]]			; CHECK-NEXT: ret <2 x i1> [[C]]
	;			;
	%C = mul <2 x i1> %A, %B			%C = mul <2 x i1> %A, %B
	ret <2 x i1> %C			ret <2 x i1> %C
	}			}
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