[VE] Support inlineasm memory operand

[kaz7]

Summary

Support inline asm memory operand for VE. Add regression tests also.

[efocht]

Looks good.

[kaz7]

Correct errors in buildbot.

llvm/lib/Target/VE/VEAsmPrinter.cpp

public:
   void emitInstruction(const MachineInstr *MI) override;
 
   static const char *getRegisterName(unsigned RegNo) {
     return VEInstPrinter::getRegisterName(RegNo);
   }
   void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &OS);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        const char *ExtraCode, raw_ostream &O) override;
+  bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+                             const char *ExtraCode, raw_ostream &O) override;
 };
 } // end of anonymous namespace
 
 static MCOperand createVEMCOperand(VEMCExpr::VariantKind Kind, MCSymbol *Sym,
                                    MCContext &OutContext) {
   const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym, OutContext);
   const VEMCExpr *expr = VEMCExpr::create(Kind, MCSym, OutContext);
   return MCOperand::createExpr(expr);

 void VEAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                 raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNum);
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
     break;
+  case MachineOperand::MO_Immediate:
+    O << (int)MO.getImm();
+    break;
   default:
     llvm_unreachable("<unknown operand type>");
   }
 }
 
 // PrintAsmOperand - Print out an operand for an inline asm expression.
 bool VEAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                    const char *ExtraCode, raw_ostream &O) {
if (ExtraCode && ExtraCode[0]) {
     }
   }
 
   printOperand(MI, OpNo, O);
 
   return false;
 }
 
+bool VEAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+                                         const char *ExtraCode,
+                                         raw_ostream &O) {
+  if (ExtraCode && ExtraCode[0])
+    return true;  // Unknown modifier
+
+  if (MI->getOperand(OpNo+1).isImm() &&
+      MI->getOperand(OpNo+1).getImm() == 0) {
+    // don't print "+0"
+  } else {
+    printOperand(MI, OpNo+1, O);
+  }
+  if (MI->getOperand(OpNo).isImm() &&
+      MI->getOperand(OpNo).getImm() == 0) {
+    if (MI->getOperand(OpNo+1).isImm() &&
+        MI->getOperand(OpNo+1).getImm() == 0) {
+      O << "0";
+    } else {
+      // don't print "(0)"
+    }
+  } else {
+    O << "(";
+    printOperand(MI, OpNo, O);
+    O << ")";
+  }
+  return false;
+}
+
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmPrinter() {
   RegisterAsmPrinter<VEAsmPrinter> X(getTheVETarget());
 }

llvm/lib/Target/VE/VEISelDAGToDAG.cpp

public:
   // Complex Pattern Selectors.
   bool selectADDRrri(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
   bool selectADDRrii(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
   bool selectADDRzri(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
   bool selectADDRzii(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
   bool selectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
   bool selectADDRzi(SDValue N, SDValue &Base, SDValue &Offset);
 
+  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+  /// inline asm expressions.
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    unsigned ConstraintID,
+                                    std::vector<SDValue> &OutOps) override;
+
   StringRef getPassName() const override {
     return "VE DAG->DAG Pattern Instruction Selection";
   }
 
   // Include the pieces autogenerated from the target description.
 #include "VEGenDAGISel.inc"
 
 private:
void VEDAGToDAGISel::Select(SDNode *N) {
   case VEISD::GLOBAL_BASE_REG:
     ReplaceNode(N, getGlobalBaseReg());
     return;
   }
 
   SelectCode(N);
 }
 
+/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+/// inline asm expressions.
+bool
+VEDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                             unsigned ConstraintID,
+                                             std::vector<SDValue> &OutOps) {
+  SDValue Op0, Op1;
+  switch (ConstraintID) {
+  default:
+    llvm_unreachable("Unexpected asm memory constraint");
+  case InlineAsm::Constraint_o:
+  case InlineAsm::Constraint_m: // memory
+    // Try to match ADDRri since reg+imm style is safe for all VE instructions
+    // with a memory operand.
+    if (selectADDRri(Op, Op0, Op1)) {
+      OutOps.push_back(Op0);
+      OutOps.push_back(Op1);
+      return false;
+    }
+    // Otherwise, require the address to be in a register and immediate 0.
+    OutOps.push_back(Op);
+    OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
+    return false;
+  }
+  return true;
+}
+
 SDNode *VEDAGToDAGISel::getGlobalBaseReg() {
   Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
   return CurDAG
       ->getRegister(GlobalBaseReg, TLI->getPointerTy(CurDAG->getDataLayout()))
       .getNode();
 }
 
 /// createVEISelDag - This pass converts a legalized DAG into a
 /// VE-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) {
   return new VEDAGToDAGISel(TM);
 }

llvm/lib/Target/VE/VERegisterInfo.cpp

static unsigned offsetToDisp(MachineInstr &MI) {
   // Default offset in instruction's operands (reg+reg+imm).
   unsigned OffDisp = 2;
 
 #define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii
 
   {
     using namespace llvm::VE;
     switch (MI.getOpcode()) {
+    case INLINEASM:
     case RRCAS_multi_cases(TS1AML):
     case RRCAS_multi_cases(TS1AMW):
     case RRCAS_multi_cases(CASL):
     case RRCAS_multi_cases(CASW):
       // These instructions use AS format (reg+imm).
       OffDisp = 1;
       break;
     }

llvm/test/CodeGen/VE/Scalar/inlineasm-mem-gv.ll

+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+@A = dso_local global i64 0, align 8
+
+define i64 @leam(i64 %x) nounwind {
+; CHECK-LABEL: leam:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, A@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s0, A@hi(, %s0)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea %s0, (%s0)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    b.l.t (, %s10)
+  %asmtmp = tail call i64 asm "lea $0, $1", "=r,*m"(i64* elementtype(i64) @A) nounwind
+  ret i64 %asmtmp
+}

llvm/test/CodeGen/VE/Scalar/inlineasm-mem-lo.ll

+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+define i64 @leam(i64 %x) nounwind {
+; CHECK-LABEL: leam:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lea %s0, 8(%s11)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    adds.l %s11, 16, %s11
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = alloca i64, align 8
+  %asmtmp = tail call i64 asm "lea $0, $1", "=r,*m"(i64* elementtype(i64) %z) nounwind
+  ret i64 %asmtmp
+}