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Differential D131613

[LLDB][NFC] Clean up dead code
ClosedPublic

Authored by fixathon on Aug 10 2022, 12:54 PM.

Details

Reviewers
clayborg
JDevlieghere
DavidSpickett
jasonmolenda
Commits
rGf4c21ab8b32d: [LLDB][NFC] Clean up dead code
Summary

Remove unreachable code that will never execute.

Diff Detail

Event Timeline

fixathon created this revision.Aug 10 2022, 12:54 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2022, 12:54 PM
fixathon requested review of this revision.Aug 10 2022, 12:54 PM
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Herald added a subscriber: lldb-commits. · View Herald Transcript
Harbormaster completed remote builds in B180502: Diff 451607.Aug 10 2022, 12:57 PM
JDevlieghere accepted this revision.Aug 10 2022, 3:05 PM

LGTM!

This revision is now accepted and ready to land.Aug 10 2022, 3:05 PM
Closed by commit rGf4c21ab8b32d: [LLDB][NFC] Clean up dead code (authored by fixathon). · Explain WhyAug 10 2022, 3:22 PM
This revision was automatically updated to reflect the committed changes.
fixathon added a commit: rGf4c21ab8b32d: [LLDB][NFC] Clean up dead code.

Revision Contents

PathSize
lldb/
source/
Plugins/
Instruction/
ARM/
10 lines

Diff 451656

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,763 Lines • ▼ Show 20 Lines if (shift_type == SRType_ROR && use_encoding == eEncodingT1) {
// Morph the T1 encoding from the ARM Architecture Manual into T2 // Morph the T1 encoding from the ARM Architecture Manual into T2
// encoding to have the same decoding of bit fields as the other Thumb2 // encoding to have the same decoding of bit fields as the other Thumb2
// shift operations. // shift operations.
use_encoding = eEncodingT2; use_encoding = eEncodingT2;
} }
switch (use_encoding) { switch (use_encoding) {
case eEncodingT1: case eEncodingT1:
// Due to the above special case handling!
if (shift_type == SRType_ROR)
return false;
Rd = Bits32(opcode, 2, 0); Rd = Bits32(opcode, 2, 0);
Rm = Bits32(opcode, 5, 3); Rm = Bits32(opcode, 5, 3);
setflags = !InITBlock(); setflags = !InITBlock();
imm5 = Bits32(opcode, 10, 6); imm5 = Bits32(opcode, 10, 6);
break; break;
case eEncodingT2: case eEncodingT2:
// A8.6.141 RRX // A8.6.141 RRX
// There's no imm form of RRX instructions. // There's no imm form of RRX instructions.
▲ Show 20 Lines • Show All 350 Lines • ▼ Show 20 Lines if (BitIsSet(registers, 15)) {
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
// if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers); // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
if (wback && BitIsClear(registers, n)) { if (wback && BitIsClear(registers, n)) {
if (!success)
return false;
offset = (addr_byte_size * BitCount(registers)) * -1; offset = (addr_byte_size * BitCount(registers)) * -1;
context.type = EmulateInstruction::eContextAdjustBaseRegister; context.type = EmulateInstruction::eContextAdjustBaseRegister;
context.SetImmediateSigned(offset); context.SetImmediateSigned(offset);
addr_t addr = Rn + offset; addr_t addr = Rn + offset;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
addr)) addr))
return false; return false;
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines if (BitIsSet(registers, 15)) {
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
// if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers); // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
if (wback && BitIsClear(registers, n)) { if (wback && BitIsClear(registers, n)) {
if (!success)
return false;
offset = (addr_byte_size * BitCount(registers)) * -1; offset = (addr_byte_size * BitCount(registers)) * -1;
context.type = EmulateInstruction::eContextAdjustBaseRegister; context.type = EmulateInstruction::eContextAdjustBaseRegister;
context.SetImmediateSigned(offset); context.SetImmediateSigned(offset);
addr_t addr = Rn + offset; addr_t addr = Rn + offset;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
addr)) addr))
return false; return false;
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines if (BitIsSet(registers, 15)) {
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data)) if (!LoadWritePC(context, data))
return false; return false;
} }
// if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers); // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
if (wback && BitIsClear(registers, n)) { if (wback && BitIsClear(registers, n)) {
if (!success)
return false;
offset = addr_byte_size * BitCount(registers); offset = addr_byte_size * BitCount(registers);
context.type = EmulateInstruction::eContextAdjustBaseRegister; context.type = EmulateInstruction::eContextAdjustBaseRegister;
context.SetImmediateSigned(offset); context.SetImmediateSigned(offset);
addr_t addr = Rn + offset; addr_t addr = Rn + offset;
if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n,
addr)) addr))
return false; return false;
▲ Show 20 Lines • Show All 10,100 Lines • Show Last 20 Lines