[IndVars] Eliminate redundant type cast with different sizes

[Allen]

Summary

Deal with different sizes between the itofp and fptoi with
trunc or sext/zext, depend on D129756.
Fixes https://github.com/llvm/llvm-project/issues/55505.

[nikic]

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

696

Why do we need an early inc range now? We're adding a new user of the IVOperand, not the UseInst, right?

706–724

I don't think the IVOperand is necessarily a phi node. Can you add a test where the itofp is on the postinc IV (i.e. the add)?

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

135

I don't understand these tests. We don't want an existing sext user, but rather a wider type on the fptosi. So sitofp i16 and then fptosi i32.

[Allen]

Address the comment and add new test sitofp_fptosi_range_zext_postinc with postinc IV

[Allen]

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

696

I thought using make_early_inc_range would increase the robustness of the code referring to 85b4b21c8bb, I'll delete it as it is surely unnecessary.

706–724

I'm kind of curious, besides phi nodes, what other types of inductive variables can be expressed?

Sure, IVOperand does not need to be a phi node at this point.

PS: the new added case sitofp_fptosi_range_zext_postinc with postinc IV

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

135

Done, thanks for guiding me on how to build the right test cases.

[Allen]

ping ?

[Allen]

update to fix llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll

[nikic]

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

713

I believe we only need sext if both fptosi and sitofp are used. If one of them is unsigned, then we can use zext. This would match InstCombine logic.

In any case, we should have a test for the uitofp+fptosi combination.

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

145

Should be fptoui

180

Same here

[Allen]

If one of them is unsigned, then we can use zext

[nikic]

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

181

This isn't quite what I had in mind. By "postinc IV" I mean that %inc.int gets passed to sitofp, rather than %iv.int. I think your current code may result in a wrong insertion point for this case.

[Allen]

Fix the crash of the case with 'postinc IV'

[nikic]

I don't think the last update changed any code?

[Allen]

update to fix crash

[Allen]

In D129958#3709096, @nikic wrote:

I don't think the last update changed any code?

sorry, I upload with an old version, and now it is ok.

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

713

Done, thanks @nikic very much!

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

181

Now, I just update code to fix the crash for the case with "postinc IV", and I'll try to improve it next patch as I need some time to get the right insertion point.

[nikic]

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

181

Shouldn't the insertion point simply be CI?

[Allen]

update the insertion point with CI

[nikic]

LGTM

[Allen]

rebase to update test case in file floating-point-iv.ll

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

 }
 
 /// Eliminate redundant type cast between integer and float.
 bool SimplifyIndvar::replaceFloatIVWithIntegerIV(Instruction *UseInst) {
   if (UseInst->getOpcode() != CastInst::SIToFP &&
       UseInst->getOpcode() != CastInst::UIToFP)
     return false;
 
-  Value *IVOperand = UseInst->getOperand(0);
+  Instruction *IVOperand = cast<Instruction>(UseInst->getOperand(0));
   // Get the symbolic expression for this instruction.
   const SCEV *IV = SE->getSCEV(IVOperand);
   unsigned MaskBits;
   if (UseInst->getOpcode() == CastInst::SIToFP)
     MaskBits = SE->getSignedRange(IV).getMinSignedBits();
   else
     MaskBits = SE->getUnsignedRange(IV).getActiveBits();
   unsigned DestNumSigBits = UseInst->getType()->getFPMantissaWidth();
   if (MaskBits <= DestNumSigBits) {
     for (User *U : UseInst->users()) {
       // Match for fptosi/fptoui of sitofp and with same type.
       auto *CI = dyn_cast<CastInst>(U);
-      if (!CI || IVOperand->getType() != CI->getType())
+      if (!CI)
         continue;
 
       CastInst::CastOps Opcode = CI->getOpcode();
       if (Opcode != CastInst::FPToSI && Opcode != CastInst::FPToUI)
         continue;
 
-      CI->replaceAllUsesWith(IVOperand);
+      Value *Conv = nullptr;
+      if (IVOperand->getType() != CI->getType()) {
+        IRBuilder<> Builder(CI);
+        StringRef Name = IVOperand->getName();
+        // To match InstCombine logic, we only need sext if both fptosi and
+        // sitofp are used. If one of them is unsigned, then we can use zext.
+        if (SE->getTypeSizeInBits(IVOperand->getType()) >
+            SE->getTypeSizeInBits(CI->getType())) {
+          Conv = Builder.CreateTrunc(IVOperand, CI->getType(), Name + ".trunc");
+        } else if (Opcode == CastInst::FPToUI ||
+                   UseInst->getOpcode() == CastInst::UIToFP) {
+          Conv = Builder.CreateZExt(IVOperand, CI->getType(), Name + ".zext");
+        } else {
+          Conv = Builder.CreateSExt(IVOperand, CI->getType(), Name + ".sext");
+        }
+      } else
+        Conv = IVOperand;
+
+      CI->replaceAllUsesWith(Conv);
       DeadInsts.push_back(CI);
       LLVM_DEBUG(dbgs() << "INDVARS: Replace IV user: " << *CI
-                        << " with: " << *IVOperand << '\n');
+                        << " with: " << *Conv << '\n');
 
       ++NumFoldedUser;
       Changed = true;
     }
   }
 
   return Changed;
 }

llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll

 ; CHECK-LABEL: @pr55505_remove_redundant_fptosi_for_float_iv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[FLOAT_IV_INT:%.*]] = phi i32 [ 1000, [[ENTRY:%.*]] ], [ [[FLOAT_IV_NEXT_INT:%.*]], [[LOOP]] ]
 ; CHECK-NEXT:    [[INDVAR_CONV:%.*]] = sitofp i32 [[FLOAT_IV_INT]] to float
 ; CHECK-NEXT:    call void @use.float(float [[INDVAR_CONV]])
 ; CHECK-NEXT:    call void @use.i32(i32 [[FLOAT_IV_INT]])
-; CHECK-NEXT:    [[CONV_I16:%.*]] = fptosi float [[INDVAR_CONV]] to i16
-; CHECK-NEXT:    [[CONV_I64:%.*]] = fptosi float [[INDVAR_CONV]] to i64
-; CHECK-NEXT:    call void @use.i16(i16 [[CONV_I16]])
-; CHECK-NEXT:    call void @use.i64(i64 [[CONV_I64]])
-; CHECK-NEXT:    [[UCONV_I16:%.*]] = fptoui float [[INDVAR_CONV]] to i16
-; CHECK-NEXT:    [[UCONV_I64:%.*]] = fptoui float [[INDVAR_CONV]] to i64
-; CHECK-NEXT:    call void @use.i16(i16 [[UCONV_I16]])
-; CHECK-NEXT:    call void @use.i64(i64 [[UCONV_I64]])
+; CHECK-NEXT:    [[FLOAT_IV_INT_TRUNC:%.*]] = trunc i32 [[FLOAT_IV_INT]] to i16
+; CHECK-NEXT:    [[FLOAT_IV_INT_SEXT:%.*]] = sext i32 [[FLOAT_IV_INT]] to i64
+; CHECK-NEXT:    call void @use.i16(i16 [[FLOAT_IV_INT_TRUNC]])
+; CHECK-NEXT:    call void @use.i64(i64 [[FLOAT_IV_INT_SEXT]])
+; CHECK-NEXT:    [[FLOAT_IV_INT_TRUNC2:%.*]] = trunc i32 [[FLOAT_IV_INT]] to i16
+; CHECK-NEXT:    [[FLOAT_IV_INT_ZEXT:%.*]] = zext i32 [[FLOAT_IV_INT]] to i64
+; CHECK-NEXT:    call void @use.i16(i16 [[FLOAT_IV_INT_TRUNC2]])
+; CHECK-NEXT:    call void @use.i64(i64 [[FLOAT_IV_INT_ZEXT]])
 ; CHECK-NEXT:    [[FLOAT_IV_NEXT_INT]] = add nsw i32 [[FLOAT_IV_INT]], -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[FLOAT_IV_NEXT_INT]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br label %loop

llvm/test/Transforms/IndVarSimplify/floating-point-small-iv.ll

for.body:                                         ; preds = %for.body, %entry
   %dec.int = add nsw i32 %iv.int, -1
   %cmp = icmp ugt i32 %dec.int, 0
   br i1 %cmp, label %for.body, label %cleanup
 
 cleanup:                                          ; preds = %for.body
   ret void
 }
 
-; Negative test: Type mismatch between the integer IV and the fptosi result
-define void @sitofp_fptosi_range_mismatch_type() {
+; Type mismatch between the integer IV and the fptosi result
+define void @sitofp_fptosi_range_trunc() {
 ;
-; CHECK-LABEL: @sitofp_fptosi_range_mismatch_type(
+; CHECK-LABEL: @sitofp_fptosi_range_trunc(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
 ; CHECK:       for.body:
-; CHECK-NEXT:    [[IV_INT:%.*]] = phi i32 [ 100, [[ENTRY:%.*]] ], [ [[DEC_INT:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT:    [[INDVAR_CONV:%.*]] = sitofp i32 [[IV_INT]] to float
-; CHECK-NEXT:    [[CONV:%.*]] = fptosi float [[INDVAR_CONV]] to i16
-; CHECK-NEXT:    [[IDXPROM32:%.*]] = sext i16 [[CONV]] to i32
-; CHECK-NEXT:    [[IDXPROM64:%.*]] = sext i16 [[CONV]] to i64
-; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[IDXPROM64]]
-; CHECK-NEXT:    store i32 [[IDXPROM32]], i32* [[ARRAYIDX]], align 4
-; CHECK-NEXT:    [[DEC_INT]] = add nsw i32 [[IV_INT]], -1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[DEC_INT]], 0
+; CHECK-NEXT:    [[IV_INT:%.*]] = phi i64 [ 100, [[ENTRY:%.*]] ], [ [[DEC_INT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[IV_INT_TRUNC:%.*]] = trunc i64 [[IV_INT]] to i32
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[IV_INT]]
+; CHECK-NEXT:    store i32 [[IV_INT_TRUNC]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT:    [[DEC_INT]] = add nsw i64 [[IV_INT]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[DEC_INT]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[CLEANUP:%.*]]
 ; CHECK:       cleanup:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
-  %iv.int = phi i32 [ 100, %entry ], [ %dec.int, %for.body ]
-  %indvar.conv = sitofp i32 %iv.int to float
-  %conv = fptosi float %indvar.conv to i16
-  %idxprom32 = sext i16 %conv to i32
-  %idxprom64 = sext i16 %conv to i64
+  %iv.int = phi i64 [ 100, %entry ], [ %dec.int, %for.body ]
+  %indvar.conv = sitofp i64 %iv.int to float
+  %idxprom32 = fptosi float %indvar.conv to i32
+  %idxprom64 = fptosi float %indvar.conv to i64
   %arrayidx = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 %idxprom64
   store i32 %idxprom32, i32* %arrayidx, align 4
-  %dec.int = add nsw i32 %iv.int, -1
-  %cmp = icmp ugt i32 %dec.int, 0
+  %dec.int = add nsw i64 %iv.int, -1
+  %cmp = icmp ugt i64 %dec.int, 0
   br i1 %cmp, label %for.body, label %cleanup
 
 cleanup:                                          ; preds = %for.body
   ret void
 }
 
+define void @sitofp_fptosi_range_sext() {
+;
+; CHECK-LABEL: @sitofp_fptosi_range_sext(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[IV_INT:%.*]] = phi i16 [ 100, [[ENTRY:%.*]] ], [ [[DEC_INT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[IV_INT_SEXT1:%.*]] = sext i16 [[IV_INT]] to i32
+; CHECK-NEXT:    [[IV_INT_SEXT:%.*]] = sext i16 [[IV_INT]] to i64
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[IV_INT_SEXT]]
+; CHECK-NEXT:    store i32 [[IV_INT_SEXT1]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT:    [[DEC_INT]] = add nsw i16 [[IV_INT]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i16 [[DEC_INT]], -3
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[CLEANUP:%.*]]
+; CHECK:       cleanup:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %iv.int = phi i16 [ 100, %entry ], [ %dec.int, %for.body ]
+  %indvar.conv = sitofp i16 %iv.int to float
+  %idxprom32 = fptosi float %indvar.conv to i32
+  %idxprom64 = fptosi float %indvar.conv to i64
+  %arrayidx = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 %idxprom64
+  store i32 %idxprom32, i32* %arrayidx, align 4
+  %dec.int = add nsw i16 %iv.int, -1
+  %cmp = icmp sgt i16 %dec.int, -3
+  br i1 %cmp, label %for.body, label %cleanup
+
+cleanup:                                          ; preds = %for.body
+  ret void
+}
+
+; If one of them is unsigned, then we can use zext.
+define void @sitofp_fptoui_range_zext() {
+;
+; CHECK-LABEL: @sitofp_fptoui_range_zext(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[IV_INT:%.*]] = phi i16 [ 100, [[ENTRY:%.*]] ], [ [[DEC_INT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[IV_INT_ZEXT1:%.*]] = zext i16 [[IV_INT]] to i32
+; CHECK-NEXT:    [[IV_INT_ZEXT:%.*]] = zext i16 [[IV_INT]] to i64
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[IV_INT_ZEXT]]
+; CHECK-NEXT:    store i32 [[IV_INT_ZEXT1]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT:    [[DEC_INT]] = add nsw i16 [[IV_INT]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i16 [[DEC_INT]], 0
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[CLEANUP:%.*]]
+; CHECK:       cleanup:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %iv.int = phi i16 [ 100, %entry ], [ %dec.int, %for.body ]
+  %indvar.conv = sitofp i16 %iv.int to float
+  %idxprom32 = fptoui float %indvar.conv to i32
+  %idxprom64 = fptoui float %indvar.conv to i64
+  %arrayidx = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 %idxprom64
+  store i32 %idxprom32, i32* %arrayidx, align 4
+  %dec.int = add nsw i16 %iv.int, -1
+  %cmp = icmp ugt i16 %dec.int, 0
+  br i1 %cmp, label %for.body, label %cleanup
+
+cleanup:                                          ; preds = %for.body
+  ret void
+}
+
+; Take care of the insertion point.
+define void @sitofp_fptoui_range_zext_postinc() {
+;
+; CHECK-LABEL: @sitofp_fptoui_range_zext_postinc(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[IV_INT:%.*]] = phi i16 [ 100, [[ENTRY:%.*]] ], [ [[INC_INT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[INC_INT]] = add nuw nsw i16 [[IV_INT]], 2
+; CHECK-NEXT:    [[INC_INT_ZEXT1:%.*]] = zext i16 [[INC_INT]] to i32
+; CHECK-NEXT:    [[INC_INT_ZEXT:%.*]] = zext i16 [[INC_INT]] to i64
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[INC_INT_ZEXT]]
+; CHECK-NEXT:    store i32 [[INC_INT_ZEXT1]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i16 [[INC_INT]], 200
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[CLEANUP:%.*]]
+; CHECK:       cleanup:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %iv.int = phi i16 [ 100, %entry ], [ %inc.int, %for.body ]
+  %inc.int = add nsw i16 %iv.int, 2
+  %indvar.conv = sitofp i16 %inc.int to float     ; The 'postinc IV' %inc.int passes to sitofp
+  %idxprom32 = fptoui float %indvar.conv to i32
+  %idxprom64 = fptoui float %indvar.conv to i64
+  %arrayidx = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 %idxprom64
+  store i32 %idxprom32, i32* %arrayidx, align 4
+  %cmp = icmp ult i16 %inc.int, 200
+  br i1 %cmp, label %for.body, label %cleanup
+
+cleanup:                                          ; preds = %for.body
+  ret void
+}
+
+; If one of them is unsigned, then we can use zext.
+define void @uitofp_fptosi_range_zext() {
+;
+; CHECK-LABEL: @uitofp_fptosi_range_zext(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[IV_INT:%.*]] = phi i16 [ 100, [[ENTRY:%.*]] ], [ [[INC_INT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[IV_INT_ZEXT1:%.*]] = zext i16 [[IV_INT]] to i32
+; CHECK-NEXT:    [[IV_INT_ZEXT:%.*]] = zext i16 [[IV_INT]] to i64
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[IV_INT_ZEXT]]
+; CHECK-NEXT:    store i32 [[IV_INT_ZEXT1]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT:    [[INC_INT]] = add nuw nsw i16 [[IV_INT]], 2
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i16 [[INC_INT]], 200
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[CLEANUP:%.*]]
+; CHECK:       cleanup:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %iv.int = phi i16 [ 100, %entry ], [ %inc.int, %for.body ]
+  %indvar.conv = uitofp i16 %iv.int to float
+  %idxprom32 = fptosi float %indvar.conv to i32
+  %idxprom64 = fptosi float %indvar.conv to i64
+  %arrayidx = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 %idxprom64
+  store i32 %idxprom32, i32* %arrayidx, align 4
+  %inc.int = add nsw i16 %iv.int, 2
+  %cmp = icmp ult i16 %inc.int, 200
+  br i1 %cmp, label %for.body, label %cleanup
+
+cleanup:                                          ; preds = %for.body
+  ret void
+}
+
+
 define void @sitofp_fptoui_range() {
 ; CHECK-LABEL: @sitofp_fptoui_range(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[IV_INT:%.*]] = phi i32 [ 100, [[ENTRY:%.*]] ], [ [[DEC_INT:%.*]], [[FOR_BODY]] ]
 ; CHECK-NEXT:    [[IDXPROM:%.*]] = zext i32 [[IV_INT]] to i64
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [16777219 x i32], [16777219 x i32]* @array, i64 0, i64 [[IDXPROM]]