Don't raise inexact when lowering ceil, floor, round, trunc

[scanon]

Summary

The C standard has historically not specified whether or not these functions should raise the inexact flag. Traditionally on Darwin, these functions *did* raise inexact, and the llvm lowerings followed that conventions. n1778 (C bindings for IEEE-754 (2008)) clarifies that these functions should not set inexact. This patch brings the lowerings for arm64 and x86 in line with the newly specified behavior.

[t.p.northover]

Oh, nice! I wished we could do this when I became aware of the issue but thought it would be too late. The AArch64 changes look fine to me, and the x86 ones technically correct (still raise an exception for frint, for example).

It looks like this changes Linux behaviour on x86 though. I still think the change should be made (as does at least one GCC developer: https://gcc.gnu.org/ml/gcc/2015-01/msg00274.html), but perhaps we should give people a few days to pipe up if they object.

Tim.

[gberry]

I believe with this change we could remove both AArch64DAGToDAGISel::SelectFPConvertWithRound() and AArch64DAGToDAGISel::SelectLIBM() in favor of TD file patterns as well.

[t.p.northover]

Quite right, well spotted!

Tim.

[scanon]

Removed AArch64DAGToDAGISel::SelectFPConvertWithRound() and SelectLIBM() in favor of TD patterns.

[t.p.northover]

Thanks for updating the patch Steve. One more thing I spotted:

lib/Target/AArch64/AArch64InstrInfo.td

2488–2492

Sorry for only bringing this up now, but this doesn't look right. I think if an FRINTX does get created it probably should be treated specially. You'd mostly only do so (by calling "rint") if you actually cared about the otherwise unmodeled FPSR flags, wouldn't you?

[scanon]

In D12969#250004, @t.p.northover wrote:

Sorry for only bringing this up now, but this doesn't look right. I think if an FRINTX does get created it probably should be treated specially. You'd mostly only do so (by calling "rint") if you actually cared about the otherwise unmodeled FPSR flags, wouldn't you?

On x86 rint( ) is often just the fastest portable way to get round-to-nearest integer (assuming default rounding is set), so it's mostly used for that purpose, not because the caller is necessarily interested in the flags.

We don't handle FPSR like this anywhere else, so it doesn't seem like we should give it special attention here either. While I'd like to eventually model floating-point flags correctly, I don't think it's important that we go out of our way to add fake side-effects to one instruction in isolation.

[t.p.northover]

Fair point, and it does seem much less important now that we're not having to keep an otherwise dead FCVTX around for libm compatibility.

I think this looks good (again) now, then.

Anyone from the x86 Linux world object to following C1y's rules more widely? Speak up now if so.

Tim.

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

 
 //===--------------------------------------------------------------------===//
 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
 /// instructions for SelectionDAG operations.
 ///
 namespace {
 
 class AArch64DAGToDAGISel : public SelectionDAGISel {
-  AArch64TargetMachine &TM;
 
   /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const AArch64Subtarget *Subtarget;
 
   bool ForCodeSize;
 
 public:
   explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
                                CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(tm, OptLevel), TM(tm), Subtarget(nullptr),
+      : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
         ForCodeSize(false) {}
 
   const char *getPassName() const override {
     return "AArch64 Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     ForCodeSize = MF.getFunction()->optForSize();
public:
   SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
   SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
   SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
 
   SDNode *SelectBitfieldExtractOp(SDNode *N);
   SDNode *SelectBitfieldInsertOp(SDNode *N);
   SDNode *SelectBitfieldInsertInZeroOp(SDNode *N);
 
-  SDNode *SelectLIBM(SDNode *N);
-  SDNode *SelectFPConvertWithRound(SDNode *N);
-
   SDNode *SelectReadRegister(SDNode *N);
   SDNode *SelectWriteRegister(SDNode *N);
 
 // Include the pieces autogenerated from the target description.
 #include "AArch64GenDAGISel.inc"
 
 private:
   bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
                          SDValue &Offset, SDValue &SignExtend);
 
   template<unsigned RegWidth>
   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
     return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
   }
 
   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
-
-  SDNode *GenerateInexactFlagIfNeeded(const SDValue &In, unsigned InTyVariant,
-                                      SDLoc DL);
 };
 } // end anonymous namespace
 
 /// isIntImmediate - This method tests to see if the node is a constant
 /// operand. If so Imm will receive the 32-bit value.
 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
   if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
     Imm = C->getZExtValue();
SDNode *AArch64DAGToDAGISel::SelectBitfieldInsertInZeroOp(SDNode *N) {
   unsigned ImmS = Width - 1;
 
   SDLoc DL(N);
   SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
                    CurDAG->getTargetConstant(ImmS, DL, VT)};
   return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
 }
 
-/// GenerateInexactFlagIfNeeded - Insert FRINTX instruction to generate inexact
-/// signal on round-to-integer operations if needed. C11 leaves it
-/// implementation-defined whether these operations trigger an inexact
-/// exception. IEEE says they don't.  Unfortunately, Darwin decided they do so
-/// we sometimes have to insert a special instruction just to set the right bit
-/// in FPSR.
-SDNode *AArch64DAGToDAGISel::GenerateInexactFlagIfNeeded(const SDValue &In,
-                                                         unsigned InTyVariant,
-                                                         SDLoc DL) {
-  if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) {
-    // Pick the right FRINTX using InTyVariant needed to set the flags.
-    // InTyVariant is 0 for 32-bit and 1 for 64-bit.
-    unsigned FRINTXOpcs[] = { AArch64::FRINTXSr, AArch64::FRINTXDr };
-    return CurDAG->getMachineNode(FRINTXOpcs[InTyVariant], DL,
-                                  In.getValueType(), MVT::Glue, In);
-  }
-  return nullptr;
-}
-
-SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
-  EVT VT = N->getValueType(0);
-  unsigned Variant;
-  unsigned Opc;
-
-  if (VT == MVT::f32) {
-    Variant = 0;
-  } else if (VT == MVT::f64) {
-    Variant = 1;
-  } else
-    return nullptr; // Unrecognized argument type. Fall back on default codegen.
-
-  switch (N->getOpcode()) {
-  default:
-    return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
-  case ISD::FCEIL: {
-    unsigned FRINTPOpcs[] = { AArch64::FRINTPSr, AArch64::FRINTPDr };
-    Opc = FRINTPOpcs[Variant];
-    break;
-  }
-  case ISD::FFLOOR: {
-    unsigned FRINTMOpcs[] = { AArch64::FRINTMSr, AArch64::FRINTMDr };
-    Opc = FRINTMOpcs[Variant];
-    break;
-  }
-  case ISD::FTRUNC: {
-    unsigned FRINTZOpcs[] = { AArch64::FRINTZSr, AArch64::FRINTZDr };
-    Opc = FRINTZOpcs[Variant];
-    break;
-  }
-  case ISD::FROUND: {
-    unsigned FRINTAOpcs[] = { AArch64::FRINTASr, AArch64::FRINTADr };
-    Opc = FRINTAOpcs[Variant];
-    break;
-  }
-  }
-
-  SDLoc dl(N);
-  SDValue In = N->getOperand(0);
-  SmallVector<SDValue, 2> Ops;
-  Ops.push_back(In);
-
-  if (SDNode *FRINTXNode = GenerateInexactFlagIfNeeded(In, Variant, dl))
-    Ops.push_back(SDValue(FRINTXNode, 1));
-
-  return CurDAG->getMachineNode(Opc, dl, VT, Ops);
-}
-
-/// SelectFPConvertWithRound - Try to combine FP rounding and
-/// FP-INT conversion.
-SDNode *AArch64DAGToDAGISel::SelectFPConvertWithRound(SDNode *N) {
-  SDNode *Op0 = N->getOperand(0).getNode();
-
-  // Return if the round op is used by other nodes, as this would result in two
-  // FRINTX, one each for round and convert.
-  if (!Op0->hasOneUse())
-    return nullptr;
-
-  unsigned InTyVariant;
-  EVT InTy = Op0->getValueType(0);
-  if (InTy == MVT::f32)
-    InTyVariant = 0;
-  else if (InTy == MVT::f64)
-    InTyVariant = 1;
-  else
-    return nullptr;
-
-  unsigned OutTyVariant;
-  EVT OutTy = N->getValueType(0);
-  if (OutTy == MVT::i32)
-    OutTyVariant = 0;
-  else if (OutTy == MVT::i64)
-    OutTyVariant = 1;
-  else
-    return nullptr;
-
-  assert((N->getOpcode() == ISD::FP_TO_SINT
-          || N->getOpcode() == ISD::FP_TO_UINT) && "Unexpected opcode!");
-  unsigned FpConVariant = N->getOpcode() == ISD::FP_TO_SINT ? 0 : 1;
-
-  unsigned Opc;
-  switch (Op0->getOpcode()) {
-  default:
-    return nullptr;
-  case ISD::FCEIL: {
-    unsigned FCVTPOpcs[2][2][2] = {
-        { { AArch64::FCVTPSUWSr, AArch64::FCVTPSUXSr },
-          { AArch64::FCVTPSUWDr, AArch64::FCVTPSUXDr } },
-        { { AArch64::FCVTPUUWSr, AArch64::FCVTPUUXSr },
-          { AArch64::FCVTPUUWDr, AArch64::FCVTPUUXDr } } };
-    Opc = FCVTPOpcs[FpConVariant][InTyVariant][OutTyVariant];
-    break;
-  }
-  case ISD::FFLOOR: {
-    unsigned FCVTMOpcs[2][2][2] = {
-        { { AArch64::FCVTMSUWSr, AArch64::FCVTMSUXSr },
-          { AArch64::FCVTMSUWDr, AArch64::FCVTMSUXDr } },
-        { { AArch64::FCVTMUUWSr, AArch64::FCVTMUUXSr },
-          { AArch64::FCVTMUUWDr, AArch64::FCVTMUUXDr } } };
-    Opc = FCVTMOpcs[FpConVariant][InTyVariant][OutTyVariant];
-    break;
-  }
-  case ISD::FTRUNC: {
-    unsigned FCVTZOpcs[2][2][2] = {
-        { { AArch64::FCVTZSUWSr, AArch64::FCVTZSUXSr },
-          { AArch64::FCVTZSUWDr, AArch64::FCVTZSUXDr } },
-        { { AArch64::FCVTZUUWSr, AArch64::FCVTZUUXSr },
-          { AArch64::FCVTZUUWDr, AArch64::FCVTZUUXDr } } };
-    Opc = FCVTZOpcs[FpConVariant][InTyVariant][OutTyVariant];
-    break;
-  }
-  case ISD::FROUND: {
-    unsigned FCVTAOpcs[2][2][2] = {
-        { { AArch64::FCVTASUWSr, AArch64::FCVTASUXSr },
-          { AArch64::FCVTASUWDr, AArch64::FCVTASUXDr } },
-        { { AArch64::FCVTAUUWSr, AArch64::FCVTAUUXSr },
-          { AArch64::FCVTAUUWDr, AArch64::FCVTAUUXDr } } };
-    Opc = FCVTAOpcs[FpConVariant][InTyVariant][OutTyVariant];
-    break;
-  }
-  }
-
-  SDLoc DL(N);
-  SDValue In = Op0->getOperand(0);
-  SmallVector<SDValue, 2> Ops;
-  Ops.push_back(In);
-
-  if (SDNode *FRINTXNode = GenerateInexactFlagIfNeeded(In, InTyVariant, DL))
-    Ops.push_back(SDValue(FRINTXNode, 1));
-
-  return CurDAG->getMachineNode(Opc, DL, OutTy, Ops);
-}
-
 bool
 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
                                               unsigned RegWidth) {
   APFloat FVal(0.0);
   if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
     FVal = CN->getValueAPF();
   else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
     // Some otherwise illegal constants are allowed in this case.
case AArch64ISD::ST4LANEpost: {
     else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
              VT == MVT::v2f32)
       return SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
     else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
              VT == MVT::v1f64)
       return SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
     break;
   }
-
-  case ISD::FCEIL:
-  case ISD::FFLOOR:
-  case ISD::FTRUNC:
-  case ISD::FROUND:
-    if (SDNode *I = SelectLIBM(Node))
-      return I;
-    break;
-
-  case ISD::FP_TO_SINT:
-  case ISD::FP_TO_UINT:
-    if (SDNode *I = SelectFPConvertWithRound(Node))
-      return I;
-    break;
   }
 
   // Select the default instruction
   ResNode = SelectCode(Node);
 
   DEBUG(errs() << "=> ");
   if (ResNode == nullptr || ResNode == Node)
     DEBUG(Node->dump(CurDAG));

lib/Target/AArch64/AArch64InstrInfo.td

 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
 let isCodeGenOnly = 1 in {
 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
 }
 
+multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> {
+  def : Pat<(i32 (to_int (round f32:$Rn))),
+            (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
+  def : Pat<(i64 (to_int (round f32:$Rn))),
+            (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
+  def : Pat<(i32 (to_int (round f64:$Rn))),
+            (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
+  def : Pat<(i64 (to_int (round f64:$Rn))),
+            (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
+}
+
+defm : FPToIntegerPats<fp_to_sint, fceil,  "FCVTPS">;
+defm : FPToIntegerPats<fp_to_uint, fceil,  "FCVTPU">;
+defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
+defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
+defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
+defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
+defm : FPToIntegerPats<fp_to_sint, frnd,   "FCVTAS">;
+defm : FPToIntegerPats<fp_to_uint, frnd,   "FCVTAU">;
+
 //===----------------------------------------------------------------------===//
 // Scaled integer to floating point conversion instructions.
 //===----------------------------------------------------------------------===//
 
 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
 
 //===----------------------------------------------------------------------===//

 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
 
 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
           (FRINTNDr FPR64:$Rn)>;
 
-// FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
-// in the C spec. Setting hasSideEffects ensures it is not DCE'd.
-// <rdar://problem/13715968>
-// TODO: We should really model the FPSR flags correctly. This is really ugly.
-let hasSideEffects = 1 in {
 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
-}
-
 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
 
 let SchedRW = [WriteFDiv] in {
 defm FSQRT  : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
 }
 
 //===----------------------------------------------------------------------===//
 // Floating point two operand instructions.

lib/Target/X86/X86InstrSSE.td

defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
                                   int_x86_avx_round_pd_256>, VEX, VEX_L;
   defm VROUND  : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
                                   int_x86_sse41_round_ss,
                                   int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
 }
 
 let Predicates = [UseAVX] in {
   def : Pat<(ffloor FR32:$src),
-            (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
+            (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
   def : Pat<(f64 (ffloor FR64:$src)),
-            (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
+            (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
   def : Pat<(f32 (fnearbyint FR32:$src)),
             (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
   def : Pat<(f64 (fnearbyint FR64:$src)),
             (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
   def : Pat<(f32 (fceil FR32:$src)),
-            (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
+            (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
   def : Pat<(f64 (fceil FR64:$src)),
-            (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
+            (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
   def : Pat<(f32 (frint FR32:$src)),
             (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
   def : Pat<(f64 (frint FR64:$src)),
             (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
   def : Pat<(f32 (ftrunc FR32:$src)),
-            (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
+            (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
   def : Pat<(f64 (ftrunc FR64:$src)),
-            (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
+            (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
 }
 
 let Predicates = [HasAVX] in {
   def : Pat<(v4f32 (ffloor VR128:$src)),
-            (VROUNDPSr VR128:$src, (i32 0x1))>;
+            (VROUNDPSr VR128:$src, (i32 0x9))>;
   def : Pat<(v4f32 (fnearbyint VR128:$src)),
             (VROUNDPSr VR128:$src, (i32 0xC))>;
   def : Pat<(v4f32 (fceil VR128:$src)),
-            (VROUNDPSr VR128:$src, (i32 0x2))>;
+            (VROUNDPSr VR128:$src, (i32 0xA))>;
   def : Pat<(v4f32 (frint VR128:$src)),
             (VROUNDPSr VR128:$src, (i32 0x4))>;
   def : Pat<(v4f32 (ftrunc VR128:$src)),
-            (VROUNDPSr VR128:$src, (i32 0x3))>;
+            (VROUNDPSr VR128:$src, (i32 0xB))>;
 
   def : Pat<(v2f64 (ffloor VR128:$src)),
-            (VROUNDPDr VR128:$src, (i32 0x1))>;
+            (VROUNDPDr VR128:$src, (i32 0x9))>;
   def : Pat<(v2f64 (fnearbyint VR128:$src)),
             (VROUNDPDr VR128:$src, (i32 0xC))>;
   def : Pat<(v2f64 (fceil VR128:$src)),
-            (VROUNDPDr VR128:$src, (i32 0x2))>;
+            (VROUNDPDr VR128:$src, (i32 0xA))>;
   def : Pat<(v2f64 (frint VR128:$src)),
             (VROUNDPDr VR128:$src, (i32 0x4))>;
   def : Pat<(v2f64 (ftrunc VR128:$src)),
-            (VROUNDPDr VR128:$src, (i32 0x3))>;
+            (VROUNDPDr VR128:$src, (i32 0xB))>;
 
   def : Pat<(v8f32 (ffloor VR256:$src)),
-            (VROUNDYPSr VR256:$src, (i32 0x1))>;
+            (VROUNDYPSr VR256:$src, (i32 0x9))>;
   def : Pat<(v8f32 (fnearbyint VR256:$src)),
             (VROUNDYPSr VR256:$src, (i32 0xC))>;
   def : Pat<(v8f32 (fceil VR256:$src)),
-            (VROUNDYPSr VR256:$src, (i32 0x2))>;
+            (VROUNDYPSr VR256:$src, (i32 0xA))>;
   def : Pat<(v8f32 (frint VR256:$src)),
             (VROUNDYPSr VR256:$src, (i32 0x4))>;
   def : Pat<(v8f32 (ftrunc VR256:$src)),
-            (VROUNDYPSr VR256:$src, (i32 0x3))>;
+            (VROUNDYPSr VR256:$src, (i32 0xB))>;
 
   def : Pat<(v4f64 (ffloor VR256:$src)),
-            (VROUNDYPDr VR256:$src, (i32 0x1))>;
+            (VROUNDYPDr VR256:$src, (i32 0x9))>;
   def : Pat<(v4f64 (fnearbyint VR256:$src)),
             (VROUNDYPDr VR256:$src, (i32 0xC))>;
   def : Pat<(v4f64 (fceil VR256:$src)),
-            (VROUNDYPDr VR256:$src, (i32 0x2))>;
+            (VROUNDYPDr VR256:$src, (i32 0xA))>;
   def : Pat<(v4f64 (frint VR256:$src)),
             (VROUNDYPDr VR256:$src, (i32 0x4))>;
   def : Pat<(v4f64 (ftrunc VR256:$src)),
-            (VROUNDYPDr VR256:$src, (i32 0x3))>;
+            (VROUNDYPDr VR256:$src, (i32 0xB))>;
 }
 
 defm ROUND  : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
                                memopv4f32, memopv2f64,
                                int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
 let Constraints = "$src1 = $dst" in
 defm ROUND  : sse41_fp_binop_rm<0x0A, 0x0B, "round",
                                int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
 
 let Predicates = [UseSSE41] in {
   def : Pat<(ffloor FR32:$src),
-            (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
+            (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
   def : Pat<(f64 (ffloor FR64:$src)),
-            (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
+            (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
   def : Pat<(f32 (fnearbyint FR32:$src)),
             (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
   def : Pat<(f64 (fnearbyint FR64:$src)),
             (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
   def : Pat<(f32 (fceil FR32:$src)),
-            (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
+            (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
   def : Pat<(f64 (fceil FR64:$src)),
-            (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
+            (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
   def : Pat<(f32 (frint FR32:$src)),
             (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
   def : Pat<(f64 (frint FR64:$src)),
             (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
   def : Pat<(f32 (ftrunc FR32:$src)),
-            (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
+            (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
   def : Pat<(f64 (ftrunc FR64:$src)),
-            (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
+            (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
 
   def : Pat<(v4f32 (ffloor VR128:$src)),
-            (ROUNDPSr VR128:$src, (i32 0x1))>;
+            (ROUNDPSr VR128:$src, (i32 0x9))>;
   def : Pat<(v4f32 (fnearbyint VR128:$src)),
             (ROUNDPSr VR128:$src, (i32 0xC))>;
   def : Pat<(v4f32 (fceil VR128:$src)),
-            (ROUNDPSr VR128:$src, (i32 0x2))>;
+            (ROUNDPSr VR128:$src, (i32 0xA))>;
   def : Pat<(v4f32 (frint VR128:$src)),
             (ROUNDPSr VR128:$src, (i32 0x4))>;
   def : Pat<(v4f32 (ftrunc VR128:$src)),
-            (ROUNDPSr VR128:$src, (i32 0x3))>;
+            (ROUNDPSr VR128:$src, (i32 0xB))>;
 
   def : Pat<(v2f64 (ffloor VR128:$src)),
-            (ROUNDPDr VR128:$src, (i32 0x1))>;
+            (ROUNDPDr VR128:$src, (i32 0x9))>;
   def : Pat<(v2f64 (fnearbyint VR128:$src)),
             (ROUNDPDr VR128:$src, (i32 0xC))>;
   def : Pat<(v2f64 (fceil VR128:$src)),
-            (ROUNDPDr VR128:$src, (i32 0x2))>;
+            (ROUNDPDr VR128:$src, (i32 0xA))>;
   def : Pat<(v2f64 (frint VR128:$src)),
             (ROUNDPDr VR128:$src, (i32 0x4))>;
   def : Pat<(v2f64 (ftrunc VR128:$src)),
-            (ROUNDPDr VR128:$src, (i32 0x3))>;
+            (ROUNDPDr VR128:$src, (i32 0xB))>;
 }
 
 //===----------------------------------------------------------------------===//
 // SSE4.1 - Packed Bit Test
 //===----------------------------------------------------------------------===//
 
 // ptest instruction we'll lower to this in X86ISelLowering primarily from
 // the intel intrinsic that corresponds to this.

test/CodeGen/AArch64/arm64-rounding.ll

-; RUN: llc -O3 < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK-INEXACT
-; RUN: llc -O3 < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECK-FAST
+; RUN: llc -O3 < %s -mtriple=arm64 | FileCheck %s
 
-; CHECK-INEXACT-LABEL: test1:
-; CHECK-INEXACT-DAG: frintm
-; CHECK-INEXACT-DAG: frintx
-
-; CHECK-FAST-LABEL: test1:
-; CHECK-FAST: frintm
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test1:
+; CHECK: frintm
+; CHECK-NOT: frintx
 define float @test1(float %a) #0 {
 entry:
   %call = tail call float @floorf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @floorf(float) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test2:
-; CHECK-INEXACT: frintm
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test2:
-; CHECK-FAST: frintm
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test2:
+; CHECK: frintm
+; CHECK-NOT: frintx
 define double @test2(double %a) #0 {
 entry:
   %call = tail call double @floor(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @floor(double) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test3:
-; CHECK-INEXACT: frinti
-
-; CHECK-FAST-LABEL: test3:
-; CHECK-FAST: frinti
+; CHECK-LABEL: test3:
+; CHECK: frinti
 define float @test3(float %a) #0 {
 entry:
   %call = tail call float @nearbyintf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @nearbyintf(float) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test4:
-; CHECK-INEXACT: frinti
-
-; CHECK-FAST-LABEL: test4:
-; CHECK-FAST: frinti
+; CHECK-LABEL: test4:
+; CHECK: frinti
 define double @test4(double %a) #0 {
 entry:
   %call = tail call double @nearbyint(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @nearbyint(double) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test5:
-; CHECK-INEXACT: frintp
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test5:
-; CHECK-FAST: frintp
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test5:
+; CHECK: frintp
+; CHECK-NOT: frintx
 define float @test5(float %a) #0 {
 entry:
   %call = tail call float @ceilf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @ceilf(float) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test6:
-; CHECK-INEXACT: frintp
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test6:
-; CHECK-FAST: frintp
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test6:
+; CHECK: frintp
+; CHECK-NOT: frintx
 define double @test6(double %a) #0 {
 entry:
   %call = tail call double @ceil(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @ceil(double) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test7:
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test7:
-; CHECK-FAST: frintx
+; CHECK-LABEL: test7:
+; CHECK: frintx
 define float @test7(float %a) #0 {
 entry:
   %call = tail call float @rintf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @rintf(float) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test8:
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test8:
-; CHECK-FAST: frintx
+; CHECK-LABEL: test8:
+; CHECK: frintx
 define double @test8(double %a) #0 {
 entry:
   %call = tail call double @rint(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @rint(double) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test9:
-; CHECK-INEXACT: frintz
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test9:
-; CHECK-FAST: frintz
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test9:
+; CHECK: frintz
+; CHECK-NOT: frintx
 define float @test9(float %a) #0 {
 entry:
   %call = tail call float @truncf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @truncf(float) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test10:
-; CHECK-INEXACT: frintz
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test10:
-; CHECK-FAST: frintz
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test10:
+; CHECK: frintz
+; CHECK-NOT: frintx
 define double @test10(double %a) #0 {
 entry:
   %call = tail call double @trunc(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @trunc(double) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test11:
-; CHECK-INEXACT: frinta
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test11:
-; CHECK-FAST: frinta
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test11:
+; CHECK: frinta
+; CHECK-NOT: frintx
 define float @test11(float %a) #0 {
 entry:
   %call = tail call float @roundf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @roundf(float %a) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test12:
-; CHECK-INEXACT: frinta
-; CHECK-INEXACT: frintx
-
-; CHECK-FAST-LABEL: test12:
-; CHECK-FAST: frinta
-; CHECK-FAST-NOT: frintx
+; CHECK-LABEL: test12:
+; CHECK: frinta
+; CHECK-NOT: frintx
 define double @test12(double %a) #0 {
 entry:
   %call = tail call double @round(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @round(double %a) nounwind readnone
 
-; CHECK-INEXACT-LABEL: test13:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frintm
-
-; CHECK-FAST-LABEL: test13:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frintm
+; CHECK-LABEL: test13:
+; CHECK-NOT: frintx
+; CHECK: frintm
 define float @test13(float %a) #1 {
 entry:
   %call = tail call float @floorf(float %a) nounwind readnone
   ret float %call
 }
 
-; CHECK-INEXACT-LABEL: test14:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frintm
-
-; CHECK-FAST-LABEL: test14:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frintm
+; CHECK-LABEL: test14:
+; CHECK-NOT: frintx
+; CHECK: frintm
 define double @test14(double %a) #1 {
 entry:
   %call = tail call double @floor(double %a) nounwind readnone
   ret double %call
 }
 
-; CHECK-INEXACT-LABEL: test15:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frintp
-
-; CHECK-FAST-LABEL: test15:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frintp
+; CHECK-LABEL: test15:
+; CHECK-NOT: frintx
+; CHECK: frintp
 define float @test15(float %a) #1 {
 entry:
   %call = tail call float @ceilf(float %a) nounwind readnone
   ret float %call
 }
 
-; CHECK-INEXACT-LABEL: test16:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frintp
-
-; CHECK-FAST-LABEL: test16:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frintp
+; CHECK-LABEL: test16:
+; CHECK-NOT: frintx
+; CHECK: frintp
 define double @test16(double %a) #1 {
 entry:
   %call = tail call double @ceil(double %a) nounwind readnone
   ret double %call
 }
 
-; CHECK-INEXACT-LABEL: test17:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frintz
-
-; CHECK-FAST-LABEL: test17:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frintz
+; CHECK-LABEL: test17:
+; CHECK-NOT: frintx
+; CHECK: frintz
 define float @test17(float %a) #1 {
 entry:
   %call = tail call float @truncf(float %a) nounwind readnone
   ret float %call
 }
 
-; CHECK-INEXACT-LABEL: test18:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frintz
-
-; CHECK-FAST-LABEL: test18:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frintz
+; CHECK-LABEL: test18:
+; CHECK-NOT: frintx
+; CHECK: frintz
 define double @test18(double %a) #1 {
 entry:
   %call = tail call double @trunc(double %a) nounwind readnone
   ret double %call
 }
 
-; CHECK-INEXACT-LABEL: test19:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frinta
-
-; CHECK-FAST-LABEL: test19:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frinta
+; CHECK-LABEL: test19:
+; CHECK-NOT: frintx
+; CHECK: frinta
 define float @test19(float %a) #1 {
 entry:
   %call = tail call float @roundf(float %a) nounwind readnone
   ret float %call
 }
 
-; CHECK-INEXACT-LABEL: test20:
-; CHECK-INEXACT-NOT: frintx
-; CHECK-INEXACT: frinta
-
-; CHECK-FAST-LABEL: test20:
-; CHECK-FAST-NOT: frintx
-; CHECK-FAST: frinta
+; CHECK-LABEL: test20:
+; CHECK-NOT: frintx
+; CHECK: frinta
 define double @test20(double %a) #1 {
 entry:
   %call = tail call double @round(double %a) nounwind readnone
   ret double %call
 }
 
-
-
 attributes #0 = { nounwind }
 attributes #1 = { nounwind "unsafe-fp-math"="true" }

test/CodeGen/AArch64/round-conv.ll

-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK-INEXACT
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
-; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECK-FAST
-
-; CHECK-INEXACT-LABEL: testmsws:
-; CHECK-INEXACT: fcvtms w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testmsws:
-; CHECK-FAST: fcvtms w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; RUN: llc < %s -mtriple=arm64 | FileCheck %s
+
+; CHECK-LABEL: testmsws:
+; CHECK: fcvtms w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testmsws(float %a) {
 entry:
   %call = call float @floorf(float %a) nounwind readnone
   %conv = fptosi float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmsxs:
-; CHECK-INEXACT: fcvtms x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testmsxs:
-; CHECK-FAST: fcvtms x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testmsxs:
+; CHECK: fcvtms x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testmsxs(float %a) {
 entry:
   %call = call float @floorf(float %a) nounwind readnone
   %conv = fptosi float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmswd:
-; CHECK-INEXACT: fcvtms w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testmswd:
-; CHECK-FAST: fcvtms w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testmswd:
+; CHECK: fcvtms w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testmswd(double %a) {
 entry:
   %call = call double @floor(double %a) nounwind readnone
   %conv = fptosi double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmsxd:
-; CHECK-INEXACT: fcvtms x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testmsxd:
-; CHECK-FAST: fcvtms x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testmsxd:
+; CHECK: fcvtms x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testmsxd(double %a) {
 entry:
   %call = call double @floor(double %a) nounwind readnone
   %conv = fptosi double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmuws:
-; CHECK-INEXACT: fcvtmu w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testmuws:
-; CHECK-FAST: fcvtmu w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testmuws:
+; CHECK: fcvtmu w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testmuws(float %a) {
 entry:
   %call = call float @floorf(float %a) nounwind readnone
   %conv = fptoui float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmuxs:
-; CHECK-INEXACT: fcvtmu x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testmuxs:
-; CHECK-FAST: fcvtmu x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testmuxs:
+; CHECK: fcvtmu x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testmuxs(float %a) {
 entry:
   %call = call float @floorf(float %a) nounwind readnone
   %conv = fptoui float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmuwd:
-; CHECK-INEXACT: fcvtmu w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testmuwd:
-; CHECK-FAST: fcvtmu w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testmuwd:
+; CHECK: fcvtmu w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testmuwd(double %a) {
 entry:
   %call = call double @floor(double %a) nounwind readnone
   %conv = fptoui double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testmuxd:
-; CHECK-INEXACT: fcvtmu x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testmuxd:
-; CHECK-FAST: fcvtmu x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testmuxd:
+; CHECK: fcvtmu x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testmuxd(double %a) {
 entry:
   %call = call double @floor(double %a) nounwind readnone
   %conv = fptoui double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpsws:
-; CHECK-INEXACT: fcvtps w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testpsws:
-; CHECK-FAST: fcvtps w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testpsws:
+; CHECK: fcvtps w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testpsws(float %a) {
 entry:
   %call = call float @ceilf(float %a) nounwind readnone
   %conv = fptosi float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpsxs:
-; CHECK-INEXACT: fcvtps x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testpsxs:
-; CHECK-FAST: fcvtps x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testpsxs:
+; CHECK: fcvtps x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testpsxs(float %a) {
 entry:
   %call = call float @ceilf(float %a) nounwind readnone
   %conv = fptosi float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpswd:
-; CHECK-INEXACT: fcvtps w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testpswd:
-; CHECK-FAST: fcvtps w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testpswd:
+; CHECK: fcvtps w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testpswd(double %a) {
 entry:
   %call = call double @ceil(double %a) nounwind readnone
   %conv = fptosi double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpsxd:
-; CHECK-INEXACT: fcvtps x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testpsxd:
-; CHECK-FAST: fcvtps x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testpsxd:
+; CHECK: fcvtps x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testpsxd(double %a) {
 entry:
   %call = call double @ceil(double %a) nounwind readnone
   %conv = fptosi double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpuws:
-; CHECK-INEXACT: fcvtpu w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testpuws:
-; CHECK-FAST: fcvtpu w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testpuws:
+; CHECK: fcvtpu w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testpuws(float %a) {
 entry:
   %call = call float @ceilf(float %a) nounwind readnone
   %conv = fptoui float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpuxs:
-; CHECK-INEXACT: fcvtpu x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testpuxs:
-; CHECK-FAST: fcvtpu x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testpuxs:
+; CHECK: fcvtpu x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testpuxs(float %a) {
 entry:
   %call = call float @ceilf(float %a) nounwind readnone
   %conv = fptoui float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpuwd:
-; CHECK-INEXACT: fcvtpu w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testpuwd:
-; CHECK-FAST: fcvtpu w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testpuwd:
+; CHECK: fcvtpu w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testpuwd(double %a) {
 entry:
   %call = call double @ceil(double %a) nounwind readnone
   %conv = fptoui double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testpuxd:
-; CHECK-INEXACT: fcvtpu x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testpuxd:
-; CHECK-FAST: fcvtpu x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testpuxd:
+; CHECK: fcvtpu x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testpuxd(double %a) {
 entry:
   %call = call double @ceil(double %a) nounwind readnone
   %conv = fptoui double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzsws:
-; CHECK-INEXACT: fcvtzs w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testzsws:
-; CHECK-FAST: fcvtzs w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testzsws:
+; CHECK: fcvtzs w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testzsws(float %a) {
 entry:
   %call = call float @truncf(float %a) nounwind readnone
   %conv = fptosi float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzsxs:
-; CHECK-INEXACT: fcvtzs x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testzsxs:
-; CHECK-FAST: fcvtzs x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testzsxs:
+; CHECK: fcvtzs x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testzsxs(float %a) {
 entry:
   %call = call float @truncf(float %a) nounwind readnone
   %conv = fptosi float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzswd:
-; CHECK-INEXACT: fcvtzs w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testzswd:
-; CHECK-FAST: fcvtzs w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testzswd:
+; CHECK: fcvtzs w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testzswd(double %a) {
 entry:
   %call = call double @trunc(double %a) nounwind readnone
   %conv = fptosi double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzsxd:
-; CHECK-INEXACT: fcvtzs x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testzsxd:
-; CHECK-FAST: fcvtzs x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testzsxd:
+; CHECK: fcvtzs x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testzsxd(double %a) {
 entry:
   %call = call double @trunc(double %a) nounwind readnone
   %conv = fptosi double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzuws:
-; CHECK-INEXACT: fcvtzu w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testzuws:
-; CHECK-FAST: fcvtzu w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testzuws:
+; CHECK: fcvtzu w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testzuws(float %a) {
 entry:
   %call = call float @truncf(float %a) nounwind readnone
   %conv = fptoui float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzuxs:
-; CHECK-INEXACT: fcvtzu x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testzuxs:
-; CHECK-FAST: fcvtzu x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testzuxs:
+; CHECK: fcvtzu x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testzuxs(float %a) {
 entry:
   %call = call float @truncf(float %a) nounwind readnone
   %conv = fptoui float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzuwd:
-; CHECK-INEXACT: fcvtzu w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testzuwd:
-; CHECK-FAST: fcvtzu w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testzuwd:
+; CHECK: fcvtzu w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testzuwd(double %a) {
 entry:
   %call = call double @trunc(double %a) nounwind readnone
   %conv = fptoui double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testzuxd:
-; CHECK-INEXACT: fcvtzu x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testzuxd:
-; CHECK-FAST: fcvtzu x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testzuxd:
+; CHECK: fcvtzu x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testzuxd(double %a) {
 entry:
   %call = call double @trunc(double %a) nounwind readnone
   %conv = fptoui double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testasws:
-; CHECK-INEXACT: fcvtas w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testasws:
-; CHECK-FAST: fcvtas w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testasws:
+; CHECK: fcvtas w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testasws(float %a) {
 entry:
   %call = call float @roundf(float %a) nounwind readnone
   %conv = fptosi float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testasxs:
-; CHECK-INEXACT: fcvtas x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testasxs:
-; CHECK-FAST: fcvtas x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testasxs:
+; CHECK: fcvtas x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testasxs(float %a) {
 entry:
   %call = call float @roundf(float %a) nounwind readnone
   %conv = fptosi float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testaswd:
-; CHECK-INEXACT: fcvtas w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testaswd:
-; CHECK-FAST: fcvtas w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testaswd:
+; CHECK: fcvtas w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testaswd(double %a) {
 entry:
   %call = call double @round(double %a) nounwind readnone
   %conv = fptosi double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testasxd:
-; CHECK-INEXACT: fcvtas x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testasxd:
-; CHECK-FAST: fcvtas x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testasxd:
+; CHECK: fcvtas x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testasxd(double %a) {
 entry:
   %call = call double @round(double %a) nounwind readnone
   %conv = fptosi double %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testauws:
-; CHECK-INEXACT: fcvtau w0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testauws:
-; CHECK-FAST: fcvtau w0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testauws:
+; CHECK: fcvtau w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i32 @testauws(float %a) {
 entry:
   %call = call float @roundf(float %a) nounwind readnone
   %conv = fptoui float %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testauxs:
-; CHECK-INEXACT: fcvtau x0, s0
-; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
-
-; CHECK-FAST-LABEL: testauxs:
-; CHECK-FAST: fcvtau x0, s0
-; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+; CHECK-LABEL: testauxs:
+; CHECK: fcvtau x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
 define i64 @testauxs(float %a) {
 entry:
   %call = call float @roundf(float %a) nounwind readnone
   %conv = fptoui float %call to i64
   ret i64 %conv
 }
 
-; CHECK-INEXACT-LABEL: testauwd:
-; CHECK-INEXACT: fcvtau w0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testauwd:
-; CHECK-FAST: fcvtau w0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testauwd:
+; CHECK: fcvtau w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i32 @testauwd(double %a) {
 entry:
   %call = call double @round(double %a) nounwind readnone
   %conv = fptoui double %call to i32
   ret i32 %conv
 }
 
-; CHECK-INEXACT-LABEL: testauxd:
-; CHECK-INEXACT: fcvtau x0, d0
-; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
-
-; CHECK-FAST-LABEL: testauxd:
-; CHECK-FAST: fcvtau x0, d0
-; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+; CHECK-LABEL: testauxd:
+; CHECK: fcvtau x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
 define i64 @testauxd(double %a) {
 entry:
   %call = call double @round(double %a) nounwind readnone
   %conv = fptoui double %call to i64
   ret i64 %conv
 }
 
-
 declare float @floorf(float) nounwind readnone
 declare double @floor(double) nounwind readnone
 declare float @ceilf(float) nounwind readnone
 declare double @ceil(double) nounwind readnone
 declare float @truncf(float) nounwind readnone
 declare double @trunc(double) nounwind readnone
 declare float @roundf(float) nounwind readnone
 declare double @round(double) nounwind readnone

test/CodeGen/X86/avx-cvt.ll

; CHECK-NEXT:    retq
   %res = call double @llvm.nearbyint.f64(double %a)
   ret double %res
 }
 declare double @llvm.nearbyint.f64(double %p)
 
 define float @floor_f32(float %a) {
 ; CHECK-LABEL: floor_f32:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vroundss $1, %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vroundss $9, %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %res = call float @llvm.floor.f32(float %a)
   ret float %res
 }
 declare float @llvm.floor.f32(float %p)
 
 

test/CodeGen/X86/floor-soft-float.ll

 ; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
 ; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx,+soft-float | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
 
 target triple = "x86_64-unknown-linux-gnu"
 
 declare float @llvm.floor.f32(float)
 
 ; CHECK-SOFT-FLOAT: callq floorf
-; CHECK-HARD-FLOAT: roundss $1, %xmm0, %xmm0
+; CHECK-HARD-FLOAT: roundss $9, %xmm0, %xmm0
 define float @myfloor(float %a) {
   %val = tail call float @llvm.floor.f32(float %a)
   ret float %val
 }

test/CodeGen/X86/rounding-ops.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse4.1 | FileCheck -check-prefix=CHECK-SSE %s
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx | FileCheck -check-prefix=CHECK-AVX %s
 
 define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-SSE-LABEL: test1:
-; CHECK-SSE: roundss $1
+; CHECK-SSE: roundss $9
 
 ; CHECK-AVX-LABEL: test1:
-; CHECK-AVX: vroundss $1
+; CHECK-AVX: vroundss $9
 }
 
 declare float @floorf(float) nounwind readnone
 
 define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-SSE-LABEL: test2:
-; CHECK-SSE: roundsd $1
+; CHECK-SSE: roundsd $9
 
 ; CHECK-AVX-LABEL: test2:
-; CHECK-AVX: vroundsd $1
+; CHECK-AVX: vroundsd $9
 }
 
 declare double @floor(double) nounwind readnone
 
 define float @test3(float %x) nounwind  {
   %call = tail call float @nearbyintf(float %x) nounwind readnone
   ret float %call
 

 
 declare double @nearbyint(double) nounwind readnone
 
 define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-SSE-LABEL: test5:
-; CHECK-SSE: roundss $2
+; CHECK-SSE: roundss $10
 
 ; CHECK-AVX-LABEL: test5:
-; CHECK-AVX: vroundss $2
+; CHECK-AVX: vroundss $10
 }
 
 declare float @ceilf(float) nounwind readnone
 
 define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-SSE-LABEL: test6:
-; CHECK-SSE: roundsd $2
+; CHECK-SSE: roundsd $10
 
 ; CHECK-AVX-LABEL: test6:
-; CHECK-AVX: vroundsd $2
+; CHECK-AVX: vroundsd $10
 }
 
 declare double @ceil(double) nounwind readnone
 
 define float @test7(float %x) nounwind  {
   %call = tail call float @rintf(float %x) nounwind readnone
   ret float %call
 

 
 declare double @rint(double) nounwind readnone
 
 define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-SSE-LABEL: test9:
-; CHECK-SSE: roundss $3
+; CHECK-SSE: roundss $11
 
 ; CHECK-AVX-LABEL: test9:
-; CHECK-AVX: vroundss $3
+; CHECK-AVX: vroundss $11
 }
 
 declare float @truncf(float) nounwind readnone
 
 define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-SSE-LABEL: test10:
-; CHECK-SSE: roundsd $3
+; CHECK-SSE: roundsd $11
 
 ; CHECK-AVX-LABEL: test10:
-; CHECK-AVX: vroundsd $3
+; CHECK-AVX: vroundsd $11
 }
 
 declare double @trunc(double) nounwind readnone

test/CodeGen/X86/stack-folding-fp-avx1.ll

define <8 x float> @stack_fold_roundps_ymm(<8 x float> %a0) {
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
   %2 = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7)
   ret <8 x float> %2
 }
 declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readnone
 
 define double @stack_fold_roundsd(double %a0) optsize {
   ;CHECK-LABEL: stack_fold_roundsd
-  ;CHECK:       vroundsd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  ;CHECK:       vroundsd $9, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
   %2 = call double @llvm.floor.f64(double %a0)
   ret double %2
 }
 declare double @llvm.floor.f64(double) nounwind readnone
 
 ; TODO stack_fold_roundsd_int
 declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
 
 define float @stack_fold_roundss(float %a0) optsize {
   ;CHECK-LABEL: stack_fold_roundss
-  ;CHECK:       vroundss $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  ;CHECK:       vroundss $9, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
   %2 = call float @llvm.floor.f32(float %a0)
   ret float %2
 }
 declare float @llvm.floor.f32(float) nounwind readnone
 
 ; TODO stack_fold_roundss_int
 declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone

test/CodeGen/X86/stack-folding-fp-sse42.ll

define <4 x float> @stack_fold_roundps(<4 x float> %a0) {
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
   %2 = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7)
   ret <4 x float> %2
 }
 declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
 
 define double @stack_fold_roundsd(double %a0) optsize {
   ;CHECK-LABEL: stack_fold_roundsd
-  ;CHECK:       roundsd $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
+  ;CHECK:       roundsd $9, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
   %2 = call double @llvm.floor.f64(double %a0)
   ret double %2
 }
 declare double @llvm.floor.f64(double) nounwind readnone
 
 ; TODO stack_fold_roundsd_int
 declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
 
 define float @stack_fold_roundss(float %a0) minsize {
   ;CHECK-LABEL: stack_fold_roundss
-  ;CHECK:       roundss $1, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
+  ;CHECK:       roundss $9, {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
   %2 = call float @llvm.floor.f32(float %a0)
   ret float %2
 }
 declare float @llvm.floor.f32(float) nounwind readnone
 
 ; TODO stack_fold_roundss_int
 declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone